CN109580975B - Speed detector, processing circuit and chip based on PWM signal - Google Patents
Speed detector, processing circuit and chip based on PWM signal Download PDFInfo
- Publication number
- CN109580975B CN109580975B CN201811501749.9A CN201811501749A CN109580975B CN 109580975 B CN109580975 B CN 109580975B CN 201811501749 A CN201811501749 A CN 201811501749A CN 109580975 B CN109580975 B CN 109580975B
- Authority
- CN
- China
- Prior art keywords
- output
- pwm
- clock
- signal
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P3/00—Measuring linear or angular speed; Measuring differences of linear or angular speeds
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02K—DYNAMO-ELECTRIC MACHINES
- H02K11/00—Structural association of dynamo-electric machines with electric components or with devices for shielding, monitoring or protection
- H02K11/20—Structural association of dynamo-electric machines with electric components or with devices for shielding, monitoring or protection for measuring, monitoring, testing, protecting or switching
Abstract
The invention discloses a speed detector, a processing circuit and a chip based on PWM signals, wherein the speed detector is applied to providing pulse sampling speed for an external motor system and comprises a rising edge detection circuit, a pulse width counter and a median average module; the clock input end of the rising edge detection circuit is connected with the clock input end of the pulse width counter, the output end of the rising edge detection circuit is connected with the reset end (reset) of the pulse width counter, and the data output end of the pulse width counter is connected with the data input end of the median average module. The speed detector expands the functions of the traditional PWM signal output circuit and improves the speed measurement precision of pulse signals.
Description
Technical Field
The invention relates to the technical field of signal modulation, in particular to a speed detector, a processing circuit and a chip based on PWM signals.
Background
PWM (Pulse Width Modulation) technology is widely applied in various fields such as industrial automation, robots, precise numerical control machine tools, aerospace and the like. The servo motor control system is required to generate PWM signals with variable duty ratio to drive power devices such as IGBT, IPM and the like; and a position control instruction can be transmitted between the motion control card and the servo driver through a PWM signal with variable frequency. PWM and PFM are two control modes of DC/DC switches, and such techniques are commonly used for control of some analog circuits or peripheral motors. As the integration of ICs increases. Most of the PWM circuits in the market have various implementation manners, but these circuits generally have single functions, no speed measurement function, and the like, and do not utilize sampling feedback to control the rotation speed of the motor system.
Disclosure of Invention
To overcome the above problems, the present invention proposes a speed detector based on PWM signals.
A speed detector based on a PWM signal, which is applied to provide a pulse sampling speed for an external motor system, and comprises a rising edge detection circuit, a pulse width counter and a median average module; the clock input end of the rising edge detection circuit is connected with the clock input end of the pulse width counter, the output end of the rising edge detection circuit is connected with the reset end (reset) of the pulse width counter, the data output end of the pulse width counter is connected with the data input end of the median average module, the data output end of the median average module is used as the output end of the speed detector, and the input end of the rising edge detection circuit is used as the data input end of the speed detector.
Further, the rising edge detection circuit comprises a D trigger and an AND gate, wherein the input end (D) of the D trigger is connected with one input end of the AND gate, and the inverting output end of the D triggerThe other input end of the AND gate is connected; the clock end of the pulse width counter is connected with the clock end of the D trigger, the output end of the AND gate is used as the output end of the rising edge detection circuit, and the input end of the D trigger is used as the input end of the rising edge detection circuit.
Further, the bit width number power of the pulse width counter of 2 is greater than the ratio of the signal frequency of the clock input of the pulse width counter to the signal frequency of the input of the D flip-flop.
A processing circuit of a PWM signal, the processing circuit being applied to regulate an external motor system, the processing circuit comprising a PWM sampling detection module and a PWM generation module; the clock input end of the PWM sampling detection module is connected with the clock input end of the PWM generation module; the PWM sampling detection module comprises a step length counting sub-module, a signal prescaler, a filter, a first time Zhong Yu frequency divider and the speed detector, wherein the signal input end of the filter is used as the signal input end of the PWM sampling detection module, and the speed signal output end of the speed detector is used as the output end of the PWM sampling detection module; the connection relation inside the PWM sampling detection module is as follows: the signal output end of the filter is connected with the data input end of the step length counting submodule and the clock input end of the signal prescaler at the same time, and the clock output end of the signal prescaler is connected with the data input end of the speed detector; the clock input end of the speed detector is connected with the clock output end of the first time Zhong Yu frequency divider; the PWM generation module comprises a second clock prescaler and a PWM signal generator, and the connection relation inside the module is as follows: the clock output end of the second clock prescaler is connected with the data input end of the PWM signal generator, the clock input end of the second clock prescaler is used as the clock input end of the PWM generating module, and the data output end of the PWM signal generator is used as the output end of the PWM generating module.
Further, the filter comprises a first preset number of D triggers and a comparison output module, the first preset number of D triggers form a shift register with a first preset number of bits, clock ends of the first preset number of D triggers are connected to clock input ends of the filter, output ends (Q) of the first preset number of D triggers are respectively connected to first preset number of data input ends of the comparison output module, the data input ends of the shift register serve as signal input ends of the filter, and the data output ends of the comparison output module serve as signal output ends of the filter.
Further, in the shift register, an output terminal (Q) of each D flip-flop except for the rightmost D flip-flop is connected to an input terminal (D) of the right one D flip-flop, and the output terminal (Q) of the rightmost D flip-flop is connected to one data input terminal of the comparison output module.
Further, in the shift register, an output terminal (Q) of each D flip-flop except for the leftmost D flip-flop is connected to an input terminal (D) of the left one D flip-flop, and the output terminal (Q) of the leftmost D flip-flop is connected to one data input terminal of the comparison output module.
Further, the first preset number is set to 6, so that the filter filters out level jitter of less than 5 clock cycles of the input PWM signal to be processed (pwm_in) as glitches, wherein the clock cycles are pulse cycles of the jitter level of the PWM signal to be processed (pwm_in).
Further, the step counting sub-module comprises a step counter and a direction register, the output end of the direction register is connected with the enabling end of the step counter, the counting output end of the step counter is used as the output end of the step counting sub-module, and the counting input end of the step counter is used as the data input end of the step counting sub-module.
Further, the PWM signal generator includes an output frequency divider and a comparator, a clock output terminal of the output frequency divider is connected to a comparison input terminal of the comparator, an input terminal of the output frequency divider is used as a data input terminal of the PWM signal generator, and an output terminal of the comparator is used as a data output terminal of the PWM signal generator.
A chip comprising the processing circuit inside.
Compared with the prior art, the speed detector counts the pulse width of the signal detected by sampling through the counter to measure the pulse width of the input PWM signal, and carries out median average processing on the measured pulse width value, so that the optimized pulse speed measured value based on the input PWM signal is output, the function of a traditional PWM signal output circuit is expanded, and the speed measurement precision of the pulse signal is improved.
Drawings
Fig. 1 is a schematic diagram of a speed detector based on PWM signals according to an embodiment of the present invention.
Fig. 2 is a pulse width sampling timing chart of an input signal by a speed detector according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a processing circuit of a PWM signal according to an embodiment of the present invention.
Fig. 4 is a circuit schematic of a filter according to an embodiment of the invention.
Fig. 5 is a circuit diagram of a PWM signal generator according to an embodiment of the present invention.
Detailed Description
The following is a further description of embodiments of the invention, taken in conjunction with the accompanying drawings: as shown in fig. 1, an embodiment of the present invention provides a speed detector based on a PWM signal, as shown in fig. 1, the speed detector includes a rising edge detection circuit, a pulse width counter, and a median average module, where a clock input end of the rising edge detection circuit is connected to a clock input end of the pulse width counter, an output end of the rising edge detection circuit is connected to a reset end (reset) of the pulse width counter, and a data output end of the pulse width counter is connected to a data input end of the median average module. The data output of the median averaging module is used as the output of the speed detector. The input of the rising edge detection circuit serves as the data input of the speed detector. The speed detector is used to measure the speed value of the motor rotation by measuring the period of the PWM signal pwm_in to be processed, IN practice the time width between two rising edges of the PWM signal pwm_in to be processed.
The rising edge detection circuit comprises a D trigger and an AND gate, wherein the input end D of the D trigger is connected with one input end of the AND gate, and the inverting output end of the D triggerThe other input end of the AND gate is connected; the clock input end of the pulse width counter is connected with the clock end of the D trigger, wherein the input end of the D trigger is used as the input end of the rising edge detection circuit, and the clock end of the D trigger is used as the clock input end of the rising edge detection circuit. The rising edge detection circuit is connected with a reset end reset of the pulse width counter through an output end of the AND gate. The input end D of the D trigger is used for receiving an input PWM signal Encoder1 subjected to filtering frequency division processing; the clock end of the D trigger is used for receiving a frequency division clock signal Clk_div1, and the frequency division clock signal Clk_div1 is obtained by frequency division of an externally input high-frequency clock signal CLK_US. When the input PWM signal Encoder1 at the input end D of the D flip-flop is a low level signal at the first moment, the D flip-flop latches the low level signal of the input PWM signal Encoder1 at the first moment, and after one clock period of the frequency division clock signal Clk_div1, the inverting output end of the D flip-flop is>Outputting a high level signal, if the input end D of the D trigger becomes a high level signal at the same time, namely, the two input ends of the AND gate are simultaneously high level signals, the rising edge detection circuit outputs the high level signal through the AND gate, and at the moment, the input PWM signal Encoder1 can be judged to be a rising edge signal and is output to the complex pulse width counterAnd a bit end reset, wherein the output end of the AND gate is used as the output end of the rising edge detection circuit.
Under the driving of the frequency division clock signal clk_div1, when the pulse width counter samples and detects the rising edge signal of the input PWM signal Encoder1, the rising edge signal is used as a reset signal input to count, and each time the reset signal is input, the pulse width counter counts once according to the pulse number of the frequency division clock signal clk_div1, so as to obtain the pulse number of the frequency division clock signal clk_div1 corresponding to one pulse period of the input PWM signal Encoder1. As shown in fig. 2, each time the pulse width counter detects a rising edge signal of the input PWM signal Encoder1, the divided clock signal clk_div1 has spanned 4 clock cycles, and the pulse width counter increments 4 on the basis of the original count value as the current count value; between two rising edge signals of the input PWM signal Encoder1, the number of pulses of the divided clock signal clk_div1 is 4, and the pulse width counter uses the clock periods of the 4 divided clock signals clk_div1 to sample the input PWM signal Encoder1 for one pulse period. IN fig. 2, the pulses of the 4 divided clock signals clk_div1, which are defined by the dashed lines corresponding to the two rising edge signals of the input PWM signal Encoder1, are used as a standard for measuring the pulse width of the input PWM signal Encoder1, so as to measure the motor rotation speed corresponding to the PWM signal pwm_in to be processed. In the embodiment of the invention, the rising edge detection circuit is used for driving the pulse width counter to count the pulse width of the input PWM signal Encoder1, and the edge detection enabling signal is used for driving the pulse width counter to count the pulse width under a high-frequency clock signal, so that the clock is synchronous, and the pulse period sampling precision of the input PWM signal Encoder1 is improved.
Preferably, the bit width number power of the pulse width counter of 2 is greater than the ratio of the signal frequency of the clock input of the pulse width counter to the signal frequency of the input D of the D flip-flop. The highest input frequency of the first divided clock signal clk_div1 is 80MHz, and in the embodiment of the invention, the first divided clock signal clk_div1 is set to 20MHz. In order to realize that the first frequency-divided clock signal clk_div1 synchronously samples the rising edge signal of the first PWM signal Encoder1, the ratio of the first frequency-divided clock signal clk_div1 to the first PWM signal Encoder1 has a power-to-power relationship with the bit width of the pulse width counter, and when the clock frequency of the first PWM signal Encoder1 is 32Hz, the ratio of the clock frequency of the first frequency-divided clock signal clk_div1 to the clock frequency of the first PWM signal Encoder1 is 625000. Because the 20 th power of 2 is greater than 625000, the bit width of the pulse width counter is set to 20 bits, thereby satisfying that the bit width numerical power of the pulse width counter of 2 is greater than the ratio of the clock frequency of the first divided clock signal clk_div1 to the clock frequency of the first PWM signal Encoder1; since the highest clock frequency of the high-frequency clock signal clk_us is 80MHz and is 4 times of 20MHz, when the high-frequency clock signal clk_us is divided by one to obtain the first divided clock signal clk_div1 and the clock frequency of the first PWM signal Encoder1 is kept to be 32Hz, the bit width of the pulse width counter needs to be increased by 2 bits, the bit width value is set to 22 bits, which is reserved and configured by a related register built in the pulse width counter, and the corresponding bit width value is loaded on the premise of inputting the high-frequency clock signal clk_us. The D flip-flop of the rising edge detection circuit receives the first divided clock signal clk_div1 at a higher frequency, which can enhance the efficiency of rising edge detection, but the noise of the transitions cannot be filtered, but the noise of the first PWM signal Encoder1 has undergone the jitter elimination process, so that the noise has little influence.
The data output end of the pulse width counter is connected with the data input end of the median average module, and the signal of the pulse number output by the data output end of the pulse width counter is connected with the data input end of the median average module; the data output of the median averaging module is used as the output of the speed detector. The median average module comprises a counting sampling register which is used for storing the pulse number output by the pulse width counter in real time; the median average module is connected with the pulse width counter, controls the pulse number to be compared with the second preset number of pulses stored in the counting sampling register, sorts the pulses according to a comparison result, and then selects a middle value to represent the pulse speed signal speed; the second preset number of pulses is the number of pulses of the frequency division clock signal clk_div1 corresponding to the second preset number of pulse periods which have been sampled and detected in the input PWM signal Encoder1. The median average module in this embodiment is beneficial to eliminating the influence of signal noise on the number of pulses, and avoids the phenomenon that the measured pulse width of the input PWM signal Encoder1 is too large or too small, so as to collect stable speed signals for an external motor system.
As shown in fig. 3, an embodiment of the present invention provides a processing circuit of a PWM signal, where the processing circuit includes a PWM sampling detection module and a PWM generation module; the clock input end of the PWM sampling detection module is connected with the clock input end of the PWM generation module; the PWM input end of the PWM sampling detection module is used for capturing an input PWM signal PWM_IN to be processed, the clock input end of the PWM sampling detection module is used for receiving a high-frequency clock signal CLK_US output by an external system clock generator, under the embodiment of the invention, the frequency range of the PWM signal PWM_IN to be processed is more than 32Hz and less than 2KHz, the high-frequency clock signal CLK_US output by the external system clock generator is a clock signal with the period of 0.2US, and the signal jitter elimination effect is exerted through counting with corresponding precision; the PWM sampling detection module is used for outputting a pulse speed signal speed and a corresponding pulse step length signal based on a PWM signal to be processed to an external motor system as feedback quantity. Compared with the prior art, the application function of the PWM signal output circuit is expanded. The PWM generation module is used for receiving a sampling clock Clk output by the external system clock generator and outputting a PWM output signal PWM_OUT with controllable duty ratio based on the sampling clock Clk; the PWM sampling detection module and the PWM generation module are connected to the sampling clock Clk together; the sampling clock Clk may also be derived from a bus clock on an external AHB bus, where the corresponding clock frequency includes 80MHz, 40MHz, or 20MHz, so that the PWM output signal pwm_out meets application requirements of various motor control systems. When the PWM sampling detection module provides the pulse speed signal speed and the corresponding pulse step signal for the external motor system, the external motor system adjusts, specifically adjusts the frequency of the output sampling clock Clk, the PWM signal pwm_in to be processed and the high-frequency clock clk_us, and then controls the PWM generation module to output the PWM output signal pwm_out with the corresponding duty ratio, so as to complete the rotation speed adjustment control of the external motor system.
The PWM sampling detection module comprises a filter, a step length counting submodule, a signal prescaler, a speed detector and a first time Zhong Yu frequency divider, and the connection relation inside the module is as follows: the signal output end of the filter is connected with the data input end of the step length counting submodule and the clock input end of the signal prescaler at the same time, and the clock output end of the signal prescaler is connected with the data input end of the speed detector; the clock input end of the speed detector is connected with the clock output end of the first time Zhong Yu frequency divider; the signal input end of the filter is used as the signal input end of the PWM sampling detection module, and the speed signal output end of the speed detector is used as the output end of the PWM sampling detection module. The signal input end of the filter is used for capturing the input PWM signal PWM_IN to be processed, the clock input end of the filter receives the high-frequency clock signal CLK_US output by the external system clock generator, the PWM signal PWM_IN to be processed is controlled to be filtered under the driving action of the high-frequency clock signal CLK_US, and then the reference PWM signal Encoder is output from the signal output end of the filter. Since the high frequency clock signal clk_us is configurable, the filter can implement filtering operations of the level-jittered signals of different pulse widths IN the PWM signal pwm_in to be processed. The signal output end of the filter is connected with the data input end of the step length counting sub-module and the clock input end of the signal prescaler at the same time and is used for transmitting the reference PWM signal Encoder to the step length counting sub-module and the signal prescaler; the signal prescaler is used for dividing the received reference PWM signal Encoder to output a first PWM signal Encoder1, wherein the signal prescaler supports and can be configured as a divide-by-2, divide-by-4 or divide-by-8 divider; the clock output end of the signal prescaler is connected with the data input end of the speed detector and is used for transmitting the first PWM signal Encoder1 to the speed detector so as to output the first PWM signal Encoder1 with different frequencies to the speed detector. The first time Zhong Yu frequency divider is configured to control the received sampling clock Clk to divide to obtain a first divided clock clk_div1, and output the first divided clock clk_div1 to the speed detector, where in this embodiment, the frequency division coefficient of the first time Zhong Yu frequency divider is configured to be 16. The clock input end of the speed detector is connected with the clock output end of the first time Zhong Yu frequency divider, the speed detector counts the pulse number of the corresponding first frequency division clock signal clk_div1 IN each pulse period of the first PWM signal Encoder1 by detecting the rising edge of the first PWM signal Encoder1 under the driving action of the first frequency division clock signal clk_div1, the speed detector uses the first frequency division clock signal clk_div1 to sample and detect the first PWM signal Encoder1, median average processing is carried out on the pulse number to finish noise reduction processing of the pulse number, then the output obtains a pulse speed signal speed, reduces the influence of a pulse speed measured value of a PWM signal PWM_IN to be processed by the noise signal, and provides a higher-precision pulse speed signal for an external motor system so as to facilitate the feedback signal of the rotating speed of the motor system. Since the speed signal output end of the speed detector is used as the output end of the PWM sampling detection module, the pulse speed signal speed is output at the speed signal output end of the speed detector.
The filter comprises a first preset number of D triggers and a comparison output module, the first preset number of D triggers form a shift register with a first preset number of bits, clock ends of the first preset number of D triggers are connected to clock input ends of the filter, output ends (Q) of the first preset number of D triggers are respectively connected to first preset number of data input ends of the comparison output module, data input ends of the shift register serve as signal input ends of the filter, and data output ends of the comparison output module serve as signal output ends of the filter. In this embodiment, the first preset number is set to 6, as shown in fig. 4, where the filter includes a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth D flip-flop D5, a sixth D flip-flop D6, and a comparison output module, the 6D flip-flops form a 6-bit shift register, clock terminals of the 6D flip-flops are all connected to the high-frequency clock signal clk_us, an output terminal Q0 of the first D flip-flop D1, an output terminal Q1 of the second D flip-flop D2, an output terminal Q2 of the third D flip-flop D3, an output terminal Q3 of the fourth D flip-flop D4, an output terminal Q4 of the fifth D flip-flop D5, and an output terminal Q5 of the sixth D flip-flop D6 are respectively connected to 6 data input terminals of the comparison output module, and the data output terminal of the comparison output module is used to output the encoded PWM signal, thereby ensuring the stability of the PWM detection module.
As an embodiment, in the shift register, the output terminal of each D flip-flop except for the rightmost D flip-flop is connected to the input terminal of one D flip-flop on the right, the output terminal of the rightmost D flip-flop is connected to one data input terminal of the comparison output module, and the input terminal of the leftmost D flip-flop is used as the data input terminal of the shift register. As shown IN fig. 4, when the data IN the shift register is sequentially shifted to the right bit by bit under the driving action of the high-frequency clock signal clk_us, the output terminal of each D flip-flop except the sixth D flip-flop D6 is connected to the input terminal D of one D flip-flop on the right, and the input terminal D of the first D flip-flop D1 is connected to the PWM signal pwm_in to be processed.
As another embodiment, IN the shift register, the output end of each D flip-flop except for the leftmost D flip-flop is connected to the input end of one D flip-flop on the left, the output end of the leftmost D flip-flop is connected to one data input end of the comparison output module, and when the data IN the shift register is sequentially shifted left bit by bit under the driving action of the high-frequency clock signal clk_us, the output end Q of each D flip-flop except for the leftmost D flip-flop is connected to the input end D of one D flip-flop on the left, and the input end D of the rightmost D flip-flop is connected to the PWM signal pwm_in to be processed.
The shift register can not only register data, but also enable the data therein to be shifted left or right in sequence under the action of the high-frequency clock signal clk_us. Since a delay time is stably established from the rising edge of the high frequency clock signal clk_us applied to the flip-flops to the new state of the output terminal, when the high frequency clock signal clk_us is simultaneously applied to the first preset number of D flip-flops, each D flip-flop receives the original data in one D flip-flop on the left (or right), and then the data in the shift register is sequentially shifted right (or left) by one bit.
The internal logic relationship of the comparison output module is as follows: when the 6 data input ends of the comparison output module are all 0, namely 6 bit signals Q [5] corresponding to the output ends of the 6 flip-flops: when 0] =0, the reference PWM signal Encoder output by the comparison output module is at a low level; when the 6 data input ends of the comparison output module are all 1, namely 6 bit signals Q [5] corresponding to the output ends of the 6 flip-flops: when 0] =6' b111111, the reference PWM signal Encoder output by the comparison output module is at a high level; when there are both 0 and 1 in the first preset number of data inputs of the comparison output module, i.e. Q [5: 0-! =0 and Q [5: 0-! When=6' b111111, the reference PWM signal Encoder output by the comparison output module keeps the original level state unchanged.
Preferably, the first preset number is set to 6, so that the filter filters out level jitter of less than 5 clock cycles of the PWM signal pwm_in to be processed as glitches, wherein the clock cycles are pulse cycles of the jitter level of the PWM signal pwm_in to be processed. If the PWM signal pwm_in to be processed has a pulse smaller than a certain width to be filtered, for example, if a jitter level pulse of 1uS is to be filtered, the filter may be formed by 6D flip-flops with a delay time of 0.2uS and one comparison output module, and 6D flip-flops with a delay time of 0.2uS form a 6-bit shift register. Before the PWM signal PWM_IN to be processed is subjected to jitter elimination, the input ends of a first preset number of the comparison output modules are all 1 or all 0, and the reference PWM signal Encoder output by the comparison output modules is correspondingly high level or low level; during the period of eliminating the jitter of the PWM signal PWM_IN to be processed, the first preset number of input ends of the comparison output module are 1 and 0, the original level state of the reference PWM signal Encoder output by the comparison output module is kept unchanged, and the period can be judged to be a stable level signal. After the PWM signal PWM_IN to be processed is debounced, the first preset number of input ends of the comparison output module are all 1 or all 0, and the reference PWM signal Encoder output by the comparison output module is correspondingly high level or low level. Therefore, the input signal can be subjected to noise suppression, the level jitter of less than 5 system clock cycles is filtered, the higher harmonic energy of the input PWM signal is effectively reduced, the electromagnetic interference of an external motor system is reduced, and the method has strong practicability.
The step length counting submodule internally comprises a step length counter and a direction register, and the output end of the direction register is connected with the enabling end of the step length counter. The counting output end of the step counter is used as the output end of the step counting sub-module, and the counting input end of the step counter is used as the data input end of the step counting sub-module. The direction register is used for outputting an addition and subtraction control signal which is used as a direction control signal of an 'addition' or 'subtraction' switch, and the addition and subtraction control signal output by the direction register is connected with the step counter. If the addition and subtraction control signal is set to 1, the step counter is used for adding 1 count IN each pulse period, and when the step counting submodule detects a rising edge signal of the reference PWM signal Encoder, the step counter starts adding 1 count from 0 and keeps the current count value IN a built-IN register of the step counter, so that a step value based on the PWM_IN to be processed is provided for an external motor control system, and represents a path value obtained by motor rotation; when the count value of the step counter reaches the maximum value, the step counter overflows to generate a Tick pulse signal with one clock cycle, and the step counter restarts to count by 1 from 0. If the addition and subtraction control signal is set to 0, the step counter is used for performing 1-step count down IN each pulse period, and when the step counting submodule detects a rising edge signal of the reference PWM signal Encoder, the step counter starts to perform 1-step count down from a preset count value and keeps the current count value IN a built-IN register of the step counter, so that a step value based on the PWM signal PWM_IN to be processed is provided for an external motor control system, and represents a path value of motor rotation; when the count value of the step counter is reduced to 0, the step counter overflows (i.e. the current count value is 0) to generate a Tick pulse signal with one clock period, and the step counter loads the preset count value and then starts to count down again.
Preferably, the step counter in the step counting sub-module is set to be a 32-bit counter, and no sign processing is required for the count value.
As shown in fig. 3, the PWM generation module includes a second clock prescaler and a PWM signal generator, and the connection relationship inside the module is: the clock output end of the second clock prescaler is connected with the data input end of the PWM signal generator. Specifically, the second clock prescaler is connected with a first clock Zhong Yu frequency divider in the PWM sampling detection module, and is configured to receive a sampling clock Clk; the second clock prescaler is configured to divide the received sampling clock Clk to output a second divided clock signal clk_div2, and in this embodiment, the clock frequency of the second divided clock signal clk_div2 may be 72MHz, 40MHz, 20MHz or 10MHz. The second clock prescaler is connected with the PWM signal generator and is used for transmitting a second frequency division clock signal Clk_div2 to the PWM signal generator; the PWM signal generator is configured to receive the reference level signal level, and generate a PWM output signal pwm_out according to a comparison result between the frequency division value of the second frequency division clock signal clk_div2 and the reference level signal level, specifically, the PWM signal generator divides the frequency of the second frequency division clock signal clk_div2 by a counter, and then compares the level of the second frequency division clock signal clk_div2 with the reference level signal level, when the frequency division value of the second frequency division clock signal clk_div2 is greater than the level value of the reference level signal level, the PWM output signal pwm_out is at a high level, otherwise, the PWM output signal pwm_out is at a low level.
As shown in fig. 5, the PWM signal generator includes an output frequency divider and a comparator, wherein a clock output terminal of the output frequency divider is connected to a comparison input terminal of the comparator, an input terminal of the output frequency divider is used as a data input terminal of the PWM signal generator, and an output terminal of the comparator is used as a data output terminal of the PWM signal generator. The output frequency divider is configured to receive the second divided clock signal clk_div2, and perform frequency division processing on the second divided clock signal clk_div2. In the embodiment of the present invention, the output frequency divider includes a counter, the counter is designed as a counter with a width of 10 bits, and the frequency division coefficient is 1024, so the output frequency divider carries out 1024 frequency division processing on the second frequency division clock signal clk_div2, when the clock frequency of the second frequency division clock signal clk_div2 is 72MHz, the frequency division value output by the output frequency divider is 72 MHz/1024=70 KHz, and the frequency division value can be used as the highest output frequency to be compared, so that the signal output by the PWM signal generator is a PWM output signal with a low frequency in KHz.
As shown in fig. 5, the comparison input end of the comparator is respectively connected to the frequency division value of the output frequency divider and the reference level signal level, and is configured to output a PWM output signal pwm_out with a corresponding level according to the comparison result of the frequency division value of the second frequency division clock signal clk_div2 and the level of the reference level signal level, where the PWM output signal pwm_out is a high level when the frequency division value is greater than the level value of the reference level signal level; when the frequency division value is smaller than the level value of the reference level signal level, the PWM output signal PWM_OUT is low level. Because the frequency division coefficient of the output frequency divider and the input second frequency division clock signal Clk_div2 are adjustable, the duty ratio of the PWM output signal PWM_OUT is controllable, and meanwhile, the PWM generating module also generates an interrupt output signal to assist the PWM sampling detection module to control the rotating speed of an external motor system.
A chip, wherein the processing circuit is integrated inside the chip and comprises the PWM sampling detection module and the PWM generation module; the PWM sampling detection module captures a PWM signal PWM_IN to be processed, which is input from the outside of the chip, receives a high-frequency clock signal CLK_US, which is output by a system clock generator inside the chip, and outputs a pulse speed signal speed based on the PWM signal to be processed to the outside of the chip. The PWM generation module is used for receiving a sampling clock Clk output by a system clock generator in the chip and outputting a PWM output signal PWM_OUT with controllable duty ratio based on the sampling clock Clk, and the PWM sampling detection module and the PWM generation module are connected to the sampling clock Clk together. Compared with the prior art, the speed detector is integrated inside the chip, and the chip is used for providing pulse sampling speed for an external motor system.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
Claims (11)
1. A speed detector based on PWM signals, the speed detector being adapted to provide a pulse sampling speed for an external motor system, characterized in that the speed detector comprises a rising edge detection circuit, a pulse width counter and a median average module; the clock input end of the rising edge detection circuit is connected with the clock input end of the pulse width counter, the output end of the rising edge detection circuit is connected with the reset end (reset) of the pulse width counter, the data output end of the pulse width counter is connected with the data input end of the median average module, the data output end of the median average module is used as the output end of the speed detector, and the input end of the rising edge detection circuit is used as the data input end of the speed detector.
2. A speed detector according to claim 1, characterized in that the rising edge detection circuit comprises a D flip-flop and an and gate, the input (D) of the D flip-flop being connected to one input of the and gate, the inverting output (Q) of the D flip-flop being connected to the other input of the and gate; the clock end of the pulse width counter is connected with the clock end of the D trigger, the output end of the AND gate is used as the output end of the rising edge detection circuit, and the input end of the D trigger is used as the input end of the rising edge detection circuit.
3. The speed detector of claim 2, wherein the bit width number of the pulse width counter of 2 is greater than the ratio of the signal frequency at the clock input of the pulse width counter to the signal frequency at the input of the D flip-flop.
4. A processing circuit of a PWM signal, which is applied to an external motor system, and is characterized in that the processing circuit comprises a PWM sampling detection module and a PWM generation module; the clock input end of the PWM sampling detection module is connected with the clock input end of the PWM generation module;
the PWM sampling detection module comprises a step counting sub-module, a signal prescaler, a filter, a first time Zhong Yu frequency divider, and the speed detector of any one of claims 1 to 3, wherein a signal input end of the filter is used as a signal input end of the PWM sampling detection module, and a speed signal output end of the speed detector is used as an output end of the PWM sampling detection module;
the connection relation inside the PWM sampling detection module is as follows: the signal output end of the filter is connected with the data input end of the step length counting submodule and the clock input end of the signal prescaler at the same time, and the clock output end of the signal prescaler is connected with the data input end of the speed detector; the clock input end of the speed detector is connected with the clock output end of the first time Zhong Yu frequency divider;
the PWM generation module comprises a second clock prescaler and a PWM signal generator, and the connection relation inside the module is as follows: the clock output end of the second clock prescaler is connected with the data input end of the PWM signal generator, the clock input end of the second clock prescaler is used as the clock input end of the PWM generating module, and the data output end of the PWM signal generator is used as the output end of the PWM generating module.
5. The processing circuit according to claim 4, wherein the filter comprises a first preset number of D flip-flops and a comparison output module, the first preset number of D flip-flops forming a shift register of the first preset number of bits, the clock terminals of the first preset number of D flip-flops being connected to the clock input terminals of the filter, the output terminals (Q) of the first preset number of D flip-flops being connected to the first preset number of data input terminals of the comparison output module, respectively, the data input terminals of the shift register being the signal input terminals of the filter, the data output terminals of the comparison output module being the signal output terminals of the filter.
6. The processing circuit according to claim 5, wherein in the shift register a first predetermined number of D flip-flops is arranged in sequence from left to right, the output (Q) of each D flip-flop except for the rightmost D flip-flop being connected to the input (D) of its right adjacent one of the D flip-flops, the output (Q) of the rightmost D flip-flop being connected to one of the data inputs of the comparison output module.
7. The processing circuit according to claim 5, characterized in that in the shift register a first predetermined number of D flip-flops is arranged from left to right, the output (Q) of each D flip-flop except for the leftmost D flip-flop being connected to the input (D) of its left-most one of the D flip-flops, the output (Q) of the leftmost D flip-flop being connected to a data input of the comparison output module.
8. The processing circuit according to claim 5, characterized IN that the first preset number is set to 6 such that the filter filters out level jitter of less than 5 clock cycles of the input PWM signal to be processed (pwm_in) as glitches, wherein the clock cycles are pulse cycles of the jitter level of the PWM signal to be processed (pwm_in).
9. The processing circuit of claim 4, wherein the step size counting sub-module includes a step size counter and a direction register therein, an output of the direction register being coupled to an enable of the step size counter, a count output of the step size counter being an output of the step size counting sub-module, and a count input of the step size counter being a data input of the step size counting sub-module.
10. The processing circuit of claim 4 wherein the PWM signal generator comprises an output divider and a comparator, the clock output of the output divider being coupled to a comparison input of the comparator, the input of the output divider being the data input of the PWM signal generator and the output of the comparator being the data output of the PWM signal generator.
11. A chip, characterized in that the chip comprises the processing circuit according to any of claims 4 to 10 inside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811501749.9A CN109580975B (en) | 2018-12-10 | 2018-12-10 | Speed detector, processing circuit and chip based on PWM signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811501749.9A CN109580975B (en) | 2018-12-10 | 2018-12-10 | Speed detector, processing circuit and chip based on PWM signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109580975A CN109580975A (en) | 2019-04-05 |
| CN109580975B true CN109580975B (en) | 2023-09-05 |
Family
ID=65929156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811501749.9A Active CN109580975B (en) | 2018-12-10 | 2018-12-10 | Speed detector, processing circuit and chip based on PWM signal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109580975B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112202424A (en) * | 2020-11-06 | 2021-01-08 | 珠海市一微半导体有限公司 | N-time pulse width expansion circuit and pulse width expanded phase-locked loop system |
| CN114441796B (en) * | 2022-02-10 | 2023-09-19 | 厦门乃尔电子有限公司 | Magneto-electric type rotation speed sensor with self-checking function and PFM modulation output |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0727804A (en) * | 1993-07-12 | 1995-01-31 | Fujitsu Ltd | Pulse width measurement circuit |
| CN101599276A (en) * | 2009-06-30 | 2009-12-09 | 中国科学院上海光学精密机械研究所 | CD jitter characteristics proving installation and method of testing thereof |
| CN102427350A (en) * | 2011-11-29 | 2012-04-25 | 上海新进半导体制造有限公司 | PWM (Pulse-Width Modulation) signal phase-shift circuit and control method |
| CN202794346U (en) * | 2012-06-27 | 2013-03-13 | 比亚迪股份有限公司 | Pulse width detection circuit |
| CN103762964A (en) * | 2014-01-17 | 2014-04-30 | 北京航空航天大学 | Multi-channel high-precision PWM signal sampling and generation device |
| CN104485947A (en) * | 2014-12-30 | 2015-04-01 | 中南民族大学 | Digital phase discriminator used for GPS tame crystal oscillator |
| CN105553444A (en) * | 2015-12-15 | 2016-05-04 | 大豪信息技术（威海）有限公司 | Adaptive filter |
| CN209231361U (en) * | 2018-12-10 | 2019-08-09 | 珠海市一微半导体有限公司 | Speed detector, processing circuit and chip based on pwm signal |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102004011723A1 (en) * | 2004-03-10 | 2005-09-29 | Patent-Treuhand-Gesellschaft für elektrische Glühlampen mbH | Digital-to-analogue converter with nested pulse width modulated signal |
-
2018
- 2018-12-10 CN CN201811501749.9A patent/CN109580975B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0727804A (en) * | 1993-07-12 | 1995-01-31 | Fujitsu Ltd | Pulse width measurement circuit |
| CN101599276A (en) * | 2009-06-30 | 2009-12-09 | 中国科学院上海光学精密机械研究所 | CD jitter characteristics proving installation and method of testing thereof |
| CN102427350A (en) * | 2011-11-29 | 2012-04-25 | 上海新进半导体制造有限公司 | PWM (Pulse-Width Modulation) signal phase-shift circuit and control method |
| CN202794346U (en) * | 2012-06-27 | 2013-03-13 | 比亚迪股份有限公司 | Pulse width detection circuit |
| CN103762964A (en) * | 2014-01-17 | 2014-04-30 | 北京航空航天大学 | Multi-channel high-precision PWM signal sampling and generation device |
| CN104485947A (en) * | 2014-12-30 | 2015-04-01 | 中南民族大学 | Digital phase discriminator used for GPS tame crystal oscillator |
| CN105553444A (en) * | 2015-12-15 | 2016-05-04 | 大豪信息技术（威海）有限公司 | Adaptive filter |
| CN209231361U (en) * | 2018-12-10 | 2019-08-09 | 珠海市一微半导体有限公司 | Speed detector, processing circuit and chip based on pwm signal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109580975A (en) | 2019-04-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11791813B2 (en) | PWM generation circuit, processing circuit and chip | |
| CN108445734B (en) | Clock pulse frequency multiplication, frequency multiplication and digital pulse generation circuit and time-to-digital converter | |
| CN109580975B (en) | Speed detector, processing circuit and chip based on PWM signal | |
| CN209231361U (en) | Speed detector, processing circuit and chip based on pwm signal | |
| CN107562163B (en) | Digital logic circuit with stable reset control | |
| CN106612084B (en) | Current sample processing circuit and sampling processing method | |
| CN109361381B (en) | PWM generating circuit, processing circuit and chip | |
| CN109412582B (en) | PWM signal sampling detection circuit, processing circuit and chip | |
| CN109391247B (en) | Filter, processing circuit and chip based on PWM signal | |
| CN209170340U (en) | Pwm signal sample detecting circuit, processing circuit and chip | |
| CN111769822B (en) | Frequency measuring device | |
| TWI491169B (en) | Modularized control circuit with signal-capturing function for fan motor and method for controlling the same | |
| CN109635355B (en) | GPIO-oriented frequency-adjustable filter circuit | |
| CN209170328U (en) | PWM generative circuit, processing circuit and chip | |
| US7327300B1 (en) | System and method for generating a pulse width modulated signal having variable duty cycle resolution | |
| CN108039883B (en) | Method and device for detecting stability of output clock signal of phase-locked loop | |
| KR20180043380A (en) | High-Speed Programmable Clock Divider | |
| CN209233806U (en) | Filter, processing circuit and chip based on pwm signal | |
| CN109412582A (en) | A kind of pwm signal sample detecting circuit, processing circuit and chip | |
| CN204631519U (en) | A kind of microcontroller for Electric Machine Control | |
| CN113193868A (en) | Phase-locked detection device, phase-locked detection method and phase-locked loop | |
| Aydogmus et al. | Implementation of an FPGA-based motor control with low resource utilization | |
| CN109391247A (en) | A kind of filter based on pwm signal, processing circuit and chip | |
| CN112688672A (en) | Apparatus and method for generating PWM wave | |
| US11942938B2 (en) | Rational ratio multiplier (RRM) with optimized duty cycle implementation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 519000 2706, No. 3000, Huandao East Road, Hengqin new area, Zhuhai, Guangdong Applicant after: Zhuhai Yiwei Semiconductor Co.,Ltd. Address before: 519000 room 105-514, No. 6, Baohua Road, Hengqin new area, Zhuhai, Guangdong Applicant before: AMICRO SEMICONDUCTOR Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |