JP2002296309A - Frequency anomaly detecting circuit and anomaly detecting value setting circuit used therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect frequency anomalies of a clock to be monitored and to set anomaly detecting values, as desired. SOLUTION: The number of clock pulses of a monitoring clock 2, in the half-period of the block to be monitored 1 by the monitoring clock 2 with a frequency higher than that of the clock to be monitored 1, is counted by a counter 6. When a counted value exceeds a set value of a comparator 7 or when it does not reach a set value of a comparator 8, frequency anomaly of the clock to be monitored 1 is detected. In addition, the values of the counter 6, when the clock to be monitored 1 is under normal conditions, are captured in latching circuits 13 and 14. When the latched values are matched by a number set by a comparator 15, a predetermined value is added to or subtracted from the values to be the set values of the compactors 7 and 8. Accordingly, it is possible to set the anomaly detecting values of the frequency anomaly detecting circuit, as desired.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency abnormality detection circuit and an abnormality detection value setting circuit used therewith, and more particularly, to a frequency abnormality detection circuit for detecting a frequency abnormality of an externally monitored clock using a monitoring clock and a frequency abnormality detection circuit used therefor. It relates to an abnormality detection value setting circuit.

[0002]

2. Description of the Related Art Conventionally, a circuit for detecting an abnormal frequency of a monitored clock input from the outside has been disclosed in JP-A-7-23.
There is a frequency abnormality detection circuit disclosed in Japanese Patent No. 5831. FIG. 6 shows a block diagram of this frequency abnormality detection circuit. FIG. 6 shows a frequency abnormality detection circuit having two oscillators having different frequencies. The overflow abnormality of the oscillators 1a and 1b having different frequencies, the counter 2a, the decoder 3a, the edge detection circuit 5b, and the counter 2a is shown. It comprises an abnormality determination circuit 41a for detecting, and an abnormality determination circuit 42a for determining an abnormality when the decoder 3a and the edge detection circuit 5b do not match.

In this frequency abnormality detection circuit, the counter 2a normally counts the oscillator 1a, and the counter 2a is reset at the rising edge of the oscillator 1b detected by the edge detection circuit 5b. Although the decoder 3a decodes with an arbitrary count value, it is preset so as to output the value of the counter 2a when it matches the output of the edge detection circuit 5b for detecting the falling edge of the oscillator 1b. . When the output of the decoder 3a and the output of the edge detection circuit 5b that has detected the falling edge of the oscillator 1b detected by the edge detection circuit 5b match, the abnormality determination circuit 42a has determined that the abnormality is normal. .

In such a circuit, for example, an oscillator 1a
Stops, the counter 2a does not count up, and the decoder 3a does not decode at the same time. Therefore, the output of the decoder 3a and the output of the edge detection circuit 5b detected by the falling edge of the oscillator 1b detected by the edge detection circuit 5b are detected. Do not coincide with each other, so that the abnormality determination circuit 42a determines that there is an abnormality. Also, when the oscillator 1a oscillates at a high frequency, the counter 2a counts up earlier than in a normal state, so that the counter 2a overflows before being reset at the rising edge of the oscillator 1b detected by the edge detection circuit 5b. And the abnormality is determined to be abnormal by the abnormality determination circuit 41a. When the output of the oscillator 1b is stopped or when the oscillator oscillates at a high frequency, the abnormality is similarly detected.

Another circuit for detecting an abnormal frequency of a clock input from the outside is disclosed in JP-A-11-127.
No. 064 discloses a frequency abnormality detection circuit. FIG. 7 shows a block diagram of this frequency abnormality detection circuit. FIG. 7 shows a circuit for detecting an abnormality of an externally input clock frequency using one oscillator. The internal oscillator 100, an abnormality monitoring counter 101, a window generator 102, a frequency division counter 103, Vessel 104
And a decoding circuit 105 for generating a detected pulse, a decoding circuit 106 for generating a window, and a decoding circuit 107 for monitoring cycle timing.

In this frequency anomaly detection circuit, a window pulse is generated by a window generator 102 based on a clock generated by an internal oscillator 100, a monitoring window defined by the window pulse is determined, and a detection target input from the outside is detected. A detected pulse is generated from the clock by the detected pulse generating decode circuit 105, and the comparator 1 determines whether or not the detected pulse is within the monitoring window.
By making a determination in step 04, a frequency abnormality of the detected clock input from the outside is determined.

[0007]

However, in the frequency abnormality detection circuit shown in FIG. 6, when the decoder 3a outputs the value of the counter 2a, the output of the decoder 3a is used as an edge detection circuit for detecting the falling edge of the oscillator 1b. 5b must be set in advance to match the output of the decoder 1b.
output position of the counter a and the counter 2 by the abnormality determination circuit 41a.
The overflow detection value of 0a must be changed.

The output of the decoder 3a is the count value of the oscillator 1a when the falling edge of the oscillator 1b is detected, that is, the value of the counter 2a.
The frequency b and the decode value are associated at a certain timing. Therefore, in order to change the decode value, it is necessary to set the frequencies of the oscillators 1a and 1b again. Therefore, it is not possible to arbitrarily set a detection value for detecting a frequency abnormality, so that there is a problem that the frequency abnormality detection circuit cannot be integrated and has no versatility.

In the frequency abnormality detection circuit shown in FIG. 7, the frequency abnormality of the detected clock input from the outside is determined based on whether or not the detected pulse is within the monitoring window. Accuracy will be affected by the stability of the monitoring window. Therefore, there is a problem that the internal oscillator 100, which is the source of the monitoring window, is required to have a high degree of stability, which increases the cost.

The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a degree of freedom in the frequency relationship between a monitored clock and a monitored clock so that monitoring can be performed. An object of the present invention is to provide a frequency abnormality detection circuit which does not particularly require the frequency accuracy of a clock and which can arbitrarily set a frequency abnormality detection value, and an abnormality detection value setting circuit used therefor.

[0011]

According to the present invention, there is provided a frequency abnormality detecting circuit for detecting a frequency abnormality of an externally monitored clock, wherein the frequency abnormality detecting circuit uses a monitoring clock having a frequency higher than the monitored clock. Counting means for counting the number of clock pulses of the monitoring clock in a predetermined cycle of the monitored clock; first comparing means for comparing a count value of the counting means with a first set value set in advance; A second comparison unit configured to compare a second set value smaller than the first set value with a count value of the counting unit; A frequency abnormality detection circuit including detection means for detecting a frequency abnormality of the monitored clock is obtained.

Further, the first comparing means outputs a first abnormal signal when the count value exceeds the first set value, and the second comparing means outputs the first abnormal signal when the count value exceeds the second set value. A second abnormal signal is output when the value falls below a set value of the second period, and further comprising means for masking the comparison output of the second comparing means for at least a period corresponding to the predetermined period. .

According to the present invention, the number of clock pulses of the monitoring clock in a predetermined cycle of the monitored clock is counted by using the monitoring clock from the outside as a monitoring clock having a frequency higher than that of the monitoring clock. Counting means, and a count value of the counting means and a preset first value
First comparing means for comparing with a set value of the second set value, and second comparing means for comparing a second set value smaller than the first set value with a count value of the counting means, An abnormality detection value setting circuit used in a frequency abnormality detection circuit for detecting an abnormality in the frequency of the monitored clock in accordance with an output of the first and second comparing means, wherein the count value is calculated in a cycle of the monitored clock. First latch means for sequentially capturing and holding as a first count value, and second latch means for sequentially capturing the first count value at a cycle of the monitored clock and holding as a second count value; When the first count value and the second count value match a predetermined number of times, a predetermined value is added to the count value to make the first set value, and a predetermined value is calculated from the count value. And a subtraction means for subtracting the second set value. Abnormality detection value setting circuit used in the frequency anomaly detection circuit, wherein is obtained.

The operation of the present invention will be described. Using the monitoring clock having a higher frequency than the monitored clock, the number of clock pulses of the monitoring clock in a predetermined period of the monitored clock is counted. If the count value exceeds a preset upper limit value or falls below a preset lower limit value, it is determined that the frequency of the monitored clock is abnormal. Further, the counter value when the frequency of the monitored clock is normal is taken into the latch circuit at the period of the monitored clock, and the taken counter value is taken into another latch circuit at the next period of the monitored clock. If the counter values held in these two latch circuits match a predetermined number of times, a predetermined value is added to the counter value to set it as an upper limit value for frequency abnormality detection, and the predetermined value is subtracted from the counter value. Set as the lower limit of frequency abnormality detection.
This makes it possible to arbitrarily set the abnormality detection value of the frequency abnormality detection circuit.

[0015]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration of a frequency abnormality detection circuit according to one embodiment of the present invention. In FIG. 1, the frequency abnormality detection circuit according to the present invention is roughly divided into a frequency abnormality detection section 20a and an abnormality detection value setting section 20b.

First, the frequency abnormality detecting section 20a includes a monitored clock 1, a monitored clock 2 having a higher frequency than the monitored clock 1, and a D flip-flop (hereinafter, referred to as a D flip-flop) for synchronizing the monitored clock 2 and the monitored clock 1. After synchronizing the monitored clock 1 and the monitored clock 2, the AND circuit 4 samples the synchronous output with the monitored clock 2, and synchronizes the monitored clock 1 with the monitored clock 2. After that, the rising edge of the synchronous output is detected, the edge detection circuit 5 loads the counter 6, the counter 6 counts the sampling result, and the count value of the counter 6 is compared with a predetermined value. And a comparator for maintaining the output state for a predetermined time triggered by the output of the comparator 8 Bull monostable multivibrator (hereinafter referred to as "mono-multi") and 9, the comparator 7
ANDing the logical product of the result of comparison with the output of the mono-multi 9
A frequency abnormality output terminal 11 outputs whether or not the frequency of the monitored clock 1 is abnormal.

Next, the abnormality detection value setting section 20b includes a latch circuit 13 for holding the count value of the counter 6 when the frequency of the monitored clock 1 is normal, and a latch for holding the count value held by the latch circuit 13. A circuit 14, an OR circuit 12 that causes the latch circuits 13 and 14 to hold a count value at the timing of the edge detection circuit 5, a comparator 15 that compares the count values held by the latch circuit 13 and the latch circuit 14, As a result of the comparison by the comparator 15, the count value of the latch circuit 13 and the latch circuit 1
4 and the protection counter 16 for inhibiting the holding of the count value from the latch circuit 13 to the latch circuit 14 when the count value matches the predetermined number of times, and the count value held by the latch circuits 13 and 14 is determined in advance. An addition circuit 17 for adding the obtained values and a subtraction circuit 18 for subtracting a predetermined value from the count values held by the latch circuits 13 and 14 are provided.

Next, the operation of the frequency abnormality detecting section 20a of the frequency abnormality detecting circuit according to one embodiment of the present invention will be described in detail with reference to FIG. In the frequency abnormality detection unit 20a, the DFF3 is used to cope with the case where the monitored clock 1 and the monitoring clock 2 are asynchronous.
Thus, the monitored clock 1 and the monitoring clock 2 are synchronized. The Q output of the DFF 3, that is, the monitored clock 1 synchronized with the monitoring clock 2 is sampled by the monitoring clock 2 in the AND circuit 4. That is, the clock pulse of the monitoring clock 2 in the half cycle of the monitored clock 1 is obtained.

Here, if the frequency of the monitored clock 2 is sufficiently higher than the frequency of the monitored clock 1, even if the monitored clock 1 and the monitoring clock 2 are not synchronized, A
The sampling result of the ND circuit 4, that is, the error in the number of clock pulses of the monitoring clock 2 in the half cycle of the monitored clock 1 hardly affects the detection accuracy of the frequency abnormality. There is no particular problem even if the monitoring clock 2 is asynchronous.

The result of sampling by the AND circuit 4 is as follows:
It is input to the CK terminal of the counter 6. That is, the counter 6 counts the number of clock pulses of the monitoring clock 2 existing in a half cycle of the monitored clock 1, and outputs the count value to the comparators 7 and 8. on the other hand,
The Q output of the DFF 3 is edge-detected by the edge detection circuit 5 and is input to the LD terminal of the counter 6.

Edge detection in the edge detection circuit 5 is D
Although the rising or falling of the Q output of the FF3 may be used, the case where the rising edge is detected will be described here. When the edge detection circuit 5 detects the Q output of the DFF 3, that is, the rising edge of the monitored clock 1,
An “L” pulse is output to the LD terminal of the counter 6 to load the counter 6. From here, the counter 6 again counts the number of clock pulses of the monitoring clock 2 existing in the half cycle of the monitored clock 1.

Each of the comparators 7 and 8 compares a preset value (hereinafter referred to as a “threshold”) with a count value output from the counter 6. When the counter value of the counter 6 exceeds the threshold value, the comparator 7 outputs “L” indicating that the monitored clock 1 has an abnormal frequency,
If it does not exceed the threshold value, it outputs "H" indicating that the frequency is normal. If the counter value of the counter 6 does not exceed the threshold value, the comparator 8 outputs “L” indicating that the monitored clock 1 is abnormal in frequency, and outputs “H” indicating that the frequency is normal if it exceeds the threshold value. . That is, when the frequency of the monitored clock 1 decreases, the count value of the counter 6 increases,
If the threshold value of the comparator 7 is exceeded, it is determined that the frequency is abnormal. Further, when the frequency of the monitored clock 1 increases, the count value of the counter 6 decreases, and when it does not exceed the threshold value of the comparator 8, it is determined that the frequency is abnormal.

Further, the output of the comparator 8 is input to the mono multi 9. The mono multi 9 is a comparator 8
Since a trigger is activated each time an H "output is input, the output of the comparator 7 and the output of the mono-multi 9 are input to the AND circuit 10 and finally output as an abnormal frequency output terminal. If the output of the monitor clock 11 is “H”, the frequency of the monitored clock 1 is normal, and if the output of “11” is “L”, the frequency of the monitored clock 1 is detected as abnormal.

The above operation will be described more specifically with reference to FIG. FIG. 2 shows a monitoring clock 2 in the frequency abnormality detecting section 20a of the frequency abnormality detecting circuit according to the present invention.
4 is a timing chart when the frequency of the monitored clock 1 is normal, assuming that the frequency of the monitored clock 1 is 20 times the frequency of the monitored clock 1. FIG. In FIG. 2, parts that are the same as the parts shown in FIG. 1 are denoted by the same reference numerals.

In such a case, the count value of the counter 6 is
Since the number of clock pulses of the monitoring clock 2 in the half cycle of the monitored clock 1 is 10, it is counted from 0 to 9, and when the count value reaches 9, it is counted until the load signal from the edge detection circuit 5 is input. The value 9 is kept as it is, and the value of 0 is reset by the load signal from the edge detection circuit 5.
Is reset to Here, the threshold for judging that the frequency is abnormal detected by the comparator 7 is set to 11, and the threshold for judging that the frequency is abnormal detected by the comparator 8 is set to 8.

At this time, since the count value does not exceed the threshold value 11 of the comparator 7, it is determined that the output of the comparator 7 is always "H", that is, the frequency of the monitored clock 1 is normal. On the other hand, the comparator 8
Outputs "L" until the count value exceeds the threshold value 8, that is, an abnormal frequency of the monitored clock 1 is output. Even in such a case, it is necessary for the abnormal frequency output terminal 11 to detect that the frequency of the monitored clock 1 is normal.

For this reason, there is provided a mono-multi 9 which keeps outputting the "H" state for a predetermined time when the "H" output of the comparator 8 is inputted when the count value exceeds the threshold value 8. By inputting the output of the mono-multi 9 and the output of the comparator 7 to the AND circuit 10, the presence or absence of the frequency abnormality of the monitored clock 1 is correctly detected at the frequency abnormality output terminal 11, which is the output. Become. In other words, the mono-multi 9 and the AND circuit 10 determine whether or not the comparator 8 has been operated until the count value exceeds the threshold value 8.
Masking is performed so that the L ″ output does not appear at the abnormal frequency output terminal 11.

In FIG. 2, since the frequency of the monitored clock 1 continues to be normal, the counter value exceeds 8 even before the illustrated timing. As a result, the comparator 8 outputs “H”, and as a result, the mono-multi 9 triggered by this output always outputs “H”. In the monomulti 9, the time during which the “H” state is continuously output with the “H” output of the comparator 8 as a trigger can be arbitrarily set by a time constant circuit (not shown) provided outside.

Next, a case where the frequency of the monitored clock 1 becomes abnormal will be described. FIG. 3 is a timing chart when the frequency of the monitored clock 1 is lower than that in FIG. The threshold values of the comparators 7 and 8 are the same as in FIG. In such a case, the count value of the counter 6 is counted from 0, and when the count value exceeds 11, the comparator 7 outputs “L”, that is, an abnormal frequency of the monitored clock 1. Further, since the "L" output of the comparator 7 is input to the EP and ET terminals of the counter 6, the operation of the counter 6 also stops.

Further, the comparator 8 outputs "L", that is, an abnormal frequency of the monitored clock 1 until the count value exceeds the threshold value 8, as in the case of FIG. With the “H” output of the comparator 8 after the value exceeds the threshold value 8 as a trigger, the “H” state is maintained for the time t by the above-described time constant circuit, and “H” is constantly output. As a result, only the frequency abnormality of the monitored clock 1 detected by the comparator 7 is detected at the frequency abnormality output terminal 11.

Next, as a case where the frequency of the monitored clock 1 becomes abnormal, a case where the frequency of the monitored clock 1 becomes higher will be described. FIG. 4 shows the monitored clock 1
FIG. 3 is a timing chart when the frequency is higher than that in FIG. The threshold values of the comparators 7 and 8 are the same as in FIG. In such a case, the count value of the counter 6 is counted from 0 to 7,
Since the count value does not exceed 11, the output of the comparator 7 always outputs "H", that is, the output that the frequency of the monitored clock 1 is normal.

However, since the count value does not exceed 8, the comparator 8 outputs "L", that is, an abnormal frequency of the monitored clock 1. In such a case, since the "H" output is not obtained from the comparator 8, the monomulti 9 loses the trigger source, and the "H" output cannot be continued after the time t described above. "L" is output. Therefore, from the frequency abnormality output terminal 11, "L", that is, the frequency abnormality of the monitored clock 1 is detected simultaneously with "L" of the monomulti 9.

Returning to FIG. 1, the abnormality detection value setting section 20b constituting the frequency abnormality detection circuit according to the present invention will be described. In the abnormality detection value setting section 20b, the count value of the counter 6 is first held in the latch circuit 13 at the timing of the edge detection circuit 5. The count value held in the latch circuit 13 is held in the latch circuit 14 at the next timing of the edge detection circuit 5. That is, assuming that the count value held in the latch circuit 13 is the current count value of the counter 6, the count value held in the latch circuit 14 is the count value of the counter 6 one cycle before the monitored clock 1. become.

The count value held by the latch circuit 13 and the count value held by the latch circuit 14 are compared by a comparator 15, and the number of times the comparison result matches is counted by a protection counter 16. When the count values of the two coincide with each other a predetermined number of times by the protection counter 16, the OR circuit 12 prohibits the latch circuits 13 and 14 from holding the count values at the timing of the edge detection circuit 5. If the count values of the two do not match the number of times set by the protection counter 16 in advance, the protection counter 16 is reset once, and the edge detection circuit is used until the count values match by the number of times set in advance by the protection counter 16. Latch circuit 1 at timing 5
3, and the holding of the count value in the latch circuit 14 is continued.

If the count values of the two counters coincide with each other a predetermined number of times by the protection counter 16, the count value when the frequency of the monitored clock 1 is normal (hereinafter referred to as "normal count value") is used as the count value. I reckon. The threshold value of the comparator 7 is set by adding a predetermined value to the normal count value by the adding circuit 17, and the threshold value of the comparator 8 is set by subtracting the predetermined value from the normal count value by the subtraction circuit 18. Is set.

Next, another embodiment of the present invention will be described. FIG. 5 is a block diagram showing a configuration of the frequency abnormality detection circuit when there are a plurality of monitored clocks. In FIG. 5, reference numerals 1A, 1B, 1C, and 1D denote monitored clocks whose frequency abnormalities are to be monitored, respectively. Is provided. Here, the frequency abnormality monitoring circuits 30A, 30B,
30C and 30D are the same as the frequency abnormality detection circuit shown in FIG. 1, and the internal configuration of each circuit is shown in FIG.
The same parts as those shown in FIG. The monitoring clock 2 is common to the frequency abnormality monitoring circuits 30A to 30D, and the detection results of the frequency abnormality detection circuits 30A to 30D for the monitored clocks 1A to 1D are input to an OR circuit 19 provided outside. Then, the detection result is output to the frequency abnormality output terminal 11.

It is apparent that the present invention is not limited to the above-described embodiment, but can be appropriately modified within the scope of the technical idea of the present invention. For example, in the above-described embodiment, when detecting an abnormal frequency of the monitored clock, the number of clock pulses of the monitoring clock existing in a half cycle of the monitored clock is counted, but the frequency fluctuation of the monitored clock can be detected. If the number of clock pulses of the monitored clock is arbitrary, the number of clock pulses of the monitored clock at an arbitrary timing of the monitored clock can be counted.

[0038]

As described above, according to the present invention, the frequency abnormality detection is performed by counting the number of monitor clock pulses within a predetermined period of the monitored clock using the monitor clock having a higher frequency than the monitored clock. Because of this, the degree of freedom in the frequency relationship between the monitored clock and the monitored clock is increased, and it is possible to provide a frequency abnormality detection circuit that does not particularly require the frequency accuracy of the monitored clock.

Further, according to the present invention, since the detection range of the frequency abnormality is set by adding or subtracting a predetermined value to the count value of the monitored clock in the normal state, the abnormality detection value in the frequency abnormality detection circuit can be arbitrarily set. There is an effect that can be set to.

Further, according to the present invention, there is no need to associate any elements constituting the circuit with the monitored clock and the monitoring clock in timing, and all the circuit elements can be constituted by logic circuits. Therefore, there is an effect that integration can be easily achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frequency abnormality detection circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart when a monitored clock frequency is normal.

FIG. 3 is a timing chart when the monitored clock frequency is abnormal (when it becomes low).

FIG. 4 is a timing chart when the monitored clock frequency is abnormal (when it becomes high).

FIG. 5 is a block diagram of a frequency abnormality detection circuit when there are a plurality of monitored clocks.

FIG. 6 is a block diagram of a conventional frequency abnormality detection circuit.

FIG. 7 is a block diagram of another conventional frequency abnormality detection circuit.

[Explanation of symbols]

 1, 1A, 1B, 1C, 1D Monitored clock input terminal 2 Monitored clock 3 D flip-flop (DFF) 4, 10 AND circuit 5 Edge detection circuit 6 Counter 7, 8, 15 Comparator 9 Monostable multivibrator (mono multi) 11 Frequency abnormality output terminal 12, 19 OR circuit 13, 14 Latch circuit 16 Protection counter 17 Addition circuit 18 Subtraction circuit 20a Frequency abnormality detection unit 20b Abnormal detection value setting unit 30A, 30B, 30C, 30D Frequency abnormality detection circuit

Claims (4)

[Claims] 1. A frequency abnormality detection circuit for detecting an abnormal frequency of a clock to be monitored from outside, wherein the monitoring is performed at a predetermined cycle of the monitored clock using a monitoring clock having a frequency higher than the monitored clock. Counting means for counting the number of clock pulses of the clock;
First comparing means for comparing the count value of the counting means with a first preset value, and a second setting value smaller than the first setting value and a count value of the counting means. And a second comparing means for making a comparison between the first and second comparing means, and a detecting means for detecting an abnormal frequency of the monitored clock in accordance with an output of the first and second comparing means. . 2. The first comparing means outputs a first abnormal signal when the count value exceeds the first set value, and the second comparing means outputs the first abnormal signal when the count value exceeds the second set value. 2. A frequency abnormality detection circuit according to claim 1, wherein a second abnormality signal is output when the frequency falls below a set value. 3. The frequency anomaly detection circuit according to claim 1, further comprising: means for masking a comparison output of said second comparison means for at least a period corresponding to the predetermined period. 4. A counter for counting the number of clock pulses of the monitor clock in a predetermined cycle of the monitor clock, using a monitor clock from the outside as a monitor clock having a frequency higher than the monitor clock, First comparing means for comparing a count value of the counting means with a first set value set in advance, and a second comparing means smaller than the first set value
And a second comparator for comparing the set value of the counter with the count of the counter, and a frequency abnormality for detecting a frequency abnormality of the monitored clock in accordance with an output of the first and second comparators. An abnormality detection value setting circuit used in a detection circuit, wherein: first latch means for sequentially taking in the count value at a cycle of the monitored clock and holding the count value as a first count value; A second latch means for sequentially taking in the first count value and holding it as a second count value; and when the first count value and the second count value match a predetermined number of times, the count value is set to a predetermined value. Frequency abnormality detection, comprising: adding means for adding a value and setting the first set value; and subtracting a predetermined value from the count value to set the second set value. An abnormality detection value setting circuit used for the circuit.