SU771663A1

SU771663A1 - Comparison device

Info

Publication number: SU771663A1
Application number: SU782679310A
Authority: SU
Inventors: Владимир Петрович Гончаренко
Original assignee: За витель
Priority date: 1978-10-02
Filing date: 1978-10-02
Publication date: 1980-10-15

Description

Изобретение относится к области автоматики и вычислительной техники и предназначено для анализа информационного кода с кодом уставки и логической оценки соотношения этих кодов по принципу ’’равно”, ’’больше”, ’’меньше” с последующей выдачей результата сравнения ⁵в исполнительное устройство.The invention relates to the field of automation and computer engineering and is intended for the analysis of an information code with a setpoint code and a logical assessment of the ratio of these codes according to the principle of "equal", "" more "," less ", followed by the output of the comparison result ⁵ to the actuator.

Известно устройство для сравнения, содержащее триггеры, счетчики, генератор тактовых импульсов, формирователи, элементы И, ИЛИ [1].₎₀ A device for comparison is known, containing triggers, counters, a clock, shapers, AND, OR elements [1]. _{) 0}

Недостатком этого устройства является сложность.The disadvantage of this device is complexity.

Наиболее близким к предложенному техническим решением является устройство для сравнения, содержащее счетчик, триггеры, элементы И, _jSИЛИ, НЕ, п переключателей, причем первая шина i-ro переключателя, где i = 1, 2, ..., η, η — число разрядов сравниваемых чисел, соединен с i-ым входом первого элемента И, со входом i-ro элемента НЕ и (i + 3)-ым входом (i + 1)_>м(1 + 2),..., , η-го поразрядных элементов И, вторая шина i-ro переключателя подключена к инверсному выходу i-ro разряда счетчика и к первому входу i-ro поразрядного элемента И, вы- ход которого соединен с i-ым входом первого элемента ИЛИ, выход которого подключен ко входу установки в единичное состояние первого триггера, выход i-ro элемента НЕ соединен со вторым входом i-ro поразрядного элемента И, третьи входы поразрядных элементов И подключены к шине управления устройства, выход первого элемента И соединен со входом установки в единичное срстояние второго триггера, (п + 1)-й вход первого элемента И подключен к шине управления устройства, третья шина i-ro переключателя соединена с прямым выходом i-ro разрядного счетчика (2].Closest to the proposed technical solution is a device for comparison, containing a counter, triggers, elements AND, _jS OR, NOT, n switches, and the first bus i-ro switch, where i = 1, 2, ..., η, η - the number of digits of the numbers being compared, connected to the i-th input of the first AND element, with the i-ro input of the NOT element and the (i + 3) -th input (i + 1) _{> m} (1 + 2), ..., η -th bit elements AND, the second bus of the i-ro switch is connected to the inverse output of the i-ro discharge of the counter and to the first input of the i-ro bit element And, the output of which is connected to the i-th input of the first of the OR element, the output of which is connected to the unit state of the first trigger, the output of the i-ro element is NOT connected to the second input of the i-ro bit element AND, the third inputs of the bit elements AND are connected to the control bus of the device, the output of the first element AND is connected to the input of the unit to the unit distance of the second trigger, the (n + 1) -th input of the first element AND is connected to the control bus of the device, the third bus of the i-ro switch is connected to the direct output of the i-ro bit counter (2].

Недостатком этого устройства 'является его сложность.The disadvantage of this device is its complexity.

Целью изобретения является упрощение устройства.The aim of the invention is to simplify the device.

Поставленная цель достигается тем, что в устройстве, содержащем счетчик, триггеры, элементы И, ИЛИ, НЕ, η переключателей, причем первая шина i-ro переключателя, где i = 1, 2, ...Д п — число разрядов сравниваемых чисел, со-_сединена с i-ым входом первого элемента И, со входом i-ro элемента НЕ и (i + 3)-м входомThis goal is achieved by the fact that in the device containing the counter, triggers, elements AND, OR, NOT, η switches, and the first bus i-ro switch, where i = 1, 2, ... D p - the number of digits of the compared numbers, connected _{to the} i-th input of the first AND element, with the input of the i-ro element NOT and the (i + 3) -th input

771663 4 (i + 1), (i + 2), ..., η-го поразрядных элементов И, вторая шина i-ro переключателя подключена к инверсному выходу i-ro разряда счетчика. и к первому входу i-ro поразрядного элемента И, выход которого соединен с i-ым входом первого элемента ИЛИ, выход которого подключен ко входу установки в единичное состояние первого триггера, выход i-ro элемента НЕ соединен со вторым входом i-ro поразрядного элемента И, третьи входы поразрядных элементов И подключены к шине управления устройства, выход первого элемента И соединен со входом установки в единичное состояние второго триггера, (п + 1)-ый вход первого элемента И подключен к шине управления устройства, третья 15 шина i-ro переключателя соединена с прямым выходом i-ro разряда счетчика, прямой выход первого триггера соединен с первым входом второго элемента ИЛИ, второй вход которого подключен к прямому выходу второго тригге- 20 ра, выход второго элемента ИЛИ соединен со > входом установки в нулевое состояние третьего триггера, инверсные выходы первого и второго триггеров подключены к первому и второму входам второго элемента И соответствен- 25 до, третий вход второго элемента И соединен с шиной управления устройства, а выход второго элемента И подключен ко входу установки в единичное состояние третьего тирггера.771663 4 (i + 1), (i + 2), ..., η-th bit elements And, the second bus of the i-ro switch is connected to the inverse output of the i-ro discharge of the counter. and to the first i-ro input of the bit element AND, the output of which is connected to the i-th input of the first OR element, the output of which is connected to the unit input to the first state of the first trigger, the output of the i-ro element is NOT connected to the second input of the i-ro bit element And, the third inputs of the bit elements AND are connected to the control bus of the device, the output of the first element And is connected to the unit input to the second state of the trigger, (p + 1) -th input of the first element And is connected to the control bus of the device, third 15 i-ro bus switch connection inena with direct output of the i-ro discharge of the counter, the direct output of the first trigger is connected to the first input of the second OR element, the second input of which is connected to the direct output of the second trigger, 20, the output of the second OR element is connected to> the installation input to the zero state of the third trigger, the inverse outputs of the first and second triggers are connected to the first and second inputs of the second element And, respectively, 25 to, the third input of the second element And is connected to the control bus of the device, and the output of the second element And is connected to the installation input to unity the new state of the third tirgger.

Функциональная схема устройства представ- зо лена на чертеже.Functional diagram of the device is shown in the drawing.

Устройство содержит счетчик 1, элементы НЕ 21, 2₂, ...»2_П , переключатели 3], 3₂, ..., 3^ , поразрядные элементы И 4_t, 4₂, .... 4_П , элементы ИЛИ 5, 6, элементы И 7, 8, триггеры 9, ₃₅ The device contains a counter 1, elements NOT 21, 2 ₂ , ... ”2 _П , switches 3], 3 ₂ , ..., 3 ^, bit elements AND 4 _t , 4 ₂ , .... 4 _П , elements OR 5, 6, AND elements 7, 8, triggers 9, ₃₅

10, 11, входные шины 12, 13, 14 управления устройства.10, 11, input buses 12, 13, 14 of the control device.

Устройство работает следующим образом.The device operates as follows.

На переключателях 3_lt 3₂, ..., 3^ в двоичном коде набирают ожидаемое число (напри- ₄θ мер 23, как показано на чертеже). В исходном состоянии все разряды счетчика 1 и триггеры 9, 10, 11 находятся в состоянии ”0”. Сигналами по входной шине 14 заполняется счетчик 1. Затем на входную шину 12 поступает разрешающий 45 импульс конца измерений; если на счетчик. 1 пришла пачка из 23 импульсов, то на счетчике 1 будет код 10111, произойдет поразрядное сравнение кода, на выходе элемента И 8 формируется единичный сигнал, а триггер 10 фикси- ₅θ рует ’’равно”. В случае, если на счетчике 1 код меньше кода уставки, например 10011, то элемент НЕ З₃ в третьем разряде своим выходом даст разрешение на поразрядный элемент И 4₃, а с приходом сигнала по входной шине 12 эле- ₅₅мент ИЛИ 5 срабатывает, триггер 9 фиксирует ’’меньше”. Если на счетчик 1 пришла пачка 31 импульс (11111), то триггеры 9, 10 останутся в нулевом состоянии, а через элемент И 7 на триггере И зафиксируется состояние ’’больше”. Результат сравнения с выходов триггеров 9, 10j 11 воспринимается исполнительным устройством с некоторой задержкой относительно сигнала по входной шине 12. Затем формируется импульс установки в ”0” и срабатывают в ”0” счетчик 1 и триггеры 9, 10, 11. Элемент ИЛИ 6 повышает надежность схемы в целом, подтверждая нулевое состояние триггеров ’’больше” в случае срабатывания одного из триггеров 9 или 10.On the switches 3 _lt 3 ₂ , ..., 3 ^ in the binary code, the expected number is dialed (for example, ₄ θ measures 23, as shown in the drawing). In the initial state, all bits of the counter 1 and the triggers 9, 10, 11 are in the state "0". The signals are filled on the input bus 14 by the counter 1. Then, an enable pulse 45 of the end of the measurements arrives at the input bus 12; if on the counter. 1 a burst of 23 pulses arrived, then on the counter 1 there will be a code 10111, a bitwise comparison of the code will occur, a single signal is generated at the output of the And 8 element, and the trigger 10 fixes ₅ θ “equals”. If on the counter 1 the code is less than the set-point code, for example 10011, then the element NOT ₃ in the third digit will give permission to the bit element And 4 ₃ , and with the arrival of the signal via the input bus 12 element ₅₅ OR 5, trigger 9 captures “less”. If burst 31 of pulse (11111) arrived at counter 1, then triggers 9, 10 will remain in the zero state, and through the And 7 element on the And trigger, the “more” state will be recorded. The result of the comparison with the outputs of the triggers 9, 10j 11 is perceived by the actuator with a certain delay relative to the signal on the input bus 12. Then a pulse is set to “0” and counter 1 and triggers 9, 10, 11 are triggered at “0”. The OR element 6 increases the reliability of the circuit as a whole, confirming the zero state of the triggers is “greater” if one of the triggers 9 or 10 is triggered.

Преимущество предложенного устройства по сравнению с прототипом заключается в его простоте.The advantage of the proposed device compared to the prototype lies in its simplicity.

Claims

The invention relates to the field of automation and computer technology and is intended to analyze an information code with a set code and a logical assessment of the ratio of these codes on the basis of equal, larger, smaller, followed by the output of the comparison result to the actuator. A comparison device is known which contains triggers, counters, a clock pulse generator, drivers, AND, OR 1 elements. The disadvantage of this device is complexity. The closest to the proposed technical solution is a comparison device containing a counter, triggers, AND, OR, NOT, n switches, and the first bus of the i-th switch, where i 1, 2, ..., n, n - the number of bits of the compared numbers, is connected to the i-th input of the first element AND, with the input of the i-ro element NOT and (i + 3) -th input (i + 0, (1 + 2), ...,. n- The second bit of the i-ro switch is connected to the inverse output of the i-th digit of the counter and to the first input of the i-ro of the bit element I, the output of which is connected to the first input of the first of the OR element, the output of which is connected to the installation input to the single state of the first trigger, the output of the i-ro element is NOT connected to the second input of the i-bit of the bit element AND, the third inputs of the bit elements of AND are connected to the control bus of the device, the output of the first element And connected to the installation input to the single state of the second trigger, (n + 1) -th input of the first element I connected to the control bus of the device, the third bus of the i-ro switch is connected to the direct output of the i-ro bit counter 2. The disadvantage of this device is e of complexity. The aim of the invention is to simplify the device. The goal is achieved by the fact that in a device containing a counter, triggers, elements AND, OR, NOT, n switches, and the first tire is an i-ro switch, where I 1, 2, ..., P, n is the number of bits compared numbers, connected to the i-th input of the first element AND, with the input of the i-ro element NOT and the (i + 3) -th input (i + 1), (i + 2), ..., n-ro of the bit elements And, the second i-ro bus switch is connected to the inverse output of the i-ro counter of the counter, and to the first input of the i-ro of the bit AND, the output of which is connected to the i-th input of the first OR element, the output of which on the installation input to the unit state of the first trigger, the output of the i-element of the element is NOT connected to the second input of the 1st load cell And, the third inputs of the load cell And are connected to the control unit of the device, the output of the first I item is connected to the setup input to the unit state of the second flip-flop, (item 1) -input of the first element is connected to the control bus of the device, the third bus of the i-ro switch is connected to the direct output of the 1st bit of the counter, the direct output of the first flip-flop is connected to the first the input of the second element OR, the second the input of which is connected to the forward output of the second trigger, the output of the second element OR is connected to the installation input to the zero state of the third trigger; the inverse outputs of the first and second triggers are connected to the first and second inputs of the second element AND, respectively; io, the third input of the second element AND It is connected to the control bus of the device, and the output of the second element I is connected to the input of the installation in the unit state of the third tierger. Functional diagram of the device shown in the drawing. The device contains a counter 1, elements HE 2i, 22, ..., 2j, switches 3, 3h, ..., 3) -j, bitwise AND elements 4j, 4, ..., 4, elements OR 5, 6 , elements And 7, 8, triggers 9, 10, 11, input bus 12, 13, 14 control device. The device works as follows. On the switch 3i, 3, ..., 3 in binary code, dial the expected number (for example, 23, as shown in the drawing). In the initial state, all bits of the counter 1 and the triggers 9 10, 11 are in the -O state. Signals and the input bus 14 fill the counter 1. Then, the enabling pulse of the end of the measurements goes to the input terminal 12; if on the counter. 1 a packet of 23 pulses has arrived, then the counter 1 will have the code 101 P, a one-by-one code comparison will occur, a single signal will be output at the output of the AND 8 element, and the trigger 10 will fix equal. If on the counter 1 the code is less than the setpoint code, for example 10011, the element NOT Z3 in the third discharge will give permission for the bit 4 and 4z, and with the arrival of the signal on the input bus 12, the element OR 5 will work, the trigger 9 fixes less. If step 31 of pulse 1 (11111) arrived at counter 1, then the flip-flops 9, 10 will remain in zero cocTonifjiH, and through element 7 on the 34 rigger 11 the state will be higher. The result of the comparison with the outputs of the flip-flops 9, lOj 11 is perceived by the actuator by some delay relative to the signal on the input bus 12. The zatel is set to an impulse of setting O and the switch 1 and the triggers 9, 10, 11 are triggered. confirming the zero state of the triggers is greater than the case when one of the triggers 9 or 10 is triggered. The advantage of the proposed device as compared with the prototype lies in its protote. The invention Comparison device containing a counter, triggers, elements AND, OR, NOT, n switches, the first tire of the i-ro switch, where i 1,2, ..., n, n is the number of bits of the numbers being compared, with the i-th input, the first element And, with the input of the i-ro epemet. NOT and (i + 3) -th input of (1 + 1) -th, (1 + 2) -th, .., p-th bit elements AND, the second bus of the 1st switch is connected to the inverse output 1- th counter and to the first input of the 1st bit element AND, the output of which is connected to the 1st input of the first OR element, the output of which is connected to the input of the installation of the first state of the first trigger, the output of the i-ro element is NOT connected to the second the input i-ro of the bit element I, the third inputs of the bit elements AND are connected to the control bus of the device, the output of the first element I is connected to the input of the In the unit state of the second trigger, the () -th input of the first element I is connected to the device control bus, the third bus of the i-switch is connected to the direct output of the i-meter discharge of the counter (characterized in that, in order to simplify the device , in it the direct output of the first trigger is connected to the first input of the second element OR, the second input of which is connected to the direct output of the second trigger, the output of the second element OR is connected to the input of the installation to the zero state of the third trigger, inverse outputs of the first and second triggers connected to the first and second inputs of the second element And, respectively, the third input of the second element And connected to the bus control device, the output of the second element And is connected to the input of the installation in the unit state of the third trigger. Sources of information taken into account during the examination 1. USSR author's certificate N ° 452827,, cl. G 06 F 7/04, 1973.

2. USSR author's certificate number 342184, cl. G 06 F 7/02, 1971 (prototype).