RU2379828C1 - Backup counter - Google Patents

Abstract

FIELD: physics; computer engineering.

SUBSTANCE: invention can be used in computer and pulse engineering for counting and processing digital information. The device consists of m channels, each of which contains an n-bit counter, a unit of n majority decision elements and series-connected majority decision element and monostable multivibrator, as well as a first, second and m^th shift register. Any random failure occurring during operation in any channel of the backup counter will be countered in time T (input pulse period) by restoring correct information in each of the n-bit counters (5).

EFFECT: simple circuit design of the device.

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Description

The invention relates to computing and pulse technology and can be used to build highly reliable redundant systems for counting and processing digital information.

Known redundant pulse counter, a description of which is given in [1]. The device contains 3 pairs of input buses and 3 channels, each of which contains bits, including a trigger, two AND elements and a majority element.

This device allows you to give true information in the presence of failures less than the majority number M [M = (m + 1): 2] in each reserved digit of the counter. But with the accumulation of failures, their number in one category can exceed the number M, as a result of which the information in the counter becomes false, which is unacceptable. The counter itself does not recover information in the category that failed. The probability of failure of the redundant counter increases significantly if the operating time of this counter is sufficiently long.

The closest technical solution to the proposed one is a redundant pulse counter [2], containing m channels, and in each channel an n-bit counter, a block of n majority elements and series-connected majority element and one-shot, the output of which is connected to the input C of the n-bit counter , the parallel recording input D of which is connected to the output bus of a block of n majority elements, and the inputs of the majority element of each channel are connected to the channel inputs of the redundant counter.

This redundant pulse counter can independently recover information lost in the presence of failures, the number of which is less than the majority number M [M = (m + 1): 2] in each digit of the counter.

The disadvantage of this device is that it has a large number of inter-channel connections and, as a result, each such connection requires the installation of an additional matching device (for example, an optocoupler), since each channel is powered by a power source that is galvanically disconnected in many cases from the power source of others channels. In addition, modern digital circuits are implemented on the basis of programmable logic integrated circuits (FPGAs) with a high degree of integration, which allows the implementation of logically complex circuits in one FPGA. A large number of inter-channel communications requires a large number of FPGA conclusions, which leads to the need to use two or more FPGAs or a more expensive FPGA with a large number of conclusions.

The objective of the invention is to simplify the device by reducing inter-channel communications.

This task is achieved by the fact that in a redundant counter containing m channels, and in each channel an n-bit counter, a block of n majority elements and series-connected majority element and one-shot, the output of which is connected to the input C of the n-bit counter, the input is D parallel records of which are connected to the output bus of a block of n majority elements, and the inputs of the majority element of each channel are connected to the inputs of the channels of the redundant counter, a control unit, the first, second and mth registers with moving, in each channel, the output of the single-shot is connected to the input of the control unit, the first and second outputs of which are connected to the PE inputs of the parallel recording of the n-bit counter and the first shift register, respectively, the third output of the control unit is connected to the input C of the first shift register and the inputs From the corresponding shift registers of other channels, the inputs D of which are connected to the output of the first shift register, the inputs D of the parallel recording of the first shift register of each channel are connected to the output bus n-bit with etchika input bus and the first block of n majority of elements, the second and m-I input bus which is connected to the output buses, respectively, the second and m-th shift registers.

Figure 1 shows a block diagram of a redundant counter, where 1 is a majority element, 2 is a one-shot, 3 is a control unit, 4 is a block of n majority elements, 5 is an n-bit counter, 6, 7 and 8 are the first, second and mth shift registers.

The redundant counter contains m channels, each of which includes a majority element 1, a one-shot 2, a control unit 3, an n-bit counter 5, a block of n majority elements 4, the first 6, the second 7 and the mth 8 shift registers. In each channel, the majority element 1 and the one-shot 2 are connected in series, the output of which is connected to the input of the control unit 3 and the input C of the n-bit counter 5, the parallel recording input D of which is connected to the output bus of the block of n majority elements 4. The inputs of the majority element 1 of each channels are connected to the channel inputs of the redundant counter. The first and second outputs of the control unit 3 are connected to the inputs PE for parallel recording of the n-bit counter 5 and the first shift register 6, respectively, the third output of the control unit 3 is connected to the input C of the first shift register 6 and the inputs C of the corresponding shift registers of other channels, inputs D which are connected to the output of the first shift register 6. The inputs D of parallel recording of the first shift register 6 of each channel are connected to the output bus of the n-bit counter 5 and the first input bus of the block of n majority elements 4, second I and m-I input bus which is connected to the output of the second buses respectively 7 and 8 m-th shift registers.

The redundant counter works as follows (for simplicity we assume m = 3 and that all n-bit counters 6 are in the zero state). We assume that when a pulse arrives from the output of a one-shot 2 to the input of the control unit 3, the following signals are generated at its outputs: a pulse P ₁ is formed at the first output, allowing parallel writing to the n-bit counter 5 of the code information of the output bus of the block of n majority elements 4, a pulse P ₂ is generated at the second output, allowing parallel writing to the first shift register 6 of the code information of the output bus of the n-bit counter 5; at the third output, a sequence of n pulses T _{n with} a trace frequency vanishing T ₀ . We assume that the first in time is the pulse P ₂ is formed, then a sequence of pulses T _n is formed and then the pulse P _{1 is formed} . We will also assume that the repetition period of the input pulses is T> nT ₀ , and during the time T all signals are generated from the outputs of the control unit 3: pulses P ₁ , P ₂ and the sequence T _n .

Let pulses synchronized in time arrive at the inputs of each channel of the redundant counter. In this case, when the next input pulses appear at the output of the majority element 1 of each channel, a signal is generated that enters the input of the one-shot 2, which generates a pulse at the input C of the n-bit counter 5 and the input of the control unit 3. This pulse is summed with the contents of the n-bit counter 5 and starts the program for generating signals P ₁ , P _2, and T _{n by} the control unit 3. The signal P _2, which is generated first in time, parallel writes the code information of the n-bit output bus to the first shift register 6 about the counter 5. The sequence T _n of n pulses that is formed later goes to the input C of the first shift register 6 and the inputs C of the corresponding shift registers of other channels and transmits code information from the output of the first shift register 6 to the inputs D of the corresponding shift registers of other channels. Thus, after the passage of the nth pulse of the sequence T _n in each channel, the code state of the second 7 and mth 8 shift registers will correspond to the code state of the n-bit counter 5 of the other channels. As a result, code information of n-bit counters 5 of all channels is generated at the corresponding inputs of a block of n majority elements 4 of each channel (we assume that a block of n majority elements 4 contains n majority elements and the inputs of the jth majority element in each channel, j = 1, 2, ... n, are connected respectively to the outputs of the jth bit of the n-bit counter 5 and the corresponding shift registers of this channel).

At each output j of the output bus of a block of n majority elements 4, a state will be formed corresponding to the state of most jx bits of n-bit counters 5 of all channels. The code state of the output bus of a block of n majority elements 4 of each channel will correspond to the true value if, for some reason, the number of failures in any jx bits does not exceed the number M [M = (m + 1): 2]. The pulse P _1, which is further formed by the control unit 3 at the second output, will write to the n-bit counter 5 all channels of the code state of the block of n majority elements 4. Thus, if for some reason the information in the n-bit counter 5 of any channel turned out to be unreliable, it will be restored by the output pulse P ₁ at the time of writing to the n-bit counter 5 of all channels of the code state of a block of n majority elements 4.

As follows from the above description of the operation of the redundant counter, a random malfunction arising during operation in any of the channels will be counterbalanced during time T (the period of repetition of input pulses) by restoring the correct information in each of the n-bit counters 5.

We estimate the complexity of the known [2] and the proposed device. Suppose the number n = 30. In this case, to implement a redundant counter according to the well-known scheme [2], 120 inter-channel communications will be required (each bit requires 4 inter-channel communications). In addition, the implementation of these links will require the installation of 60 optrons in each channel. If a redundant counter is implemented on an FPGA with 64 pins, three such FPGAs will be required instead of one.

To implement a redundant counter according to the proposed scheme, each channel requires 6 inter-channel communications and the installation of 4 optocouplers (see drawing). The implementation of the redundant counter according to the proposed scheme can be performed on one FPGA in each channel. Otherwise, the proposed scheme of the redundant counter is much simpler than the known solution [2] by reducing the number of inter-channel communications.

The proposed set of features in the solutions considered by the author was not found to solve the problem and does not follow explicitly from the prior art, which allows us to conclude that the technical solution meets the criteria of "novelty" and "inventive step". As the majority elements, counters, shift registers, etc. to implement the device, you can use the logical elements of digital circuits of any series, for example 564, etc.

Literature

1. USSR author's certificate No. 982197, cl. H03K 21/40, 1982. Redundant pulse counter.

2. Patent of the Russian Federation No. 2103815, cl. 7 Н03К 21/40, 21/10, 23/50 from 01/27/98. Reserved counter.

Claims (1)

A redundant counter containing m channels, and in each channel an n-bit counter, a block of n majority elements and a series-connected majority element and one-shot, the output of which is connected to the input C of the n-bit counter, the parallel recording input D of which is connected to the block output bus of n majority elements, and the inputs of the majority element of each channel are connected to the inputs of the channels of the redundant counter, characterized in that a control unit, the first, second and mth shift registers are introduced into each channel the volume in each channel, the output of the one-shot is connected to the input of the control unit, the first and second outputs of which are connected to the PE inputs of the parallel recording of the n-bit counter and the first shift register, respectively, the third output of the control unit is connected to the input C of the first shift register and the inputs C of the corresponding registers the shift of other channels, the inputs D of which are connected to the output of the first shift register, the inputs D of parallel recording of the first shift register of each channel are connected to the output bus of the n-bit counter and the first input bus of the block of n majority elements, the second and mth input buses of which are connected to the output buses of the second and mth shift registers, respectively.