RU2146840C1 - Programmable gate - Google Patents

Abstract

FIELD: computer engineering, in particular, calculation of Boolean functions for failure-resistant systems. SUBSTANCE: goal of invention is achieved by introduced two-cycle calculation of logical functions using disjunction of results output by two intermediate functions. Device decreases time required for repeated programming and uses gates implementing Turing function. The gates keeps their functional completeness for single persistent errors at their inputs. EFFECT: increased speed of calculation upon failures, simplified diagnostics of calculation of Boolean functions. 2 cl, 4 dwg

Description

 The invention relates to computer technology and can be used to calculate logical functions in fault-tolerant computing systems.

 A programmable logic device is known that contains a conjunction implementation matrix, a disjunction implementation matrix, a programmable inverter unit (S.I. Baranov, V.A. Sklyarov, Digital devices on programmable LSIs with a matrix structure, M .: Radio and communications, 1986, p. 43). The disadvantage of this device is the low speed in the reprogramming mode.

The closest in technical essence to the proposed one is a device containing g n-input elements AND (n is the number of information inputs of the device, 2≤g≤2 ⁿ ), t elements OR (t is the number of information outputs of the device), the first, second and third groups of D-triggers, the first group of AND elements with three output states, the group of AND elements with three output states, g • t two-input AND elements, a counter and a decoder, the first, second and third RS-triggers, an additional OR element and a second group elements and with three states output, and the D-inputs of [i + (k-1) • n] -x D-flip-flops of the first and second groups, the first inputs of the corresponding AND elements with three output states of the first group and the first inputs of AND-NOT elements with three output states (1 ≤i≤n; 1≤k≤g) are the ith information input of the device, the outputs of the D-flip-flops of the first group are connected to the second inputs of the corresponding elements AND with three output states of the first group, and the outputs of the D-flip-flops of the second group are connected to the second inputs corresponding NAND elements with three output states, the outputs of which are connected to the outputs corresponding elements And with three output states of the first group, the C-inputs of [(k-1) n + i] -x D-triggers of the first group are connected to the k-th odd output of the decoder, and the C-inputs of the same D-triggers of the second group with the kth even output of the decoder, the outputs of the [(k-1) n + i] -x elements And with three output states of the first group are connected to the inputs of the k-th n-input element And, the output of which is connected to the first inputs [k + (j -1) g] -x two-input elements AND (1≤j≤t), the second inputs of which are connected to the outputs of the corresponding D-triggers of the third group, and the outputs - with the k-th input of j-x OR elements, the information outputs of the counter are connected to the inputs of the decoder, and the counting input of the counter is the clock input of the device, the first inputs of the second group of AND elements with three output states are connected to the outputs of the corresponding OR elements, and the second inputs are inverted with the third RS-trigger, S -the input of which is connected to the zero output of the decoder, and the R-input - with the output of an additional OR element, the output of the j-th AND element with three output states of the second group is connected to the D-inputs [k + (j-1) g] -x D- triggers of the third group and are is the corresponding information output of the device, the p-th output of the decoder (1≤p≤g) is connected to the C-inputs of [(p-1) t + j] -x D-flip-flops of the third group, S-inputs of the first and second RS-flip-flops connected respectively with the gth output of the decoder and with the output of the counter overflow, the output of the first RS-trigger is the output of the programming indication of the OR elements of the device, the output of the second RS-trigger is connected to the first input of the additional OR element and is the output of the programming indication of the AND elements of the device, R- inputs of D- and RS-flip-flops and second input q additional OR element is the reset input of the device (Aut. St. USSR N 1444892, class G 11 C 17/00, G 06 F 7/00, 1988).

 A disadvantage of the known device is the low speed of the calculation of logical functions in the presence of failures.

 The technical means of the prototype are focused on the calculation of logical functions in the absence of failures without any restructuring (reconfiguration) of the circuit. If the technical means of implementing one of the functions fail, which is determined by testing using external technical means, this function can be calculated on the remaining technical means with preliminary reprogramming of the entire device and storing the result in technical means external to the prototype device. However, this significantly reduces performance. In addition, if there is one failure that makes it impossible to calculate for each function, the prototype device is unable to calculate logical functions even with reprogramming.

 All this reduces the speed of the device in the tasks of ensuring operability in the presence of failures.

 The aim of the invention is to improve performance when calculating logical functions in the conditions of failure.

, а старший неинверсный разряд этих входов является соответствующим n-м неинверсным входом группы 2n•m входов парафазных входных переменных, выходы элементов ИЛИ группы m(n-1) элементов ИЛИ подключены к соответствующим i-м инверсным входам парафазных входных переменных соответствующего из m блоков вычисления функций

, а старший инверсный разряд этих входов является соответствующим n-м инверсным входам группы 2n•m входов парафазных входных переменных, входы сброса блоков вычисления функций являются входом сброса устройства, входы синхронизации блоков вычисления функций являются входом синхронизации устройства, дополнительные входы сброса блоков вычисления функций являются группой m входов дополнительного сброса устройства, входы реконфигурации m блоков вычисления функций являются группой m входов реконфигурации блоков вычисления функций при отказах, входы типа реконфигурации m блоков вычисления функции при отказах являются группой m входов типа реконфигурации блоков вычисления функций при отказах, выходы неинверсного значения функции блоков вычисления функций являются соответствующими разрядами группы m выходов значений функции устройства, выходы инверсного значения функции блоков вычисления функций являются соответствующими разрядами группы m выходов инверсных значений функций устройства, выходы готовности результатов вычислений блоков вычисления функций являются группой m выходов готовности результатов вычисления функций устройства, каждый блок вычисления функций содержит группу 4•2ⁿ элементов И с тремя состояниями на выходе, два D-триггера, T-триггер, RS-триггер фиксации импульса, пять элементов ИЛИ, три элемента И, четыре инвертора, n групп элементов 2•2 НЕ-И-ИЛИ (в каждую i-ю группу входит 2^n-1 элементов,

), элемент задержки, дополнительную группу элементов И с тремя состояниями на выходе, причем входы управления нечетных элементов И с тремя состояниями на выходе из группы 4•2ⁿ элементов И с тремя состояниями на выходе подключены к неинверсному выходу T-триггера, инверсный выход которого подключен ко входам управления четырех элементов И с тремя состояниями на выходе из группы 4•2ⁿ элементов И с тремя состояниями на выходе, информационные выходы которых являются соответствующими разрядами входов настройки блока, информационные входы нечетных элементов И с тремя состояниями на выходе из первой половины группы 4•2ⁿ элементов И с тремя состояниями на выходе подключены к соответствующим j-м элементам второй половины входов настройки,

, информационные входы нечетных элементов И с тремя состояниями на выходе из второй половины 4•2ⁿ элементов И с тремя состояниями на выходе подключены к соответствующим M разрядам первой половины входов настройки,

, выходы нечетных элементов И с тремя состояниями на выходе группы 4•2ⁿ элементов И с тремя состояниями на выходе объединены с выходами соответствующих четных элементов И с тремя состояниями на выходе и подключены к соответствующим нечетным входам соответствующего элемента 2•2 НЕ-И-ИЛИ первой группы из n групп элементов 2•2 НЕ-И-ИЛИ (по две пары нечетный - четный элемент И с тремя состояниями выхода на каждый элемент 2•2 НЕ-И-ИЛИ, четные входы элементов 2•2 НЕ-И-ИЛИ каждой S-й группы,

, элементов 2•2 НЕ-И-ИЛИ являются соответствующими разрядами входов парафазных входных переменных блока (второй вход каждого элемента 2•2 НЕ-И-ИЛИ S-й группы является входом X_S, четвертый -

), выходы элементов 2•2 НЕ-И-ИЛИ S-й группы,

, где n - число входных переменных, подключены к соответствующим нечетным входам элементов 2•2 НЕ-И-ИЛИ S+1 группы, причем к каждому элементу 2•2 НЕ-И-ИЛИ в группы

подключены выходы двух элементов i-1 групп, выход единственного элемента 2•2 НЕ-И-ИЛИ последней n-й группы из n групп элементов 2•2 НЕ-И-ИЛИ подключен к информационному входу первого D-триггера, второй вход этого элемента подключен к выходу первого элемента ИЛИ, а четвертый вход этого элемента 2•2 НЕ-И-ИЛИ n-й группы подключен к выходу второго элемента ИЛИ, первые входы первого и второго элементов ИЛИ подключены к выходам первого и второго элементов И соответственно, второй вход первого элемента ИЛИ подключен к объединенным выходами первого и второго элементов И с тремя состояниями на выходе дополнительной группы элементов И с тремя состояниями при выходе, второй вход второго элемента ИЛИ подключен к объединенным выходам третьего и четвертого элементов И с тремя состояниями на выходе дополнительной группы элементов И с тремя состояниями на выходе, вторые входы первого и второго элементов И, входы второго и четвертого инвертора являются видом реконфигурации блока при отказах, первый вход первого элемента И и вход первого инвертора являются входом типа реконфигурации блока при отказах, выход первого инвертора подключен к первому входу второго элемента И, вход обнуления первого D-триггера и первый вход четвертого элемента ИЛИ являются входом сброса блока, входы синхронизации первого и второго D-триггеров, счетный вход T-триггера, вход элемента задержки являются входом синхронизации блока, выход второго инвертора подключен ко второму входу четвертого элемента ИЛИ, третий вход которого является входом дополнительного сброса блока, выход четвертого элемента ИЛИ подключен ко входам обнуления второго D-триггера, RS-триггера фиксации импульса и T-триггера, выход первого D-триггера подключен к информационному входу второго D-триггера и первому входу третьего элемента ИЛИ, второй вход которого подключен к выходу второго D-триггера, выход третьего элемента ИЛИ является выходом значения функции блока и подключен ко входу третьего инвертора и первому входу пятого элемента ИЛИ, выход третьего инвертора является выходом инверсного значения функции блока, выход четвертого инвертора подключен ко второму входу пятого элемента ИЛИ, третий вход которого подключен ко входу третьего элемента И, выход пятого элемента ИЛИ является выходом готовности результатов вычисления функций блока, первый вход третьего элемента И подключен к выходу RS-триггера функции импульса, а второй вход третьего элемента И подключен к инверсному выходу T-триггера, который также подключен ко входам управления нечетных элементов И с тремя состояниями на выходе дополнительной группы элементов с тремя состояниями на выходе, ко входам управления четных элементов которой подключен неинверсный выход T-триггера, информационные входы первого и четвертого элементов И с тремя состояниями на выходе являются n-м инверсным входом x_n парафазных входных переменных блока, а информационные входы второго и третьего элементов И с тремя состояниями на выходе дополнительной группы элементов И с тремя состояниями на выходе являются n-м инверсным входом

парафазных входных переменных блока.This goal is achieved by the fact that a programmable logic device containing the first, second and third groups of D-flip-flops of m • 2 ^{n each} (n is the number of input variables, m is the number of output functions), the third group of D-flip-flops of 2 (n- 1) m, a group of m (n-1) AND elements, a counter, a group of m • 2 ⁿ AND elements with three states at the output, a decoder, a group of m (n-1) OR elements, with the reset input of the first and second D-triggers and the third group, the counter is the reset input of the device, the counting input of the counter is the programming input of the device Twa, and data outputs of the counter are connected to data inputs of the decoder, non-inverting outputs of D-flip-flops of the second group are connected to control inputs of respective AND gates with three states on the group m output • 2 ⁿ elements and a tri-state output, a noninverted outputs of D-flip-flops third group connected to the second inputs of respective aND gates group m • ⁿ 2 elements and according to the invention the second group administered 2 m • ⁿ elements and a tri-state output and calculation functions of m blocks, the driving input elements of the second group of m • 2 ⁿ elements and a tri-state output connected to the inverted outputs of the respective D-flip-flops of the second group D-flip-flops, and the data inputs of the elements of the second group of m • 2 ⁿ elements and a tri-state output are appropriate expansion inputs the corresponding group of m groups of expansion inputs, the outputs of the AND elements with three states at the output are combined and connected to the input settings of the corresponding of the m function calculation blocks, the first output of the decoder is connected to the input m synchronization of D-flip-flops of the first group, the second decoder output is connected to the synchronization inputs of the D-flip-flops of the second group, the third output of the decoder is connected to the synchronization inputs of the D-flip-flops of the third group, the fourth decoder output is the output of the device programming end, the information inputs of the D-flip-flops of the first and the second group are the corresponding expansion inputs of the corresponding of m groups of expansion inputs, the information inputs of the D-flip-flops of the third group are 2 (n-1) expansion inputs respectively consisting of m groups of expansion inputs, the first inputs of AND elements of the group of m (n-1) AND elements are the corresponding of n-1 non-inverse inputs of the group 2n • m inputs of paraphase input variables (2m bits for each block of function calculation), the first inputs of elements OR groups of m (m-1) elements OR are corresponding from n-1 inverse inputs of a group of 2n • m inputs of paraphase input variables (2m bits for each of m function calculation blocks), outputs of elements AND of a group of m (n-1) elements And connected to the corresponding i-th inverse paraphase inputs variables of the corresponding of m blocks of function calculation

and the senior non-inverse discharge of these inputs is the corresponding nth non-inverse input of the group of 2n • m inputs of paraphase input variables, the outputs of the OR elements of the group of m (n-1) elements OR are connected to the corresponding i-th inverse inputs of the paraphase input variables of the corresponding m blocks function calculations

and the highest inverse discharge of these inputs corresponds to the nth inverse inputs of the group of 2n • m inputs of paraphase input variables, the reset inputs of the function calculation blocks are the device reset input, the synchronization inputs of the function calculation blocks are the device synchronization input, the additional reset inputs of the function calculation blocks are a group of m inputs of additional device reset, inputs of reconfiguration of m function calculation blocks are a group of m inputs of reconfiguration of function calculation blocks at failure zh, inputs of the reconfiguration type of m function calculation blocks for failures are a group of m inputs of reconfiguration type of function calculation blocks for failures, outputs of a non-inverse function value of function calculation blocks are the corresponding bits of the group m outputs of the function values of the device, outputs of the inverse value of the function of function calculation blocks are the corresponding bits groups of m outputs of inverse values of device functions, outputs of the readiness of the results of calculations of function calculation blocks are groups oh m readiness outputs of the results of calculating the functions of the device, each unit of calculating the functions contains a group of 4 • 2 ⁿ AND elements with three output states, two D-flip-flops, T-flip-flop, RS-flip-flop, five OR elements, three AND elements, four inverters, n groups of elements 2 • 2 NOT-AND-OR (each i-th group includes 2 ^n-1 elements,

), a delay element, an additional group of AND elements with three states at the output, and the control inputs of the odd AND elements with three states at the output of the group of 4 • 2 ⁿ AND elements with three states at the output are connected to the non-inverse output of the T-trigger, whose inverse output is connected to the inputs of the four control elements and a tri-state output from group 4 • 2 ⁿ elements and a tri-state output, information outputs of which are corresponding bits of tuner inputs, data inputs neche GOVERNMENTAL AND gates with three states on the output from the first half of the group 4 • 2 ⁿ elements and a tri-state output connected to the corresponding j-th elements of the second half of the setup input,

, information inputs of odd AND elements with three states at the output from the second half 4 • 2 ⁿ AND elements with three states at the output are connected to the corresponding M bits of the first half of the settings inputs,

, the outputs of the odd elements AND with three states at the output of a group of 4 • 2 ⁿ elements AND with three states at the output are combined with the outputs of the corresponding even elements AND with three states at the output and connected to the corresponding odd inputs of the corresponding element 2 • 2 NOT-AND-OR the first group of n groups of elements 2 • 2 NOT-AND-OR (two odd pairs - even AND element with three output states for each element 2 • 2 NOT-AND-OR, even inputs of elements 2 • 2 NOT-AND-OR each S-th group,

, elements 2 • 2 NOT-AND-OR are the corresponding bits of the inputs of the paraphase input variables of the block (the second input of each element 2 • 2 NOT-AND-OR of the S-th group is the input X _S , the fourth -

), outputs of elements 2 • 2 NOT-AND-OR S-th group,

, where n is the number of input variables, connected to the corresponding odd inputs of elements of 2 • 2 NOT-AND-OR S + 1 groups, and to each element 2 • 2 NOT-AND-OR in groups

the outputs of two elements of i-1 groups are connected, the output of a single element 2 • 2 NOT-AND-OR of the last n-th group of n groups of elements 2 • 2 NOT-AND-OR is connected to the information input of the first D-trigger, the second input of this element connected to the output of the first OR element, and the fourth input of this element 2 • 2 NOT-AND-OR of the nth group is connected to the output of the second OR element, the first inputs of the first and second OR elements are connected to the outputs of the first and second elements AND, accordingly, the second input the first element OR connected to the combined outputs of the first and watts of the second AND element with three states at the output of an additional group of AND elements with three states at the output, the second input of the second OR element is connected to the combined outputs of the third and fourth AND elements with three states at the output of an additional group of AND elements with three states at the output, the second inputs of the first and the second element And, the inputs of the second and fourth inverter are a type of reconfiguration of the block in case of failure, the first input of the first element And and the input of the first inverter are an input of the type of reconfiguration of the block at failures, the output of the first inverter is connected to the first input of the second element AND, the zeroing input of the first D-trigger and the first input of the fourth element OR are the block reset input, the synchronization inputs of the first and second D-triggers, the counting input of the T-trigger, the input of the delay element are the input block synchronization, the output of the second inverter is connected to the second input of the fourth OR element, the third input of which is the input of the additional block reset, the output of the fourth OR element is connected to the zeroing inputs of the second D-trigger, RS-t a pulser and a T-trigger lock, the output of the first D-trigger is connected to the information input of the second D-trigger and the first input of the third OR element, the second input of which is connected to the output of the second D-trigger, the output of the third OR is the output of the function value of the block and connected to the input of the third inverter and the first input of the fifth OR element, the output of the third inverter is the output of the inverse value of the block function, the output of the fourth inverter is connected to the second input of the fifth OR element, the third input of which is connected but to the input of the third AND element, the output of the fifth OR element is the readiness output of the block function calculation results, the first input of the third AND element is connected to the output of the RS-trigger of the pulse function, and the second input of the third AND element is connected to the inverse output of the T-trigger, which is also connected to the control inputs of odd elements AND with three states at the output of an additional group of elements with three states at the output, to the control inputs of even elements of which a non-inverse output of the T-trigger is connected, the information ode first and fourth elements and a tri-state output are n-th inverse input x _n paraphase input variables of the block, and information inputs of the second and third elements and a tri-state output further group of elements and a tri-state output are n-m inverse input

paraphase input block variables.

 The essence of the invention is to increase the speed when calculating logical functions in the conditions of failure by introducing the discipline of calculating logical functions in two clock cycles for two subfunctions with a disjunction of intermediate results.

The essence of the newly introduced discipline is as follows:
a) in disconnecting half of the logic elements that calculate the logical function in accordance with the paraphase input signals and setting codes;
b) in calculating the first subfunction of a logical function on half of the logic elements using half of the tuning codes with storing the result;
c) in the calculation of the second subfunction of a logical function on the same half of the logical elements using the second half of the setup codes with the replacement of the highest variable by its inversion and storing the result;
d) in the disjunction of the results of the calculation of subfunctions;
e) to use 2 • 2 NON-AND-OR elements for calculating the logical functions that maintain functional completeness with a single constant input failure (the so-called functionally complete tolerant elements that implement S. Tyurin's function).

 The invention is realized through the introduction of the following set of design features - new elements and relationships that meet the criterion of "novelty."

 The introduction of function calculation blocks with the proposed structure and the corresponding relationships allows us to calculate logical functions both in the absence of failures and in the event of failures, realizing the discipline of computing logical functions in two clock cycles over two subfunctions with a disjunction of intermediate results.

 The introduction of new connections for the group of m (n-1) AND elements, the group of m (n-1) OR elements allows you to connect significant variables from the group of 2n • m inputs of the device's paraphase input variables to the inputs of the paraphase input variable variables of the device as in the case of calculating logical functions in the absence of failures, and if they exist during the implementation of the newly introduced discipline.

The introduction of the second group of m • 2 ⁿ OR elements with three states at the output and the corresponding connections, as well as new connections for the first group of m • 2 ⁿ AND elements with three states at the output allows you to connect the settings of function calculation blocks to the inputs as tuning information from the outputs the first group of D-flip-flops, as well as external inputs of m groups of expansion inputs in order to expand the capacity in the process of computing in the absence of failures, as well as in the process of implementing a new discipline.

 The introduction of new relationships for the D-flip-flops of the first group allows for the configuration of function calculation blocks for the implementation of calculations in them, both in the process of computing in the absence of failures and in the process of implementing a new discipline.

 The introduction of new connections for the D-flip-flops of the second group makes it possible to connect to the tuning input of the discharge function calculation blocks of the m groups of expansion inputs to ensure the expansion of the capacity in the calculation process in the absence of failures, as well as in the process of implementing a new discipline.

 The introduction of new relationships for the D-triggers of the second group allows them to be programmed for their subsequent participation in the implementation of calculations in the absence of failures, and in the process of implementing a new discipline.

 The introduction of new relationships for the decoder allows programming D-flip-flops of the first, second and third groups for their subsequent participation in the implementation of computations of logical functions in the absence of failures, and in the process of implementing a new discipline.

 Thus, the proposed technical solution meets the criterion of "significant differences" because in the known devices - analogue and prototype is not achieved the property of improving performance when calculating logical functions in the conditions of failure due to the absence of the specified set of design features.

 When using the proposed programmable logic device, a positive effect of increasing speed can be obtained when calculating logical functions in the event of failure. A quantitative calculation is given in the feasibility study section.

 In FIG. 1 shows a functional electrical diagram of the proposed programmable logic device.

 In FIG. 2 shows a functional electric circuit of the i-th function calculation unit.

 In FIG. Figure 3 shows the time diagram of the operation of the function calculation unit: a) in the calculation mode in the absence of failures and b) in the calculation mode in the presence of failures.

The programmable logic device contains the first 1, second 2, and third 3 groups of D-flip-flops, in the first and second groups m • 2 ⁿ D-flip-flops, where n is the number of input variables, m is the number of output functions, in the third group 2 (n -1) • m D-flip-flops, group m • (n-1) AND elements 4, counter 5, first group m • 2 ⁿ AND elements with three output states, decoder 7, group m (n-1) elements OR 8, the second group of m • 2 ⁿ elements AND 9 with three output states, m function calculation blocks 10.1-10m, a group of 2m • m inputs of paraphase input variables 11 of 2m bits for each block kov 10.1-10.m, m groups of expansion inputs 12.1-12m, each of which contains 2 ⁿ bits, reset input 13, programming input 14, a group of m outputs of function values 15, 1.1-15. m.1, a group of m outputs of inverse values of functions 15.1.2-15.m.2, a group of m outputs of readiness of the results of calculation of functions 15.1.3-15.m.3, an output of the end of programming 16, a synchronization input 17, a group of m inputs of reconfiguration blocks for calculating functions for failures 18.1-18.m, a group of m inputs of the type of reconfiguration of blocks for calculating functions for failures 19.1-19.m.

; элемент задержки 38, дополнительную группу элементов И с тремя состояниями на выходе 39, группу дополнительных входов сброса 40.1...10.m.Each function calculation block 10.1-10.m contains a group of 4 • 2 ⁿ AND elements with three states at output 20, first 21 and second 22 D-flip-flops, T-flip-flop 23, RS-flip-flop 24, first 25, second 26 , third 27, fourth 28 and fifth 29 elements OR, first 30, second 31 and third 32 elements AND, first 33, second 34, third 35 and fourth 36 inverters, n groups 37.1-37.n elements 2 • 2 NOT-AND -OR, each group includes 2 ⁿⁱ elements, where i is the group number

; delay element 38, an additional group of AND elements with three states at output 39, a group of additional reset inputs 40.1 ... 10.m.

The reset inputs of the D-flip-flops of the first 1, second 2, third 3 groups, counter 5 are the reset input 13 of the device. The counting input of the counter 5 is the programming input 14 of the device. The information outputs of counter 5 are connected to the information inputs of the decoder 7. The non-inverse outputs of the D-flip-flops of the second group 2 are connected to the control inputs of the corresponding elements And with three states at the output of the group m • 2 ⁿ elements And with three states at output 6.

The non-inverse outputs of the D-flip-flops of the third group 3 are connected to the second inputs of the corresponding elements AND of the group m • 2 ⁿ elements AND 4.

The control inputs of the elements of the second group of m • 2 ⁿ AND elements with three states at the output 9 are connected to the inverse outputs of the corresponding D-triggers of the second group of D-flip-flops 2. The information inputs of the elements of the second group of m • 2 ⁿ elements AND with three states at the output 9 are corresponding expansion inputs of the corresponding group of m groups of expansion inputs 12.1 ... 12.m. The outputs of the And elements with three states at the output of groups 6, 9 are combined and connected to the settings inputs 10.1.2 ... 10.m.2 of the corresponding m calculation function blocks 10.1 ... 10.m.

, а старший неинверсный разряд этих входов является соответствующим n-м неинверсным входом группы 2n•m входов парафазных входных переменных 11. Выходы элементов ИЛИ группы m(n-1) элементов ИЛИ 8 подключены к соответствующим i-м инверсным входам парафазных входных переменных 10.j.1 соответствующего j-го из m блоков вычисления функций 10.1...10.m

, а старший инверсный разряд этих входов является соответствующим n-м инверсным входом группы 2n•m входов парафазных входных переменных 11. Входы сброса блоков вычисления функций 10.1. . .10.m являются входом сброса 13 устройства. Входы синхронизации блоков вычисления функций 10.1...10.m являются входом синхронизации 17 устройства. Дополнительные входы сброса блоков вычисления функций 10.1...10. m являются группой m входов дополнительного сброса 40.1...40.m устройства. Входы реконфигурации m блоков вычисления функций 10.1...10.m являются группой m входов реконфигурации 18.1...18.m блоков вычисления функций при отказах. Входы типа реконфигурации m блоков вычисления функций 10.1...10.m при отказах являются группой m входов типа реконфигурации блоков вычисления функций при отказах 19.1...19.m. Выходы неинверсного значения функции блоков вычисления функций 10.1...10.m являются соответствующими разрядами группы m выходов значений функции 15.1.1...15.m.1 устройства. Выходы инверсного значения функции блоков вычисления функций 10.1...10.m являются соответствующими разрядами группы m выходов инверсных значений функций 15.1.2...15.m.2 устройства. Выходы готовности результатов вычислений блоков вычисления функций 10.1. . . 10. m являются группой m выходов готовности результатов вычисления функций 15.1.3...15.m.3 устройства.The first output 7.1 of the decoder 7 is connected to the synchronization inputs of the D-triggers of the first group 1. The second output 7.2 of the decoder 7 is connected to the synchronization inputs of the D-triggers of the second group 2. The third output 7.3 of the decoder 7 is connected to the synchronization inputs of the D-triggers of the third group 3. Fourth output 7.4 decoder 7 is the output end of the programming 16 device. The information inputs of the D-flip-flops of the first 1 and second groups 2 are the corresponding expansion inputs of the corresponding of the m groups of extension inputs 12.1 ... 12.m. The information inputs of the D-flip-flops of the third group 3 are 2 (n-1) expansion inputs of the corresponding of the m groups of extension inputs 12.1. . .12.m. The first inputs of the elements AND of the group m (n-1) elements AND 4 are the corresponding of n-1 non-inverse inputs of the groups 2n • m inputs of the paraphase input variables 11 (2m bits for each block of function calculation). The first inputs of OR elements of a group of m (n-1) elements of OR 8 are the corresponding of n-1 inverse inputs of groups of 2n • m inputs of paraphase input variables 11 (2m bits for each block of m function calculation blocks). The outputs of the AND elements of the group m (n-1) elements AND 4 are connected to the corresponding i-th non-inverse inputs of the paraphase input variables 10.j.1 of the corresponding j-th of m function calculation blocks 10.i-10.m

, and the senior non-inverse discharge of these inputs is the corresponding nth non-inverse input of the group of 2n • m inputs of paraphase input variables 11. The outputs of the OR elements of the group m (n-1) elements of OR 8 are connected to the corresponding i-inverse inputs of the paraphase input variables 10. j.1 of the corresponding jth of m blocks of function calculation 10.1 ... 10.m

, and the senior inverse discharge of these inputs is the corresponding nth inverse input of the group of 2n • m inputs of paraphase input variables 11. Reset inputs of function calculation blocks 10.1. . .10.m are the reset input 13 of the device. The synchronization inputs of the function calculation blocks 10.1 ... 10.m are the synchronization input 17 of the device. Additional reset inputs for function calculation blocks 10.1 ... 10. m are the group m of inputs of additional reset 40.1 ... 40.m of the device. The reconfiguration inputs of m function calculation blocks 10.1 ... 10.m are the group of m reconfiguration inputs 18.1 ... 18.m of function calculation blocks in case of failures. The inputs of the reconfiguration type of m function calculation blocks 10.1 ... 10.m for failures are the group of m inputs of the reconfiguration type of function calculation blocks of failures 19.1 ... 19.m. The outputs of the non-inverse value of the function of the function calculation blocks 10.1 ... 10.m are the corresponding bits of the group m of the outputs of the values of the function 15.1.1 ... 15.m.1 of the device. The outputs of the inverse value of the function of the function calculation blocks 10.1 ... 10.m are the corresponding bits of the group m of the outputs of the inverse values of the functions 15.1.2 ... 15.m.2 of the device. Outputs of the readiness of the results of calculations of function calculation blocks 10.1. . . 10. m are the group of m outputs of the readiness of the results of the calculation of the functions 15.1.3 ... 15.m.3 of the device.

. Информационные входы нечетных элементов И с тремя состояниями на выходе из второй половины 4•2ⁿ элементов И с тремя состояниями на выходе 20 подключены к соответствующим M-м разрядам первой половины входов настройки 10. i.2.1,

. Выходы нечетных элементов И с тремя состояниями на выходе группы 4•2ⁿ элементов И с тремя состояниями на выходе 20 объединены с выходами соответствующих четных элементов И с тремя состояниями на выходе и подключены к соответствующим нечетным входам соответствующего элемента 2•2 НЕ-И-ИЛИ первой группы 37.1 из n групп элементов 2•2 НЕ-И-ИЛИ 37.1...37.n (по две пары нечетный-четный элемент И с тремя состояниями на выходе на каждый элемент 2•2 НЕ-И-ИЛИ группы 37.1). Четные входы элементов 2•2 НЕ-И-ИЛИ каждой S-й 37.5 S группы

элементов 2•2 НЕ-И-ИЛИ 37 являются соответствующими разрядами входов парафазных входных переменных 10.i.1 блока, где i - номер блока (второй вход каждого элемента 2•2 НЕ-И-ИЛИ S-й группы является входом X_S, четвертый

).The control inputs of the odd elements AND with three states at the output of the group of 4 • 2 ⁿ elements And with three states at the output 20 are connected to the non-inverse output of the T-trigger 23. The inverse output of the T-trigger 23 is connected to the control inputs of the even elements And with three states on leaving the group of 4 • 2 ⁿ AND elements with three states at the output 20, the information inputs of which are the corresponding bits of the setting inputs of the unit 10.i.2, where i is the block number. The information inputs of the odd AND elements with three states at the output of the first half of the group of 4 • 2 ⁿ AND elements with three states at the output 20 are connected to the corresponding jth digits of the second half of the settings 10. ij2,

. The information inputs of the odd AND elements with three states at the output from the second half of 4 • 2 ⁿ AND elements with three states at the output 20 are connected to the corresponding M-th digits of the first half of the settings 10. i.2.1,

. The outputs of the odd AND elements with three states at the output of a group of 4 • 2 ⁿ elements AND with three states at the output 20 are combined with the outputs of the corresponding even elements AND with three states at the output and connected to the corresponding odd inputs of the corresponding element 2 • 2 NOT-AND-OR the first group 37.1 of n groups of elements 2 • 2 NOT-AND-OR 37.1 ... 37.n (two pairs of an odd-even AND element with three states at the output of each element 2 • 2 NOT-AND-OR groups 37.1) . Even inputs of elements 2 • 2 NOT-AND-OR of each S-th 37.5 S group

elements 2 • 2 NON-AND-OR 37 are the corresponding bits of the inputs of the paraphase input variables 10.i.1 of the block, where i is the block number (the second input of each element 2 • 2 NOT-AND-OR of the S-th group is the input X _S fourth

)

, где n - число входных переменных, подключены к соответствующим нечетным входам элементов 2•2 НЕ-И-ИЛИ S+1 группы 37.5+1, причем к каждому элементу 2•2 НЕ-И-ИЛИ l группы

подключены выходы двух элементов l-1 группы. Выход единственного элемента 2•2 НЕ-И-ИЛИ 37.n последней n-ой группы из n групп элементов 2•2 НЕ-И-ИЛИ 37.1...37.n подключен к информационному входу D-триггера 21. Второй вход этого элемента подключен к выходу первого элемента ИЛИ 25, а четвертый вход этого элемента 2•2 НЕ-И-ИЛИ n-й группы 37.n подключен к выходу второго элемента 26. Первые выходы первого 25 и второго 26 элементов ИЛИ подключены к выходам первого 30 и второго 31 элементов И соответственно. Второй вход первого элемента ИЛИ 25 подключен к объединенным выходам первого и второго элементов И с тремя состояниями на выходе дополнительной группы элементов И с тремя состояниями на выходе 39. Второй вход второго элемента ИЛИ 26 подключен к объединенным выходам третьего и четвертого элементов И с тремя состояниями на выходе дополнительной группы элементов И с тремя состояниями на выходе 39. Вторые выходы первого 30 и второго 31 элементов И, входы второго 34 и четвертого 36 инвертора являются входом реконфигурации 18.i блока при отказах, i - номер блока. Первый вход первого элемента И 30 и вход первого инвертора 33 являются входом типа реконфигурации 19.i блока при отказах. Выход первого инвертора 33 подключен к первому входу второго элемента И 31. Вход обнуления первого D-триггера 21 и первый вход четвертого элемента ИЛИ 28 являются входом сброса 13 блока. Входы синхронизации первого 21 и второго 22 D-триггеров, счетный вход T-триггера 23, вход элемента задержки 38 являются входом синхронизации 17 блока. Выход второго инвертора подключен ко второму входу четвертого элемента ИЛИ 28, третий вход которого является входом дополнительного сброса 40.i блока (i - номер блока). Выход четвертого элемента ИЛИ 28 подключен ко входам обнуления второго D-триггера 22, RS-триггера фиксации импульса 24 и T-триггера 23. Выход первого D-триггера 21 подключен к информационному входу второго D-триггера 22 и первому входу третьего элемента ИЛИ 27, второй вход которого подключен к выходу второго D-триггера 22. Выход третьего элемента ИЛИ 27 является выходом значения функции 15.i.1 блока и подключен ко входу третьего инвертора 35 и первому входу пятого элемента ИЛИ 29. Выход третьего инвертора 35 является выходом инверсного значения функции 15.i.2 блока. Выход четвертого инвертора 36 подключен ко второму входу пятого элемента ИЛИ 29, третий вход которого подключен к выходу третьего элемента И 32. Выход пятого элемента ИЛИ 29 является выходом готовности результатов вычисления функции 15.i.3. Ппервый вход третьего элемента И 32 подключен к выходу RS-триггера фиксации импульса 24, а второй вход третьего элемента И 32 подключен к инверсному выходу T-триггера 23, который также подключен ко входам управления нечетных элементов И с тремя состояниями на выходе дополнительной группы элементов с тремя состояниями на выходе 39, ко входам управления четных элементов которой подключен неинверсный выход T-триггера 23. Информационные входы первого и четвертого элементов И с тремя состояниями на выходе группы 39 являются n-м неинверсным входом X_n парафазных входных переменных 10.i.1 блока. Информационные входы второго и третьего элементов И с тремя состояниями на выходе дополнительной группы элементов И с тремя состояниями на выходе 39 являются n-м инверсным входом

парафазных входных переменных 10.i.1 блока.The outputs of the elements 2 • 2 NOT-AND-OR S-th group,

, where n is the number of input variables, connected to the corresponding odd inputs of elements 2 • 2 NOT-AND-OR S + 1 groups 37.5 + 1, and to each element 2 • 2 NOT-AND-OR l groups

the outputs of two elements of the l-1 group are connected. The output of a single element 2 • 2 NOT-AND-OR 37.n of the last n-th group of n groups of elements 2 • 2 NOT-AND-OR 37.1 ... 37.n is connected to the information input of D-trigger 21. The second input of this the element is connected to the output of the first element OR 25, and the fourth input of this element 2 • 2 NOT-AND-OR of the n-th group 37.n is connected to the output of the second element 26. The first outputs of the first 25 and second 26 elements OR are connected to the outputs of the first 30 and the second 31 elements And, respectively. The second input of the first element OR 25 is connected to the combined outputs of the first and second elements AND with three states at the output of an additional group of elements AND with three states at the output 39. The second input of the second element OR 26 is connected to the combined outputs of the third and fourth elements AND with three states on the output of an additional group of AND elements with three states at the output 39. The second outputs of the first 30 and second 31 And elements, the inputs of the second 34 and fourth 36 inverters are the input of the reconfiguration of the 18.i unit in case of failures, i - nom unit. The first input of the first element And 30 and the input of the first inverter 33 are an input of the type of reconfiguration 19.i block in case of failure. The output of the first inverter 33 is connected to the first input of the second element And 31. The input of zeroing the first D-flip-flop 21 and the first input of the fourth element OR 28 are the input of the reset 13 of the block. The synchronization inputs of the first 21 and second 22 D-flip-flops, the counting input of the T-flip-flop 23, the input of the delay element 38 are the synchronization input 17 of the block. The output of the second inverter is connected to the second input of the fourth element OR 28, the third input of which is the input of the additional reset 40.i block (i is the block number). The output of the fourth element OR 28 is connected to the inputs of the zeroing of the second D-trigger 22, RS-flip latch 24 and T-trigger 23. The output of the first D-trigger 21 is connected to the information input of the second D-trigger 22 and the first input of the third element OR 27, the second input of which is connected to the output of the second D-flip-flop 22. The output of the third element OR 27 is the output of the value of the function 15.i.1 of the block and is connected to the input of the third inverter 35 and the first input of the fifth element OR 29. The output of the third inverter 35 is the output of the inverse value features 15.i.2 b time. The output of the fourth inverter 36 is connected to the second input of the fifth OR element 29, the third input of which is connected to the output of the third AND element 32. The output of the fifth OR element 29 is the readiness output of the calculation of function 15.i.3. The first input of the third AND 32 element is connected to the output of the RS-trigger for fixing the pulse 24, and the second input of the third And 32 element is connected to the inverse output of the T-trigger 23, which is also connected to the control inputs of the odd elements And with three states at the output of an additional group of elements with tri-state output 39, to which the control inputs of the even elements connected non-inverting output of T-flip-flop 23. Information inputs of the first and fourth elements and a tri-state output group 39 are n-m X _n noninverted input na afaznyh input variables 10.i.1 block. The information inputs of the second and third elements And with three states at the output of an additional group of elements And with three states at the output 39 are the nth inverse input

paraphase input variables 10.i.1 block.

The first group of D-flip-flops 1 (Fig. 1) is used to record and store tuning information of the corresponding units for calculating the device functions from the corresponding expansion inputs of m groups of expansion inputs 12.1-12.m along the leading edge of signal "1" at the output of decoder 7.1. Quantity D-flip-flops is m • 2 ⁿ , where n is the number of input variables and m is the number of output variables. D-flip-flops 1 are reset to zero at the input of zeroing 13. The tuning information recorded in D-flip-flops 1 through the elements of the first group of m • 2 ⁿ elements And with three states at the output 6, control the settings inputs 10.1.2-10. m. 2 blocks of function calculation 10.1-10.m and determine the logical (Boolean) function implemented in them. D-flip-flops 1 can be implemented, for example, on integrated circuits 155ТМ2 with additional inverters at the input R.

The second group of D-flip-flops 2 is intended for recording and storing control information at the corresponding inputs of the elements of the first 6 and second 9 groups of m • 2 ⁿ AND elements with three output states to provide the possibility of expanding the bit depth of the calculated logical functions in function calculation blocks 10.1-10. m. The number of D-triggers 2 is m • 2 ⁿ , where n is the number of input variables, m is the number of output variables. D-flip-flops 2 are reset to zero at the input of zeroing 13. Information in D-flip-flops 2 is recorded from the corresponding expansion inputs of m groups of expansion inputs 12.1-12.m along the leading edge of signal "1" at the output 7.2 of decoder 7. Tuning signals recorded in D- triggers 2, control AND elements with three states at the output of groups 6, 9 in such a way that if "1" is written in the D-trigger of group 2, then the configuration information from the output of the corresponding D-trigger of group 1 is connected to the corresponding input of the function calculation unit otherwise connects accordingly there is a corresponding category of expansion inputs of the corresponding of the m groups of expansion inputs 12.1-12.m. Thus, it is possible to connect to any category of inputs of the settings 10.1.2-10.m.2 blocks of the calculation of functions 10.1 ... 10.m or a constant from the D-triggers of group 1, or an additional variable from the expansion inputs, or the outputs of other calculation blocks functions from blocks 10.1. ..10.m, or another programmable logic device to ensure the expansion of the capacity of the calculated logical functions, for example, in accordance with / Korneychuk V.I., Tarasenko V.P. Computing devices on microcircuits: Reference. - Kiev: Technique, 1988 .-- S. 34-36 /.

 D-flip-flops of the second group of D-flip-flops 2 can also be implemented on type 155ТМ2 microcircuits with additional inverters at input 12.

 The third group of D-flip-flops 3, containing 2m (n-1) triggers, is designed to record and store from a portion (from 2 (n-1) bits) of the corresponding expansion inputs of m groups of expansion inputs 12.1-12.m along the leading edge of the signal at the output 7.3 of the decoder 7 information sets significant variables (all but the last "senior") that controls the groups m (n-1) elements AND 4, m (n-1) elements OR 8.

разрядов входов парафазных входных переменных 10.1.1-10.m. 1 блоков вычисления функций 10.1-10.m с помощью элементов И 4 (на их входах) обнуляются, а разряды

с помощью элементов ИЛИ 8 устанавливаются в "1". D-триггеры 3 обнуляются по входу сброса 13 и также могут быть реализованы на микросхемах 155ТМ2 с дополнительными инверторами по входу R.If the variable is not significant, then the corresponding digits X _i , from 2 (n-1),

discharges of inputs of paraphase input variables 10.1.1-10.m. 1 blocks of function calculation 10.1-10.m with the help of AND 4 elements (at their inputs) are reset, and the digits

using elements OR 8 are set to "1". D-flip-flops 3 are reset at the reset input 13 and can also be implemented on 155TM2 microcircuits with additional inverters at the input R.

, входов парафазных входных переменных соответствующего блока вычисления функций 10.i обнуляется с помощью соответствующих элементов И группы 2n•m элементов И 4. Старшая переменная всегда должна быть существенна. Таким образом, сигнал "1" на выходе соответствующего нечетного D-триггера группы 3 через соответствующий i-й элемент И группы 4 обеспечивает существенность этой переменной X_i, т.е. они принимаются с соответствующего разряда входов 11, а сигнал "0" на выходе соответствующего D-триггера группы 3 обеспечивает несущественность этой переменной, т.е. на соответствующий вход переменных j-го блока вычисления функций подается "0".The group of m (n-1) elements And 4 is intended for connecting input non-inverse variables from the inputs of paraphase input variables 11 to groups of variable inputs corresponding to m function calculation blocks 10.1-10.m. With the insignificance of some input non-inverse variables, except for the last "senior", the corresponding digits X _i ,

, the inputs of the paraphase input variables of the corresponding function calculation block 10.i are reset to zero using the corresponding elements AND of the group 2n • m elements AND 4. The highest variable should always be significant. Thus, the signal "1" at the output of the corresponding odd D-flip-flop of group 3 through the corresponding i-th element And of group 4 ensures the significance of this variable X _i , i.e. they are received from the corresponding discharge of inputs 11, and the signal "0" at the output of the corresponding D-trigger of group 3 ensures the insignificance of this variable, i.e. the corresponding input of the variables of the jth block of function calculation is fed with "0".

 The counter 5 is designed to control the decoder 7 in programming mode. Previously, the counter 5 is reset to zero at the reset input 13. The counter 5 receives pulses from the programming input 14.

 The counter 5 can be implemented, for example, on an integrated circuit 155IE2.

The first group of m • 2 ⁿ AND elements with three states at the output 6 is intended for connection to the tuning inputs of the function calculation blocks 10.1 ... 10. m tuning information from the outputs of the D-flip-flops of the first group 1, in the event that the non-inverse outputs of the D-flip-flops of the second group 2 are activated.

The first group of m • 2 ⁿ AND elements with three states at output 6 can be implemented, for example, on integrated circuits 589AP16.

 The decoder 7 is designed to control the synchronization inputs of the D-flip-flops of the groups of D-flip-flops 1, 2, 3 according to the information from the counter 5. According to the first programming pulse, the output of the counter 5 sets information leading to the setting of “1” at the output 7.1 of the decoder 7, according to the second - at the exit 7.2, on the third - at the exit 7.3. In this case, the information is recorded in the D-triggers of groups 1, 2, 3, respectively. The fourth programming pulse sets "1" at the output 7.4 of the decoder 7, which leads to the excitation of the output of the end of programming 16.

 The decoder 7 can be implemented, for example, on an integrated microcircuit 155ID3, and its control inputs must be connected to "0" V.

 The group of m (n-1) elements OR 8 is designed to connect the input inverse variables from the inputs of 11 paraphase input variables to the groups of variable inputs 10.1.1. . .10.m.1 of the corresponding of m blocks of function calculation 10.1-10.m.

входов парафазных входных переменных соответствующего блока вычисления функций 10.i сигналом "1" с выхода соответствующего четного D-триггера группы 3 через соответствующий элемент группы элементов ИЛИ 8 устанавливается в состояние "1", обеспечивая несущественность i-й переменной для данного j-го блока вычисления функций 10. j, причем одновременно с помощью соответствующего четного D-триггера группы 3 и соответствующего элемента И группы 4 обнулятся и разряд X_i, обеспечивая несущественность этой переменной. Таким образом, для несущественной переменной X_i = 0,

. "Старшая" переменная всегда существенна и разряды X_n,

непосредственно поступают на входы переменных блоков 10.1...10.m.If some input inverse variables are insignificant, except for the last "senior" one, the corresponding digits

the inputs of the paraphase input variables of the corresponding block of function calculation 10.i by the signal "1" from the output of the corresponding even D-trigger of group 3 through the corresponding element of the group of elements OR 8 is set to state "1", ensuring the insignificance of the i-th variable for this j-th block computing functions 10. j, and at the same time using the corresponding even D-trigger of group 3 and the corresponding element And of group 4, the digit X _i will also be zeroed, ensuring the non-essentialness of this variable. Thus, for the non-essential variable X _i = 0,

. The "senior" variable is always significant and the digits X _n ,

directly go to the inputs of variable blocks 10.1 ... 10.m.

The second group of m • 2 ⁿ AND 9 elements with three output states is designed to connect to the tuning inputs 10.1.2 ... 10.m.2 of the corresponding function calculation blocks 10.1 ... 10.m of the corresponding expansion inputs of the corresponding group of m groups 12.1-12.m if the inverted outputs of the D-flip-flops of group 2 are activated. The second group of m • 2 ⁿ AND elements with three states at the output can be implemented, for example, on integrated circuits 589PA16.

 m function calculation blocks 10.1-10.m are designed to calculate the logical functions defined by the configuration information on the training inputs of the i-th block 10. i.1, and the number of significant variables is determined by the inputs of the variables 10.i.2. The calculations are made according to the synchronization pulses received at the corresponding input of 17 blocks 10.

 Calculations can be carried out in the normal mode, when the input of reconfiguration 18.i of block 10.i is reset, or in the calculation mode if there are failures, when “1” is set at the input of reconfiguration 18.i, and at the input of the reconfiguration type of i-th block 10. i set the type of reconfiguration. In the absence of failures detected by testing using technical means external to the device, the readiness output 15.i.3 of block 10.i always sets “1” and the readiness of the calculation results at the output of the value of function 15. i.1 and the inverse value 15.i.2 functions, the result can be used at the end of the action of the synchronization pulse at input 17, taking into account the need to wait for the completion of transients by technical means external to the device.

 If there are failures in block 10.i, the readiness of the results is determined by setting signal “1” at the output 15.i.3.

 The internal structure of function calculation blocks 10.1-10.m will be described below.

 Group 2 • n • m inputs of paraphase input variables 11 is intended for receiving values of paraphase input variables, logical functions of n arguments of which are calculated in blocks of calculation of functions 10.1-10.m, each of which receives n bits of the group. The values of the paraphase input variables are fixed for the duration of the calculations by technical means external to the device, for example, the register, to exclude signal contests during the calculations. The receipt of the pulse at the synchronization input 17 is organized by external technical means only after the completion of transient fixation of paraphase input variables in external technical means.

m groups of extension inputs 12.1-12.m, each of which contains 2 ⁿ bits, is designed to increase the bit depth of the calculated logical functions by connecting to the tuning inputs of the blocks for computing functions of additional variables or outputs of similar blocks of this or another similar programmable logic device in calculation modes . In the programming mode, the programming inputs of the D-flip-flops of groups 1, 2, 3 are fed sequentially to the expansion inputs using external hardware.

 The reset input 13 is designed to receive a zeroing pulse of a device for zeroing D-triggers of groups 1, 2, 3, counter 5 and function calculation blocks 10.1-10.m.

 The programming input 14 is designed to receive programming pulses that control the counter 5.

 The group m of outputs of the values of the functions 15.1.1-15.m.1 is intended for the output of the values of the logical functions calculated in the blocks for calculating the functions 10.1-10.m.

 The group m of outputs of the inverse values of the functions 15.1.2-15.m.2 is intended for the output of the inverse values of the logical functions calculated in the blocks for calculating the functions 10.1-10.m.

 Group m of readiness outputs 15.1.3-15. m. 3 is intended for issuing to external technical means signals of readiness of calculation results in function calculation blocks 10.1-10.m.

 The output of the programming end 16 is designed to issue a signal to complete the programming from the output 7.4 of the decoder 7, by which it is allowed to start the calculation.

 The synchronization input 17 is designed to receive synchronization signals from external hardware after programming and writing, for example, in an external register of paraphase input variables.

 The group of m inputs for reconfiguring the function calculation blocks for failures 18.1-18.m is intended for receiving signals from the device external to the device for reconfiguration, which is clarified by external technical means as a result of testing the device.

 The group of m inputs of the type of reconfiguration of the blocks for calculating the functions for failures 19.1-19.m is intended for receiving signals from the external technical means such as the reconfiguration of the blocks for calculating the functions, which is revealed by testing the device.

 After programming the device with diagnostic information, calculations are performed (at inputs 18, 19, "0" is set). If the calculation results do not correspond to the standard, then at the input 18.i of the corresponding abnormal block 10.i is set to "1". Then, calculations and comparison with the standard are again performed (all this is done by technical means external to the device). If the result is again abnormal, then at the input 19.i is set to "1" by external technical means. If, after the next test, the function calculation blocks 10.i are received abnormally, then external technical means make a conclusion about the failure unsolved by the reconfiguration, and the required calculations are performed by the remaining function calculation blocks by reprogramming.

A group of 4 • 2 ⁿ AND elements with three states at the output 20 (Fig. 2) of function calculation blocks 10. i is designed to connect to the odd inputs of 2 • 2 NOT-AND-OR configuration information from the tuning inputs 10.i.2, moreover, even elements AND groups 20 connect the initial tuning information when their control inputs are activated by the inverse output of the zeroed T-trigger 23, and odd elements AND groups 20 connect the "rearranged" tuning information when the first and second half of the information from inputs 10.i.2 swaps.

 This is necessary to implement calculations in reconfiguration mode in case of failures. Therefore, the corresponding training information of the second half of the tuning inputs 10.i.2 is connected to the data inputs of the first half of the odd AND elements with output 20 and the corresponding training information of the first half of the tuning inputs 10 is connected to the data inputs of the second half of the odd elements And group 20. i.2.

Thus, the configuration information 10.i.2.1-10.i.2.2 ^n-1 and the information 10.i.2.2 ^n-1 +1 ... 10.i.2.2 ^{n are} interchanged.

 The And elements with three states at the output of group 20 are controlled by the inverse and non-inverse outputs of the T-flip-flop 23, even — inverse, odd — non-inverse. Elements And with three states at the output 20 can be, for example, implemented on the 589AP16 chips.

 The first D-trigger 21 is designed to receive the signal value from the last of n groups of elements 2 • 2 NOT-AND-OR, containing one element 37.n by the synchronization pulse from input 17. The first D-trigger 21 is reset to zero by the signal from the reset input 13.

 The value of the function is recorded in the first D-flip-flop 21 in the calculation mode in the absence of failures, which is then issued through the OR element 27 at the output of the values of the functions 15.i.1, 15.i.2. In the calculation mode, if there are failures, the value of the first subfunction is recorded in the first D-trigger 21 according to the first synchronization pulse, and the value of the second subfunction according to the second pulse. The first D-flip-flop 21 can be implemented, for example, on 155TM2 chips with an inverter at input R.

 The second D-flip-flop 22 is designed to receive a signal from the output of the first D-flip-flop 21 by the synchronization pulse supplied to the synchronization input 17. The second D-flip-flop 22 is reset by the reset pulse, which is fed to the reset input 13 via the OR element 28, or by the additional reset pulse input 40, arriving in the calculation mode in the presence of failures.

 In the calculation mode, in the absence of failures, the input 18.i receives "0", therefore, the signal through the OR element 28 coming from the output of the inverter 34, the second D-trigger 22 is held in the state "0" regardless of the synchronization signals.

 In the calculation mode, if there are failures on the first synchronization pulse, the signal from the output of the first D-trigger 21 is recorded in the second D-trigger 22, that is, its initial state is “0”. According to the second synchronization pulse, the value of the first subfunction is recorded in the second D-flip-flop 22. After that, the second D-flip-flop 22 is zeroed through the OR element 28 at the input of the additional reset 40. The second D-flip-flop 22 can be implemented, for example, on 155ТМ2 microcircuits with an inverter at the input R.

The T-trigger 23 is designed to control a group of 4 • 2 ⁿ AND elements with three states at the output 20, and even elements of the And 20 group are connected by the inverse output of the T-trigger 23 when the T-trigger 23 is zeroed, and the odd elements of the group 20 are connected by a non-inverse output T-trigger 23, i.e. when it is set to state "1", and the state of the T-flip-flop 23 is changed along the trailing edge of the synchronization pulse and signal racing does not occur during switching, since the values of the function (sub-function) are recorded in the D-flip-flops 21, 22 on the leading edge of the signal synchronization.

 In addition, the T-flip-flop 23 controls an additional group of AND elements with three states at the output 39 similarly to the above, controlling their even and odd elements to “cross” the last, highest variable in the calculations in case of failures. When the T-trigger 23 is zeroed, the odd elements of the additional group of AND elements with three states at the output 39 are connected, and with the T-trigger 23 installed, the even elements of the additional group of AND elements with three states at the output 39 are connected, providing the change of variables of the first and second half of element 2 • 2 NON-AND-OR 37.n.

 The T-trigger 23 controls the element And 32 to generate a signal of readiness of the results of the calculations in the calculation in the conditions of failure.

 T-trigger 23 can be implemented, for example, on an integrated circuit 155TV1 with an inverter at the reset input.

 The RS-trigger pulse fixation 24 is designed to control elements And 32 in order to generate a signal of readiness in the calculations in the event of a failure.

 The RS-trigger for fixing the pulse 24 is reset to zero by the signal from the output of the OR element 28, and is set by the signal from the output of the delay element 38 to the first synchronization pulse, the delay being such that the T-trigger 23 manages to settle at the trailing edge of the first pulse and its inverse output is zeroed, and After that, the RS-flip-flop 24 is installed. Thus, the signal "1" at the output of the And 32 element is generated after every second clock pulse, however this signal is used only in the calculation mode in the presence of failures.

 The RS-trigger for fixing the pulse 24 can be implemented, for example, on 155TM2 microcircuits with inverters at the inputs R, S.

. Во втором случае - логическая единица для отключения верхней половины элемента 37.n.The first OR element 25 is designed to connect to the second input of the element 37.n either a signal from the combined inputs of the first and second AND elements with three states at the output of group 39 or a signal from the output of the And 30 element in order to provide calculation modes in the presence of failures. In the first case, the oldest variable X _n or its inversion is connected

. In the second case, a logical unit to disable the upper half of element 37.n.

или саму переменную X_n, поступающую с объединенных выходов третьего и четвертого элементов И с тремя состояниями на выходе дополнительной группы 39. В случае возбуждения выхода элемента И 31 на выходе второго элемента ИЛИ 26 устанавливается сигнал "1" и нижняя половина элемента 37. n отключается. Все это также обеспечивает реализацию режима вычислений при наличии отказов.The second element OR 26 is designed to control the fourth input element 37.n similarly to the element OR 25. The second element OR 26 connects the inverse of the oldest variable

or the variable X _{n itself} , which comes from the combined outputs of the third and fourth AND elements with three states at the output of an additional group 39. In the case of excitation of the output of the And 31 element, the signal “1” is set at the output of the second OR element 26 and the lower half of the element 37. n is turned off . All this also provides the implementation of the calculation mode in the presence of failures.

 The third element OR 27 is designed to generate a signal of the function value by the signals at the outputs of the first 21 and second 22 D-flip-flops. In calculations in the absence of failures, the output of the second D-flip-flop 22 is always zeroed, therefore the function value is determined by the signal value at the output of the first D-flip-flop 21 after the clock pulse arrives at it.

 During calculations in the presence of failures, the value of the function is determined by the disjunction of the signals from the outputs of the first 21 and second 22 D-flip-flops after the second sync pulse arrives.

 The fourth element OR 28 is designed to generate a reset signal of the second D-trigger 22, RS-trigger fixation of the pulse 24, T-trigger 23, if a reset signal is received at the reset input 13, at the input of the additional reset 40, or if there is a logical unit signal at the output of the second inverter 34.

 The fifth OR element 29 is designed to generate a ready signal for the ready output 15.i.3 if the output of the And 32 element is activated, i.e., after the end of the second synchronization pulse in the calculation mode in the presence of failures, if the output of the OR element is activated 27, i.e. if it turns out that the logical function is equal to unity already in the calculations of the first subfunction, finally, if the output of the inverter 36 is activated, i.e. in the case of calculations in the absence of failures.

 The first AND 30 element is designed to generate a trip signal for the upper half of the 2 • 2 NOT-AND-OR element 37.n (“logical 1”) in the calculation mode in the presence of failures if input 18.i and input 19.i are activated.

 The second element And 31 is designed to generate a trip signal for the lower half of the element 2 • 2 NOT-AND-OR 37.n ("logical 1") in the calculation mode in the presence of failures if input 18.i is activated and input 19.i is inactive (activated inverter output 33).

 The third element And 32 is designed to generate a signal of readiness of the calculation results in the calculation mode in the presence of failures, if the RS-trigger 24 is installed and the T-trigger 23 is reset, i.e. after every second sync pulse.

 The first inverter 33 is designed to control the And 31 element in order to turn off the lower half of the 2 • 2 NOT-AND-OR 37.n signal with the signal “1”, if the input 19.i of the reconfiguration type in case of failure is inactive.

 The second inverter 34 is designed to generate a constant reset signal of the D-flip-flop 22 through the OR element 28, the RS-flip-flop 24 and the T-flip-flop 23 in the absence of failures, i.e. when input 18.i of reconfiguration of the unit for calculating functions in case of failures is inactive (at this input is "0").

 The third inverter 35 is designed to generate an inverse value of the calculated logical function to the corresponding output 15.i.2.

 The fourth inverter 36 is designed to generate a ready signal through the OR element 29 if the input 18.i of the reconfiguration of the function calculation unit in case of failures is inactive, i.e. in the absence of failures.

 n groups of elements 2 • 2NE-AND-OR 37.1-37.n are designed to calculate logical functions in accordance with the tuning signals at the inputs 10.i.2 for n input signals at the inputs 10.i.1.

The first group contains 2 ⁿ elements, the last one element, i.e. each i-th group contains 2 ⁿⁱ elements, i = 1, n and there is a "pyramidal" connection of elements.

особенностью которой является то, что она сама и все ее модификации, полученные при однократной подстановке констант 0,1 или однократного инверсирования переменных, обладают функциональной полнотой.Elements 37 realize the function of S. Tyurin

the feature of which is that she herself and all her modifications obtained by a single substitution of the constants 0.1 or a single inversion of the variables have functional completeness.

 Therefore, a single failure of the inputs of even the last element in the "pyramid" does not lead to the establishment of a constant at its output, which provides the possibility of calculations in two clock cycles on half the elements.

 The delay element 38 is designed to delay the installation of the RS-flip-flop 24 at the input S for the time of zeroing the inverse output of the T-flip-flop 23 after the influence of the trailing edge of the synchronization pulse to prevent false readiness during calculations in case of failures.

 An additional group of AND elements with high impedance at the output 39 is designed to connect to even inputs of the last group of n groups of elements 2 • 2 NOT-AND-OR 37.1-37.n, containing one element 37.n of either "own" variable or variable from another even input according to the control signals from the T-flip-flop 23, which is necessary for the implementation of the calculation mode in the presence of failures. Thus, a kind of “crossing of variables” occurs, that is, together with the replacement of the constants at the inputs of the elements of the first group 37.1, the senior variable is replaced, providing the calculation of the logical function by subfunctions on half of the elements 37.

 An additional reset input 40 is designed to receive an additional reset signal from external hardware in the calculation mode if there are failures to reset the D-flip-flops 21, 22 after performing the calculations (after two synchronization pulses have arrived) to prevent the generation of a false ready signal through the OR elements 27, 29 when shifting from D-flip-flop 21 to D-flip-flop 22 in a new calculation cycle.

 A programmable logic device operates in the following modes: 1) programming (or recording); 2) calculations in the absence of failures; 3) calculations in the presence of failures.

 In programming (or recording) mode, the device operates as follows. In the initial state, the D-flip-flops of the first 1, second 2 and 3 groups, counter 5 are reset to zero at the device input 13, the “0” signals are sent to the control inputs of the first group of elements And with three states, and their output is in a high-impedance state, at the control inputs of the second group of elements And with three states at the output 7, the signals "1" are given and at their output information is transmitted from the corresponding bits of the corresponding group of expansion inputs (Fig. 1).

 According to the first pulse received at the programming input 14 of the device, the counter 5 goes into the first state and the signal "1" appears at the output 7.1 of the decoder 7. According to this signal, programming information previously supplied to the corresponding of the m groups of extension inputs 12.1-12. m is also written using the technical means external to the device and written to the D-triggers of group 1.

 The information in the D-flip-flops is entered from their inputs D along the leading edge of the signal coming from the output of decoder 7.1. After that, using the technical means external to the device, the programming information of the second group is supplied to the corresponding of the m groups of expansion inputs 12.1-12.m D-flip-flops 2, in which it is recorded by the second programming pulse supplied to the input 14 of the device, along the leading edge of the signal "1" that occurs at the output 7.2 of the decoder 7.

 According to the third programming pulse, the output 7.3 of the decoder 7 and the information from 2 (n-1) inputs in each of the m groups of extension inputs 12.1-12 are activated. m, previously filed with external technical means to indicate the bit depth of the calculated logical functions in m blocks of the calculation of logical functions 10.1-10. m, is written by D inputs to the corresponding D-triggers of the third group. The outputs of D-triggers of group 3 control the connection of input variables through groups of m (n-1) elements AND 4, m (n-1) elements OR 8. According to the fourth programming pulse at the output of decoder 7.4, "1" is set; and at the output 16 of the end of programming, a signal "1" appears, indicating the completion of the programming mode. In the next programming cycle, if necessary, a preliminary zeroing of the device is carried out at the input of zeroing 13, as a result of which counter 5 will be reset to zero, the initial state and "0" will appear at the output 16.

In D-triggers of group 1, in programming mode, m • 2 ⁿ tuning constants of m function calculation blocks are written 10, in D-triggers of group 2 are written m • 2 ⁿ control signals And with three states at the output of group 6, 7 for connecting to configuration inputs 10.i.2-10.m.2 m function calculation blocks 10.1-10.m or constants from the outputs of individual or all D-flip-flops 1 of group 1, or individual or all bits of m groups of extension inputs 12.1-12.m .

 The control signals of groups m (n-1) elements AND 4 (odd D-flip-flops), m (n-1) elements OR 8 (even D-flip-flops) are written to the D-triggers 3 of group 3 in programming mode in order to indicate the bit depth of the input variables (with the exception of the oldest one) at the corresponding inputs of the 10.i.1-10.m.1 m variables of function calculation blocks 10.1-10.m. In case of non-use (non-materiality) of some (except the oldest) input variables in a particular i-th block 10.i using the information recorded in the corresponding D-triggers of group 3, the outputs of the corresponding elements AND of group 4 are reset to zero and the outputs of the corresponding elements OR group 8, which leads to the "imposition" of the corresponding constants on the paraphase inputs of the variables 10.i.1-10.m.1.

 In the calculation mode, in the absence of failures (the absence of failures is established in the process of some reference calculations) at the inputs of reconfiguration 18.1-18.m of the blocks for calculating functions 10.1-10.m using the technical means external to the device, the signal "0" is set, and at the inputs of the reconfiguration type 19.1-19.m, function calculation blocks 10.1-10.m, the information in this case can be any.

 The function calculation blocks 10.1-10.m calculate the values of logical functions without extension specified by the information at the outputs of the corresponding D-flip-flops 1 of group 1, while the corresponding D-flip-flops 2 of the group of D-flip-flops 2 are in state “1” and the outputs of the corresponding D- triggers 1 group 1 through the corresponding elements And with three states at the output of the first group 6 are supplied to the settings 10.i.2 inputs of the corresponding function calculation unit 10.i. The calculations are made according to the clock signal supplied to the input 17 of the device, and at the ready outputs 15.1.3-15.m.3 upon completion of the calculation, the signal “1” appears in the function calculation blocks, and the function values 15.1.1-15 on the groups of m outputs . m. 1 and on groups of m outputs of inverse values of functions 15.1.2-15. m. 2, respectively, the value of the corresponding functions and their inversions appear. It is assumed that in order to eliminate the competition of the input signals at the inputs 11, they are fixed for the duration of the calculations by means external to the device.

 The device assumes the possibility of expanding the bit depth of the calculated functions (> n) when connecting the outputs 15.i.1, 15.i.2 of individual or several blocks 10.1-10.m for individual or all expansion inputs in groups 12.1-12. m, in addition, it is possible to connect individual variables from the input m • n variables 11 to these inputs, finally, it is possible to connect the outputs 15.i.1, 15.i.2 of other similar devices to the individual inputs of the paraphase variables 11, and it is also possible to connect outputs 15.i.1, 15.i.2 of other similar devices to the extension inputs 12.1-12.m of this device.

 When calculating logical functions with expansion, the device works similarly to calculations without expansion, except that the signal of general availability must be generated using elements I that are external to the device (s).

 The expansion of the capacity of the calculated logical functions can be carried out, for example, using the methods described in the book / Korneychuk V.I., Tarasenko V.P. Computing devices on microcircuits: Reference. - Kiev: Tehnika, 1988 .-- S. 34-36 /.

 In the calculation mode in the absence of failures, the function calculation blocks work as follows (Fig. 2, 3).

 In the initial state, the first 21 and second 22 D-flip-flops, T-flip-flop 23, RS-flip-flop 24 are reset at the reset input by the function calculation blocks with the signal from the reset input 13.

, соответствующие первой переменной из n входных переменных данного i-го блока 10.i, поданных на входы 10. i. 1 в парафазном коде (x₁ - на вторые входы,

- на четвертые входы элементов 37.1). Аналогично на четные входы элементов других групп 37.j, где j = 2, n-1 поступают переменные x_j,

со входов 10.i.1. Группа 37.n из n групп 37.1-37. n элементов 2•2 НЕ-И-ИЛИ содержит один элемент, на второй и четвертый входы которого при отсутствии отказов поступают соответственно переменные x_n,

со входов 10.i.1, через дополнительную группу элементов И с высоким импедансом на выходе 39, нечетные элементы которой по входам управления подключены инверсным выходом T-триггера 23, а четные имеют на выходах высокий импеданс, так как их входы управления обнулены неинверсным выходом T-триггера 23, так как выходы элементов И 30, 31 обнулены вследствие наличия "0" на входе реконфигурации при отказе 18.i, в связи с этим же на выходе элемента ИЛИ 29 и на выходах 15.i.3 устройства установлен сигнал "1" готовности (сигнал отсутствия отказа со входа 18.i инвертируется в элементе 36 и поступает на второй вход элемента ИЛИ 29).At the inputs of the variables 10.i.1 of the function calculation block 10.i, the values of the paraphase input variables are set; at the settings inputs 10.i.2 - settings information. Since the T-trigger 23 is zeroed, its inverse output activates the control inputs of the control inputs of the odd elements And group 4 • 2 ⁿ elements And with three states at the output 20, and the non-inverse output of the T-trigger 23 generates a signal "0" to the control inputs of even elements from the group of 4 • 2 ⁿ AND elements with three states at the output 20 and their outputs are in a high impedance state. As a result, the odd inputs of 2 • 2 NOT-AND-OR elements from group 37.1 (2 ^n-1 first-level elements) are connected with the corresponding bits from 2 ⁿ bits of the settings 10.i.2 inputs, which configure the function calculation unit for the required logical function, the even inputs of the elements 37.1 receive two bits x ₁ ,

corresponding to the first variable of n input variables of this i-th block 10.i applied to inputs 10. i. 1 in the paraphase code (x ₁ - to the second inputs,

- to the fourth inputs of the elements 37.1). Similarly, to the even inputs of the elements of other groups 37.j, where j = 2, n-1, the variables x _j ,

from the inputs 10.i.1. Group 37.n of n groups 37.1-37. n elements 2 • 2 NOT-AND-OR contains one element, the second and fourth inputs of which, in the absence of failures, respectively receive the variables x _n ,

from the inputs 10.i.1, through an additional group of AND elements with a high impedance at the output 39, the odd elements of which are connected to the inverse output of the T-flip 23 at the control inputs, and the even ones have a high impedance at the outputs, since their control inputs are zeroed by the non-inverse output T-flip-flop 23, since the outputs of the elements AND 30, 31 are reset due to the presence of "0" at the input of the reconfiguration in case of a failure 18.i, in connection with this, the signal is set at the output of the element OR 29 and at the outputs 15.i.3 of the device " 1 "ready (no failure signal from input 18.i is inverted I'm in element 36 and goes to the second input of the element OR 29).

 When calculating logical functions in the absence of failures, which is determined by preliminary testing (comparing the results of calculations with the reference ones during the process of performing the described calculations), the value of the calculated function is recorded from the input 17 to the first trigger 21, which is transmitted via the OR element 27 to the second input which receives "0" from the second trigger 22, reset in turn by the output of the OR element 28, to which "1" is supplied from the output of the inverter 34 connected to input 18. i reconfiguration upon opening Zech. The signal "1" from the output of the element 29, the triggers 24, 23 is held at zero and the output signals of the T-trigger 23 are not changed and do not affect the calculation process in the group of elements 37.

 The calculations consist in transferring from one of the odd inputs of the elements of the first level 37.1 to the output of the element of the last level 37.n constants from the corresponding category of inputs 10.i.2, determined by the information at 2n inputs 10.i.1. The value of the logical function from the output of the trigger 21 is transmitted through the OR element 27 to the output of the values of the function 15.i.1, and the inverse value of the calculated logical function through the inverter 35 to the output of the inverse value of the function 15.i.2.

 Similarly, calculations are performed in other blocks of calculation of functions from group 10.1-10. m. If necessary, the calculation of other logical functions is reprogrammed.

 If it is necessary to increase the bit depth of the calculated functions, cascading is performed, as already described above.

 Calculations in the presence of failures (Fig. 2, 3).

 If during testing it was found that the calculated values differ from the reference values for a specific block 10.i from blocks 10.1-10.m, then using external technical means, a logical unit indicating a failure is supplied to the input of reconfigurations 18.i (Fig. 1) in block 10.i. At the same time, a “0” is set at the input of the reconfiguration type using technical means external to the device.

 Therefore (Fig. 2), the signal "1" from the input 18.i through the inverters 34, 36, the second inputs of the OR elements 28, 29 are reset to zero, the trigger 22 is ready to participate in the calculations; the signal "0" from input 19.i through the inverter 33 at the first input activates the output of the element And 31, the second input of which is activated by the signal "1" from the input 18.i, therefore, the logical unit from the output of the element And 31, passing through the element OR 26, disables at the fourth input the lower half of the elements of n groups of elements 37.1-37.n. The calculations are made in two steps. First, a subfunction is calculated, which is determined by the setting from the inputs 6.i supplied to the odd inputs of the elements 2 • 2 NOT-AND-OR of the upper half of the elements 37.1-37.n. Previously, before calculations in case of failure, an additional reset signal is sent to the corresponding input 40. Then, synchronization signals are received at the synchronization input 17. With a delay determined by the delay element 38 by the first synchronization pulse, the trigger 24 is set, preparing the AND 32 element for operation, the second input which has already been reset by the steady T-flip-flops 23 (the delay in the delay element 38 prevents the formation of a ready signal during the installation of the T-flip-flop 23). The second input of the OR element 29 is now reset to zero by the signal from the output of the inverter 36, which receives the signal from the input of the reconfiguration 18.i.

 According to the first synchronization pulse, the value of the first subfunction is recorded in the trigger 21 in the same way as described above, and if it is equal to one, then through the OR element 27 it is output 15.i.1 (through the inverter 35 - to the output 15. i.2) and through the element OR 29 a ready signal is issued to the output 15.i. 3. It is perceived by equipment external to the device, which prohibits the arrival of the next (second) synchronization pulse, remembering the results of the calculations.

посредством возбуждения входов управления четных элементов дополнительной группы элементов И с тремя состояниями на выходе 39.If the result of calculations on the first clock pulse is "0", then the second clock cycle is performed. In that case, the T-trigger 23 by the trailing edge of the first synchronization pulse with its outputs (inverse and non-inverse) already connected to the odd inputs of the upper half of the elements 2 • 2 NOT-AND-OR of group 37.1 of the tuning inputs of the lower half of the elements of group 37.1. In addition, the outputs of the T-flip-flop 23 provide the "crossing" of the "senior" variables X _n ,

by driving the control inputs of the even elements of an additional group of AND elements with three states at the output 39.

 Before the second clock cycle in the second D-flip-flop 22, “0” is written, because the first clock pulse at its input D had the output signal of the first flip-flop 21, previously zeroed. Before the second clock cycle, the T-flip-flop 23 is set to the state “1”, therefore its inverse output is zeroed, which leads to the zeroing of the output of the AND 32 element and the output of the OR 29 element, i.e. in case of inequality "1" of the first subfunction, the ready signal is not generated at output 20.i.

 By the second synchronization pulse, the T-flip-flop 23 is reset, its inverse output is activated, and since the RS-flip-flop 24 is set by the first synchronization impulse, the signal of readiness of the calculation result in block 10 is output through the And 32 element or the OR 29 element 15.i.3 .i.

.In the second clock cycle, in the second trigger 22 at its input D, the signal is output at the output of the first D-trigger 21 (the result of the calculations of the first subfunction), and in the first D-trigger 21, the result of the calculations of the second subfunction determined by the upper half of the elements of group 37.1 by the tuning inputs the lower half of the elements of group 37.2, connected by a T-trigger 32 through even elements AND with three states at the output of group 20. It should be noted that the D-triggers 21, 22 are triggered by the leading edge of the pulse, and the T-trigger 23 by the back, therefore the result of the calculations is written to the trigger 21 before the outputs of the T-trigger 23 switch the configuration information 10.i.2 and “cross” the “senior” variables X _n ,

.

 After the second clock cycle of the calculations, outputs 15.i.1 through the OR element 27 receive the value of the function, and through the inverter 35 the inverse value of the calculated function goes to the corresponding output 15.i.2.

 If abnormality is obtained according to the test results by comparison with technical means external to the device using the described calculations on the "upper" half of elements 37.1 ... 37.n-1, then calculations are performed using the "lower" half of elements 37.1. ..37.n-1.

с соответствующих n разрядов входов 10.i.1 через третий элемент И с высоким импедансом на выходе 39 из дополнительной группы элементов И с высоким импедансом на выходе 39. Нижняя половина элементов 37.1-37. n-1 аналогично вышеописанному настраивается вначале "собственными" константами настройки через четные элементы 20, так как они в исходном состоянии подключены по управляющим входам инверсным выходом T-триггера 23, затем аналогично вышеописанному, после второго импульса нижняя половина элементов 37.1-37. n-1 настраивается константами "верхней" половины элементов, так как T-триггер 23 своим неинверсным выходом, на котором установлена теперь "1", подключает нечетные элементы 20, при этом выходы четных элементов 20 находятся в состоянии высокого импеданса и не влияют на передачу информации через нечетные элементы 20.In this case, the device operates similarly to the above, except that in this case, the signal of the reconfiguration type 19.i is “1” and the signal “1” is generated through the AND 30 element to the OR element 25 and the second input of the element 37. n, disconnecting its upper half. The inverter 33 provides a "0" to the AND element 31, therefore, through the OR element 26 to the fourth input of the element 37. n a variable is supplied

from the corresponding n bits of the inputs 10.i.1 through the third AND element with a high impedance at the output 39 from an additional group of AND elements with a high impedance at the output 39. The lower half of the elements 37.1-37. n-1, similarly to the above, is initially set up by the "own" tuning constants via even elements 20, since they are initially connected to the control inputs by the inverse output of the T-trigger 23, then, similarly to the above, after the second pulse, the lower half of the elements 37.1-37. n-1 is set by the constants of the "upper" half of the elements, since the T-trigger 23 connects the odd elements 20 with its non-inverse output, which is now set to "1", while the outputs of the even elements 20 are in a high impedance state and do not affect the transmission information through odd elements 20.

, x_n на четвертом входе элемента 37.n через обнуленный по первому входу элемент ИЛИ 26.In addition, using the fourth element 39 of an additional group of AND elements with three states at the output 39, the "crossing" of variables

, x _n at the fourth input of element 37.n through the element OR zeroed to zero at the first input.

 Thus, the calculations are performed in two steps on the "lower" half of the elements 37.

 If, according to the results of testing using external technical means, a norm is not obtained in any of three cases: 1) during calculations using all elements 37; 2) in calculations using the "upper" half of the elements 37; 3) during calculations using the "lower" half of the elements 37, then a conclusion is made about the complete failure of the function calculation unit and external technical means are forced to perform the required calculations on the remaining function calculation units using the reprogramming mode, i.e. some function calculation blocks will be used for time-divided calculation of various functions. Consequently, a monotonous, rather than catastrophic, reduction in the time for calculating functions in a programmable logic device when failures occur is ensured.

 Calculations in the presence of failures with an extension of the capacity of the calculated functions are performed using technical means external to the device, taking into account the readiness signals 15.i.2 from the function calculation blocks 10.i.

 Consider an example of a specific implementation of a programmable logic device.

Let n = 3, then the first group of 37.1 elements from n groups of 37.1-37.n elements 2 • 2 NOT-AND-OR contains 2 ^n-1 = 2 ^3-1 = 4 elements, the second group 37.2 contains 2 ^3-2 = 2 elements, and the third group 37.3 contains 2 ^3-3 = 1 element, i.e. its output implements a logical function.

где a, b, c, d, e, g, h - настроечные сигналы, поступающие на входы 10. i. 2 (a - "младший", h - "старший"), x₃,

- парафазные входные сигналы, поступающие на входы 10.i.1.

where a, b, c, d, e, g, h are tuning signals received at inputs 10. i. 2 (a - "younger", h - "senior"), x ₃ ,

- paraphase input signals supplied to the inputs 10.i.1.

 By setting the tuning signals, any function of three arguments can be obtained.

Очевидно, что z₂ можно получить из z₁ следующей заменой

а z₄ получают из z₃, если x₃ заменяется на

и наоборот, функция z₁ получается из z₂ заменой

а

заменяется на x₃, т.е. имеется своего рода "симметрия".Convert z:

Obviously, z ₂ can be obtained from z _{1 by the} following replacement

and z _{4 is} obtained from z ₃ if x ₃ is replaced by

and vice versa, the function z _{1 is} obtained from z _{2 by} replacing

a

is replaced by x ₃ , i.e. there is a kind of "symmetry".

, тогда

Таким образом, z₄ получают из z₃, если выполнена замена

а z₆ получают из z₅, если x₃ заменяют на

.Let a function of 2 arguments be realized, let us say the essential variables x ₂ x ₃ , i.e. x ₁ = 0,

then

Thus, z _{4 is} obtained from z ₃ if a replacement is made

and z _{6 is} obtained from z ₅ if x _{3 is} replaced by

.

а z₅ получают из z₆, если

заменяют на x₃.Similarly, z _{3 is} obtained from z ₄ if a replacement is made

and z _{5 is} obtained from z ₆ if

replace with x ₃ .

Таким образом, реализацию этой функции в два такта можно получить, вычисляя на половине элементов 37, например вначале функции

, а затем, заменив набор констант 0110 на 1001 и переменную

на x₃, и на тех же технических средствах вычислить функцию

Тогда

- дизъюнкция выходных сигналов D-триггеров 21, 22 (фиг. 2).We implement the function 3 of the arguments "modulo 2 addition":

Thus, the implementation of this function in two steps can be obtained by calculating on half the elements 37, for example, at the beginning of the function

and then, replacing the set of constants 0110 with 1001 and a variable

on x ₃ , and on the same technical means calculate the function

Then

- disjunction of the output signals of the D-flip-flops 21, 22 (Fig. 2).

Следовательно, вычисления при наличии отказов производятся, например, путем получения вначале

а затем заменой набора констант 0111 на 0001 и переменной x₃ на

путем вычисления

с последующей дизъюнкцией

аналогично вышеописанному.We realize the function of 3 arguments "majorization":

Therefore, calculations in the presence of failures are performed, for example, by first obtaining

and then replacing the set of constants 0111 with 0001 and the variable x ₃ with

by calculating

with subsequent disjunction

similar to the above.

 We will evaluate the technical and economic efficiency of the proposed device.

 It can be estimated by the magnitude of the relative increase in speed when calculating logical functions in the event of failure of the proposed programmable logic device in relation to the prototype.

Рассмотрим случай r отказов, т.е. по одному описанному выше отказу в r основных технических средствах вычисления логических функций, r≤m-1, где m - количество логических функций (блоков вычисления функций). Очевидно, что в этом случае необходимо также одно перепрограммирование r технических средств вычисления функций с запоминанием промежуточных результатов во внешних технических средствах, если количество оставшихся работоспособных технических средств позволяет восполнить "потери". Если же их остается меньше половины

, то необходимо дополнительное перепрограммирование. Таким образом, необходимо

тактов перепрограммирования, где int - обозначение ближайшего большего натурального числа.Consider the case of the occurrence of one failure in the basic technical means of computing logical functions - in the block for calculating logical functions (in one of the half elements of groups 20, 37, 39) of the proposed device and in one of the elements OR, AND that determine the calculated logical function in the prototype failures that do not change the result of calculations, for example, during testing. Then, to calculate all the logical functions, one “regular cycle” is required, reprogramming to calculate the logical function “assigned” to the failed technical means takes 2g + 1 cycle, where g is the number of conjunctions in the calculated logical functions and one more cycle of calculations - without taking into account the memory intermediate results in external technical means. The proposed device for calculating all functions when a failure is detected in one of the function calculation blocks takes 2 clock cycles under the same conditions - without taking into account the time of diagnosis (testing) and storing the calculation results in operable blocks according to the first clock. Thus, the gain in speed δ is described by the expression

Consider the case of r failures, i.e. according to one failure described above in r basic technical means of computing logical functions, r≤m-1, where m is the number of logical functions (function calculation blocks). Obviously, in this case one more reprogramming of technical means of calculating functions with storing intermediate results in external technical means is also necessary if the number of remaining working technical means makes it possible to make up for the "losses". If less than half of them remain

then additional reprogramming is necessary. Therefore, it is necessary

reprogramming cycles, where int is the designation of the nearest larger natural number.

При r= m устройство-прототип не может вычислить ни одной логической функции.Therefore, the gain in speed is determined by the relation

For r = m, the prototype device cannot calculate a single logical function.

 In addition, in the prototype for diagnostics (testing), additional reprogramming (2g + 1 clock cycle) is necessary, for example, to compare by external technical means the results of calculating the same logical functions obtained on half of the basic technical means with the other half. In the proposed device, this can be done by external technical means by comparing the results obtained after setting the calculation mode in the absence of failures and obtained after setting the calculation mode in the presence of failures, i.e. for three measures.

 Achieving the objective of the invention is confirmed by the above analysis.

Claims (2)

1. A programmable logic device containing the first, second groups of D-flip-flops of m • 2 ^{n each} (n is the number of input variables, m is the number of output functions), the third group of D-flip-flops of 2 (n - 1) m, group m (n - 1) AND elements, counter, group m • 2 ⁿ AND elements with three states at the output, decoder, group m (n - 1) OR elements, and the reset inputs of D-triggers of the first, second, third groups, counter are the device reset input, the counter counter input is the device programming input, and the counter information outputs are connected to the information inputs of the decoder, non-inverse outputs of the D-triggers of the second group are connected to the control inputs of the corresponding elements AND with three states at the output of the group m • 2 ⁿ elements AND with three states at the output, non-inverse outputs of the D-triggers of the third group are connected to the second inputs of the corresponding elements AND of the group m • 2 ⁿ elements AND, characterized in that the second group of m • 2 ⁿ elements AND with three states at the output and m blocks of function calculation are introduced into it, and the control inputs of the elements of the second group m • 2 ⁿ AND elements with three output states are connected to the inverse outputs of the corresponding D-triggers of the second group, and the information inputs of the elements of the second group m • 2 ⁿ AND elements with three output states are the corresponding expansion inputs of the corresponding group of m groups of extension inputs , the outputs of the elements And with three states at the output of the first and second groups are combined and connected to the settings inputs of the corresponding of m blocks of calculation of functions, the first output of the decoder is connected to the synchronization inputs D the first group of triggers, the outputs of which are connected to the information inputs of the elements and the group of m • 2 ⁿ elements with three output states, the second decoder output is connected to the synchronization inputs of the D-triggers of the second group, the third decoder output is connected to the synchronization inputs of the D-triggers of the third group, inverted outputs of which are connected to second inputs of m • ⁿ 2 elements or groups, a fourth output is the output of the decoder closure device programming data inputs of D-flip-flops of the first and second groups are I are the corresponding expansion inputs of the corresponding of m groups of expansion inputs, the information inputs of the D-triggers of the third group are 2 (n - 1) the expansion input of the corresponding of m groups of expansion inputs, the first inputs of the elements AND the groups of m (n - 1) elements AND are the corresponding of n - 1 non-inverse inputs of the group 2n • m inputs of paraphase input variables (2m bits for each block of function calculation), the first inputs of the OR elements of the group m (n - 1) elements OR are the corresponding of n - 1 inverse inputs of the group 2n • m inputs paraphase input variables (2m bits for each of m function calculation blocks), the outputs of AND elements of a group of m (n - 1) AND elements are connected to the corresponding ith non-inverse inputs of paraphase input variables of the corresponding of m function calculation blocks

and the senior non-inverse discharge of these inputs is the corresponding nth non-inverse input of the group of 2n • m inputs of paraphase input variables, the outputs of the OR elements of the group of m (n - 1) elements OR are connected to the corresponding i-inverse inputs of the paraphase input variables of the corresponding m calculation blocks functions

and the senior inverse discharge of these inputs is the corresponding nth inverse input of the group of 2n • m inputs of paraphase input variables, the reset inputs of the function calculation blocks are the device reset input, the synchronization inputs of the function calculation blocks are the device synchronization input, the additional reset inputs of the function calculation blocks are a group of m inputs of additional device reset, inputs of reconfiguration of m function calculation blocks are a group of m inputs of reconfiguration of function calculation blocks at open the inputs, the reconfiguration type inputs of m function calculation blocks for failures are a group of m inputs the reconfiguration type inputs of function calculation blocks for failures, the outputs of a non-inverse function value of the function calculation blocks are the corresponding bits of the group m of the outputs of the device function values, the outputs of the inverse value of the function of the function calculation blocks are the corresponding bits groups of m outputs of inverse values of the functions of the device, outputs of the readiness of the results of calculations of blocks of calculation of functions are sing m outputs readiness results of the calculation of the functions of the device. 2. The device according to claim 1, characterized in that each function calculation unit contains an additional group of 4 • 2 ^n-1 AND elements with three output states, two D-flip-flops, T-flip-flop, RS-pulse fixation trigger, five elements OR, three AND elements, four inverters, n groups of elements 2 • 2НЕ - AND - OR (each i-th group includes 2 ^n-1 elements,

, delay element, an additional group of AND elements with three states at the output, and the control inputs of odd AND elements with three states at the output of the group of 4 • 2 ^n-1 AND elements with three states at the output are connected to the non-inverse output of the T-trigger, inverse output which is connected to the control inputs of even elements AND with three states at the output of a group of 4 • 2 ^n-1 elements AND with three states at the output, the information inputs of which are the corresponding bits of the unit settings inputs, the information inputs are not 4 And 2 ^n-1 elements And with three states at the output from the first half of the group are connected to the corresponding j-th bits of the second half of the settings inputs, j = 2 ^n-1 + 1, 2 ⁿ , information the inputs of odd AND elements with three states at the output from the second half of 4 • 2 ^n-1 AND elements with three states at the output are connected to the corresponding M-th digits of the first half of the tuning inputs,

, the outputs of the odd elements AND with three states at the output of a group of 4 • 2 ^n-1 elements AND with three states at the output are combined with the outputs of the corresponding even elements AND with three states at the output and connected to the corresponding odd inputs of the corresponding element 2 • 2НЕ - And - OR the first group of n groups of elements 2 • 2НЕ - AND - OR (two odd pairs - even element AND with three states at the output of each element 2 • 2НЕ - AND - OR), even inputs of elements 2 • 2НЕ - AND - OR each S-th group,

, elements 2 • 2НЕ - AND - OR are the corresponding bits of the inputs of the paraphase input variables of the block (the second input of each element 2 • 2НЕ - AND - OR of the S-th group is the input X _s , the fourth -

, outputs of elements 2 • 2НЕ - AND - OR S-th group,

, where n is the number of input variables, connected to the corresponding odd inputs of the elements of 2 • 2HE - AND - OR S + 1 groups, and to each element of 2 • 2HE - AND - OR e groups,

, the outputs of two elements of the e - 1 group are connected, the output of the only element 2 • 2НЕ - AND - OR the last n-th group of n groups of elements 2 • 2НЕ - AND - OR is connected to the information input of the first D-trigger, the second input of this element is connected to the output of the first OR element, and the fourth input of this element 2 • 2НЕ - AND - OR of the nth group is connected to the output of the second OR element, the first inputs of the first and second elements OR are connected to the outputs of the first and second elements AND, accordingly, the second input of the first element OR connected to the combined outputs of the first and second AND elements with three states at the output of an additional group of AND elements with three states at the output, the second input of the second OR element is connected to the combined outputs of the third and fourth AND elements with three states at the output of an additional group of AND elements with three states at the output, second the inputs of the first and second elements And, the inputs of the second and fourth inverters are the input of the reconfiguration of the unit in case of failure, the first input of the first element And and the input of the first inverter are the input of the reconfiguration type and the unit in case of failure, the output of the first inverter is connected to the first input of the second element AND, the input of zeroing of the first D-trigger and the first input of the fourth element OR are the reset input of the block, synchronization inputs of the first and second D-triggers, counting input of the T-trigger, element input delays are the input of the block synchronization, and the output of the delay element is connected to the input of the RS-trigger for fixing the pulse, the output of the second inverter is connected to the second input of the fourth OR element, the third input of which is the input of the additional block reset, the output of the fourth OR element is connected to the zeroing inputs of the second D-trigger, the RS-triggers for fixing the pulse and the T-trigger, the output of the first D-trigger is connected to the information input of the second D-trigger and the first input of the third OR, the second input of which is connected to the output of the second D-flip-flop, the output of the third OR element is the output of the block function value and is connected to the input of the third inverter and the first input of the fifth OR element, the output of the third inverter is the output of the inverse value of the block function, the output is of the fifth inverter is connected to the second input of the fifth OR element, the third input of which is connected to the output of the third AND element, the output of the fifth OR element is the readiness output of the block function calculation results, the first input of the third AND element is connected to the output of the RS-trigger for fixing the pulse, and the second input of the third And element is connected to the inverse output of the T-trigger, which is also connected to the control inputs of the odd elements And with three states at the output of an additional group of elements with three states at the output, to the input I will give control of even elements of which the non-inverse output of the T-trigger is connected, the information inputs of the first and fourth AND elements with three states at the output of the additional group are the nth non-inverse input x _{n of the} paraphase input variables of the block, and the information inputs of the second and third elements AND with three states at the output of an additional group of elements AND with three states at the output are the nth inverse input

paraphase input block variables.

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