RU2074415C1 - Parallel co-processor which solves boolean equations - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has processor matrix, control and interface unit. Processor matrix is designed as device for parallel reading and writing with 2n address inputs, reset input and one output. Interface and control unit is designed as unit which selects register addresses and has start input, signal input, 2+2{log₂(α)}+2{log₂(m)} + {log₂(n)} load inputs, where {x} means minimal upper round integer, reset input, writing input, 2n control outputs, three solution outputs, m reading outputs and one reset output. EFFECT: increased speed of high-parallel exhaustive search of solutions due to simplified design of processor elements, decreased number of clock cycles which processor element needs for check of one variant. 10 cl, 20 dwg

Description

 The invention relates to computer technology, in particular to highly parallel specialized processors.

 As you know, most practically important discrete and combinatorial problems can be solved using some sorting process.

 It is believed that finding an effective solution for most exhaustive problems (they are called NP-problems) is fundamentally impossible (Gary M. Johnson D. Computing machines and hard-to-solve problems, M. Mir, 1982).

 Among NP-problems, a subclass of the so-called NP-complete problems is distinguished. All NP-problems in polynomial time are reducible to each other. Thus, having learned how to efficiently solve an NP-complete problem, one can effectively solve all NP-problems. Among all NP-complete problems, the problem of satisfiability of Boolean formulas stands out. Cook's fundamental theorem (S.A. Cook, Complexity of theorem derivation procedures, Cybernetic collection, New Series, Issue 12, M. Mir, 1975) establish the NP-completeness of this problem, and the NP-completeness of all other problems is proved by polynomial reduction to the satisfiability problem Boolean formulas. We can say that this task naturally contains all the NP-problems.

The feasibility problem for Boolean formulas is formulated as follows:
Given: n Boolean variables x ₁ , x ₂ , x _n and C is the set of cardinality K of disjunctions from these variables.

CD ₁ (x ₁ , x ₂ , x _n ), D ₂ (x ₁ , x ₂ , x _n ), D _to (x ₁ , x ₂ , x _n )}
Note that some disjunctions may actually depend on fewer than n numbers of variables. Each disjunction has the form: e ₁ + e ₂ +. + E _n , where e _{i is} either identically equal to 0 (if the disjunction in question is actually independent of the variable x _i ), or it is a literal of x _i . Each literal of x _i has the form either x _i or ^{^} x _i . Hereinafter, 0 is a logical zero, a "+" sign of logical addition, a "^" sign of logical negation.

It is required to determine whether there exist sets of values of the variables x ₁ , x ₂ , x _n that fulfill the set C, i.e. such sets a ₁ , a ₂ , a _n values of these variables such that for any j:
D _j (a ₁ , a ₂ , a _n ) 1 a _j ∈ {0,1}. Hereinafter, 1 is a logical unit. If such sets exist, you need to find at least one of them.

 A known processor consisting of an arithmetic logic device (ALU), control device (UE), random access memory (OP), input-output device (I / O) and read-only memory (PP) (Kagan B.M. Electronic computers and systems, M. Energoatomizdat, 1985).

 This structure is universal, which can be used, inter alia, to solve the problem of the feasibility of Boolean formulas.

a lack of the considered universal processor structure is the impossibility of its use with a large dimension of the task, because the number M of machine clocks necessary to solve the problem of the feasibility of Boolean formulas of n Boolean variables is generally equal to K * 2 ⁿ , where K is a (sufficiently large) number. For n of the order of several tens, M becomes unacceptably large.

 Partially indicated disadvantages were eliminated in the high-parallel MPP processor (Massively Parallel Processor) of Goodyear Aerospace (USA), consisting of: a processor matrix (PM), which is an array of 16384 processor elements (PE), each of which is a sequential-bit processor equipped with own local memory of 1024 bits; processor matrix control devices (UPM); transition memory (PP) for buffering and re-arranging data; interface system (IS) for controlling the data flows to which the host machine (HOST machine) is connected (Supercomputer. Hardware and software implementation. Ed. by S. Fernbach, M. Radio and Communications, 1991, chap. 10, sections 10.1 10.3, p. 215 - 246).

 A high degree of parallelism of this processor makes it possible to increase the speed of solving the problem of the feasibility of Boolean formulas, which initially has a high degree of parallelism, by 16384 times, but this is not enough in the case of a large number of variables. In addition, a single processor element to consider a single set of variable values requires a large number of machine clocks.

 The objective of the proposed technical solution is to simplify the device by reducing the processor element to the level of one memory cell and increase its speed by reducing the number of machine clocks required by the processor element to consider one option to one.

идентичных блока записи и считывания, дешифратор адреса блока,

входовой каскад элементов И, причем i₁-й (i₁ 1, 2n₁) вход дешифратора адреса блока сделать i₁-м адресным входом процессорной матрицы, k₁-й (k₁ 1,

) выход дешифратора адреса блока соединить с разрешающим входом k₁-го блока записи и считывания, i₂-й (i₂ 1,2n₂) вход адреса строки каждого блока записи и считывания соединить с i₂+2n₁-м адресным входом процессорной матрицы, i₃-й (i₃ 1,2n₃) вход адреса столбца каждого блока записи и считывания соединить с i₃ + 2n₁+2n₂-м адресным входом процессорной матрицы, вход сброса каждого блока записи и считывания соединить с входом сброса процессорной матрицы, выход k₁-го (k₁ 1,

) блока записи и считывания соединить с k₁-м входом

входового каскада элементов И, выход которого соединить выходом процессорной матрицы, при этом каждый блок записи и считывания содержит матрицу

запоминающих ячеек, дешифратор адреса строки, дешифратор адреса столбца, n₂

-входовых каскадов элементов И,

входовый главный каскад элементов И, 2n₂ ключей, выполненных в виде элементов И с двумя входами, причем k₂-й (k₂ 1,

) выход дешифратора адреса строки соединить с первыми входами выборки всех запоминающих ячеек k₂-й строки матрицы запоминающих ячеек, k₃-й (k₃ 1,

) выход дешифратора адреса столбца соединить с вторыми входами выборки всех запоминающих ячеек k₃-го столбца матрицы запоминающих ячеек, первый вход i₂-го (i₂ 1,2n₂) ключа соединить i₂-м входом адреса строки блока записи и считывания, второй вход каждого ключа соединить с разрешающим входом блока записи и считывания, i₂-й (i₂ 1,2n₂) вход дешифратора адреса строки соединить с выходом i₂-го ключа, i₃-й (i₃ 1,2n₃) вход дешифратора адреса столбца соединить с i₃-м входом адреса столбца блока записи и считывания, вход сброса каждой из запоминающих ячеек соединить с входом сброса блока записи и считывания, выход k₃-й запоминающей ячейки k₂-го ряда матрицы запоминающих ячеек соединить с k₃ входом k₂-го каскада элементов И, выход k₂-го каскада элементов И соединить с k₂-м входом

входового главного каскада элементов И, выход которого соединить выходом блока записи и считывания, в состав каждой запоминающей ячейки включить запоминающий элемент и логический элемент И с двумя входами, причем первый и второй входы логического элемента И соединить с первым и вторым входами выборки запоминающей ячейки, выход элемента И соединить с входом записи единицы запоминающего элемента, вход записи нуля запоминающего элемента соединить с входом сброса запоминающей ячейки, прямой выход запоминающего элемента соединить выходом запоминающей ячейки; дешифраторы адресов блока, строк и столбцов выполнить в виде параллельных адресных дешифраторов, имеющих 2^N выходов и 2N адресных входов (N=n₁, n₂, n₃ для дешифраторов блока, адреса строки и адреса столбца соответственно), по одному независимому входу для нулевого и для единичного значения каждого двоичного разряда адреса, в состав 2^N-входового (N n₁, n₂, n₃) каскада элементов И включить 2^N-1 элементов И с двумя входами, расположенных на N уровнях, при этом на I-м (I 1, N) уровне расположить 2^N-I элементов, входы каскада с номерами 2k₁-1 и 2k₁ (k₁ 1,2^N-1) соединить с входами элемента И с номером k₁ первого уровня, выходы элементов И с номерами 2k_I-1 и 2k_I (k 1,2^N-I) I-го уровня соединить с входами элемента И номер k_I I+1-го уровня, выход одного элемента И N-го уровня сделать выходом всего каскада; в состав устройства управления включить блок выбора дизъюнкций, блок адресации, m+1 разрядный счетчик циклов по модулю 2^m+1, блок элементов И, m+1 разрядный регистр номера последнего цикла, блок ИЛИ-Е, блок переключателей, первый и второй определители порядка дизъюнкций, блок элементов ИЛИ, блок синхронизации, элемент ИЛИ с двумя входами, причем выход j-го (j 1,m+1) разряда регистра номера последнего цикла соединить с 2j-1-м входом блока элементов И, выход j-го разряда счетчика циклов соединить с 2j-входом блока элементов И с 2(m+1) входами, выход блока элементов И с 2(m+1) входами соединить с первым выходом решения устройства управления и с первым входом элемента ИЛИ, выход j-го (j 1,m) разряда счетчика циклов соединить с j-м управляющим входом блока выбора дизъюнкций, l-й (l 1,L), выход которого соединить с l-м входом блока переключателей и с l-м входом блока ИЛИ-Е, выход блока ИЛИ-Е соединить с вторым выходом решения устройства управления и с вторым входом элемента ИЛИ, l-й выход блока переключателей соединить с l-м входом первого определителя порядка дизъюнкций, L+l+1-й выход блока переключателей соединить с l-м, входом второго определителя порядка дизъюнкций, L+1-й выход блока переключателей соединить с L+1-м входом первого определителя порядка дизъюнкций, 2L+2-й выход блока переключателей соединить с L+1-м входом второго определителя порядка дизъюнкций, l-е выходы первого и второго определителей порядка дизъюнкций соединить, соответственно, с 2l+1-м и 2l-м входами блока элементов ИЛИ, l-й выход которого соединить с 1-м управляющим входом блока адресации, i-й (i 1,2n, n n₁ + n₂ + n₃), управляющий выход которого соединить с i-м управляющим выходом устройства управления, сигнальный выход первого определителя порядка дизъюнкций соединить с первым входом блока синхронизации, сигнальный выход второго определителя порядка дизъюнкций соединить с вторым входом блока синхронизации, третий вход блока синхронизации соединить с сигнальным входом устройства управления, четвертый вход блока синхронизации соединить с входом запуска устройства управления, пятый вход блока синхронизации соединить с выходом логического элемента ИЛИ, первый выход блока синхронизации соединить с третьим выходом решения устройства управления, второй выход блока синхронизации соединить с L+1-м входом блока переключателей, третий выход блока синхронизации соединить с L+2-м входом блока переключателей, четвертый выход блока синхронизации соединить со счетным входом счетчика циклов и с выходом сброса устройства управления, p₁-й вход (p₁ 1,log₂(m)}) загрузки регистра номера последнего цикла соединить с p₁-м входом загрузки устройства управления, q₂ 1,log₂(m)} +log₂(L)}+1) вход загрузки блока выбора дизъюнкций соединить с p₂-м (p₂ q₂+{log₂(m)}) входом загрузки устройства управления, q₃-й (q₃ 1,log₂(n)} +log₂(L)}+1), вход загрузки блока адресации соединить с p₃-м (p₃ q₃ + 2*{log₂(m)} +log₂(L)}+1) входом загрузки устройства управления, входы сброса блока выбора дизъюнкций, блока адресации, счетчика циклов и регистра номера последнего цикла соединить с входом сброса устройства управления, входы записи блока выбора дизъюнкций, блока адресации и регистра номера последнего цикла соединить с входом записи устройства управления, в состав блока выбора дизъюнкций включить m инверторов, дешифратор адреса схемы, дешифратор адреса ячейки и L схем выбора, причем j-й (j 1,m) управляющий вход блока выбора дизъюнкций соединить с 2j-1-ми управляющими входами всех схем выбора и с входом j-го и инвертора, выход которого соединить с 2j-ми управляющими входами всех схем выбора, выход l-й (l=1,L) схемы выбора соединить с l-м выходом блока выбора дизъюнкций, q₄-й (q₄ 1,log₂(L)}) вход загрузки блока выбора дизъюнкций соединить с q₄-м входом дешифратора адреса схемы, 1-й выход которого соединить с разрешающим входом 1-й схемы выбора, q₅-й (q₅log₂(L)}+1,log₂(m)}+{log₂(L)}+1), вход загрузки блока выбора дизъюнкций соединить с q₅-{log₂(L)}-м входом дешифратора адреса ячейки, j₁-й (j₁ 1,2m) выход которого соединить с j₁-ми входами выборки всех схем выбора, входы сброса и записи каждой схемы выбора соединить с входами сброса и записи блока выбора дизъюнкций, в состав каждой схемы выбора включить 2m запоминающих элементов, 2m элементов И с двумя входами, 2m элементов И с тремя входами, m элементов ИЛИ с тремя входами, элемент И-Е, блок элементов И, причем в каждой схеме выбора прямой выход 2j-1-го (j=1,m) запоминающего элемента соединить с первым входом j-го элемента ИЛИ, прямой выход 2j-го запоминающего элемента соединить с первым входом 2j-1-го элемента И с двумя входами, инверсный выход 2j-го запоминающего элемента соединить с первым входом 2j-го элемента и с двумя входами, второй вход 2j-1-го элемента И с двумя входами соединить с 2j-1-м управляющим входом схемы выбора, второй вход 2j-го элемента И с двумя входами соединить с 2j-м управляющим входом схемы выбора, выходы 2j-1-го и 2j-го элементов И с двумя входами соединить с вторым и третьим входами j-го элемента ИЛИ, выход j-го элемента ИЛИ соединить с j-м входом блока элементов И, выход которого соединить с выходом схемы выбора, прямые выходы первого и второго запоминающих элементов соединить с первым и вторым входами элемента И-Е, выход которого соединить с m+1-м входом блока элементов И, вход записи единицы j₁-го (j₁ 1,2m) запоминающего элемента соединить с выходом j₁-го элемента И с тремя входами, входы записи нуля всех запоминающих элементов соединены с входом сброса схемы выбора, первый вход j₁-го элемента И с тремя входами соединить с j₁-м входом выборки схемы выбора, вторые входы всех элементов И с тремя входами соединить с разрешающим входом схемы выбора, третьи входы всех элементов И с тремя входами соединить с входом записи схемы выбора; в состав блока адресации включить дешифратор адреса схемы, дешифратор адреса ячейки, n n₁ + n₂ + n₃ схем адресации, причем l-e (l 1,L) управляющие входы всех схем адресации соединить с l-м управляющим входом блока адресации, первый и второй выходы i-й (i 1,n) схемы адресации соединить с 2i-1-м и 2i-м выходами блока, q₆-й (q₆ 1,log₂(n)}) вход загрузки блока адресации соединен с q₆-м входом дешифратора адреса схемы, i-й выход которого соединить с разрешающим входом i-й схемы выбора, q₇-й (q₇log₂(n)}+1,log₂(n)}+log₂(L)}+1), вход загрузки блока адресации соединить с q₇-{log₂(n)}-м входом дешифратора адреса ячейки, l₁-й (l₁ 1,2L), выход которого соединить с l₁-ми входами выборки всех схем адресации, входы сброса и записи каждой схемы адресации соединить с входами сброса и записи блока адресации, в состав каждой схемы адресации включить 2L запоминающих элементов, два блока элементов ИЛИ с L входами каждый, 2L ключей, выполненных в виде элементов И с двумя входами, 2L элементов И с тремя входами, причем прямые выходы 2l-1-го и 2l-го (l=1,L) запоминающих элементов, соединить с первыми входами 2l-1-го и 2l-го ключей, вторые входы 2l-1-го и 2l-го ключей соединить с l-м управляющим входом схемы адресации, выходы всех нечетных ключей соединить с входами первого блока элементов ИЛИ, выходы всех четных ключей соединить с входами второго логического блока ИЛИ, выходы первого и второго логических блоков ИЛИ соединить с первым и вторым выходами схемы адресации, вход записи единицы l₁-го (l₁ 1, 2L) запоминающего элемента соединить с выходом l₁-го элемента И с тремя входами, входы записи нуля всех запоминающих элементов соединить с входом сброса схемы адресации, первый вход l₁-го элемента И с тремя входами соединить с l₁-м входом выборки схемы адресации, вторые входы всех элементов И с тремя входами соединены с разрешающим входом схемы адресации, третьи входы всех элементов И с тремя входами соединить с входом записи схемы адресации.The technical result of the task is achieved by the fact that in a highly parallel special processor to solve the problem of the feasibility of Boolean formulas, consisting of a processor matrix, control device and interface, it is proposed that the ith (i 1,2n) address input of the processor matrix be connected to the ith control output of the device control, the reset input of the processor matrix is connected to the reset output of the control device, the output of the processor matrix is connected to the signal input of the control device, the start input of which is connected to the output ohm trigger interface, j-th (j = 1, m) reading output control device connected to the j-th input interface read, p-th (p 1,2 + 2 (log ₂ (L)} +2 {log ₂ ( m)} + {log ₂ (n)} x} denotes the smallest integer greater than or equal to x) connect the boot input of the control device to the pth output of the interface load, the reset input of the control device to connect to the reset output of the interface, connect the record input of the control device with the output of the interface record, the first second and third outputs of the solution of the control device are connected to the first, second and third inputs of the solution of the interface, with responsibly in the processor matrix include

identical write and read blocks, block address decoder,

input cascade of elements And, whereby i ₁ (i ₁ 1, 2n ₁ ) the input of the address decoder of the block is made i the _1st address input of the processor matrix, k ₁ (k ₁ 1,

) the output of the decoder of the block address is connected to the enable input k of the _1st write and read block, the _2nd (i ₂ 1,2n ₂ ) line address input of each write and read block is connected to the i ₂ + 2n _1st processor input address matrices, i _3rd (i ₃ 1,2n ₃ ) connect the column address of each write and read block to the i ₃ + 2n ₁ + 2n _2nd address of the processor matrix, reset input of each write and read block to the reset input processor matrix, output k ₁ th (k ₁ 1,

) of the writing and reading unit to be connected to the k _1st input

the input stage of the AND elements, the output of which is connected by the output of the processor matrix, with each recording and reading unit containing a matrix

storage cells, row address decoder, column address decoder, n ₂

- input cascades of elements AND,

input main cascade of AND elements, 2n ₂ keys made in the form of AND elements with two inputs, and k _2- th (k ₂ 1,

) connect the output of the row address decoder to the first inputs of the sample of all storage cells k the _2nd row of the matrix of storage cells, k _3rd (k ₃ 1,

) connect the output of the column address decoder to the second inputs of the sample of all storage cells k of the _3rd column of the matrix of storage cells, connect the first input of the _2nd (i ₂ 1,2n ₂ ) key with the _2nd input of the address of the row of the write and read unit, connect the second input of each key to the enable input of the write and read unit, connect the _2nd (i ₂ 1,2n ₂ ) line address decoder input with the output of the _2nd key, i _3rd (i ₃ 1,2n ₃ ) input column address decoder connected to the i th input address ₃ recording unit and reading column, the reset input of each of the memory cells with one with the reset input of the write and read unit, an output k-th memory cell ₃ k ₂ -th row of the matrix of memory cells connected to k ₃ k ₂ -th input stage of AND gates, the output k ₂ -th stage elements and are connected to k ₂ - m entrance

input main cascade of AND elements, the output of which is connected by the output of the recording and reading unit, to include in the composition of each memory cell a memory element and logical element AND with two inputs, the first and second inputs of the logical element And connected to the first and second inputs of the sample memory cell, output element And connect to the recording input of the unit of the storage element, the input of the recording of zero of the storage element to connect to the reset input of the storage cell, the direct output of the storage element to connect the output storage cell; the decoders of the addresses of the block, rows and columns are executed in the form of parallel address decoders having 2 ^N outputs and 2N address inputs (N = n ₁ , n ₂ , n ₃ for the decoders of the block, row addresses and column addresses, respectively), one independent input for zero and for a single value of each binary digit of the address, in the 2 ^N- input (N n ₁ , n ₂ , n ₃ ) cascade of elements And include 2 ^N-1 elements And with two inputs located at N levels, while on I -m (I 1, N) level arrange 2 ^NI elements, the inputs of the cascade with numbers 2k ₁ -1 and 2k ₁ (k ₁ 1,2 ^N-1 ) are connected connect the inputs of the AND element with the number k _{1 of the} first level, the outputs of the AND elements with the numbers 2k _I -1 and 2k _I (k 1,2 ^NI ) of the 1st level, connect the inputs of the And element with the number k _I I + 1 of the 1st level, make the output of one element And the Nth level the output of the entire cascade; include a disjunction selection block, an addressing block, m + 1 bit cycle counter modulo 2 ^{m + 1} , a block of AND elements, m + 1 bit register of the last cycle number, an OR-E block, a switch block, the first and second identifiers disjunction order, block of OR elements, synchronization block, OR element with two inputs, the output of the jth (j 1, m + 1) discharge of the register register of the last cycle number connected to the 2j-1st input of the block of AND elements, the output of the jth discharge cycle counter connected to the 2j-input of the block of elements AND with 2 (m + 1) inputs, the output of the block ele And with 2 (m + 1) inputs, connect to the first output of the control device solution and to the first input of the OR element, connect the output of the jth (j 1, m) discharge of the cycle counter to the jth control input of the disjunction selection block, l- d (l 1, L), the output of which is connected to the l-th input of the switch block and with the l-th input of the OR-E block, the output of the OR-E block is connected to the second output of the control device solution and to the second input of the OR element, l- connect the first output of the switch block to the l-th input of the first determinant of the order of disjunctions, L + l + connect the first output of the switch block with the lth, input of the second determinant of the order of clauses, L + 1st output of the switch block connect with L + 1st input of the first determinant of the order of disruptions, 2L + 2nd output of switch block connect with L + 1st input of the second determinant of the order of disjunctions, connect the lth outputs of the first and second determinants of the order of disjunctions, respectively, with the 2l + 1st and 2lth inputs of the block of OR elements, the lth output of which is connected to the 1st control input of the addressing block, i (i 1,2n, nn ₁ + n ₂ + n _3), the control output of which is connected to the i-th control output device councils connect the signal output of the first clause order determiner to the first input of the synchronization block, connect the signal output of the second clause order determinant to the second input of the synchronization block, connect the third input of the synchronization block to the signal input of the control device, connect the fourth input of the synchronization block to the start input of the control device, connect the fifth input of the synchronization block with the output of the logical element OR, the first output of the synchronization block with the third output of the solution control, connect the second output of the synchronization block to the L + 1st input of the switch block, connect the third output of the synchronization block to the L + 2nd input of the switch block, connect the fourth output of the synchronization block to the counting input of the cycle counter and to the reset output of the control unit, p ₁ input (p ₁ 1, log ₂ (m)}) to connect the register of the last cycle number to the p ₁ input of the control device, q ₂ 1, log ₂ (m)} + log ₂ (L)} +1) connect the boot input of the disjunction selection block to the p _2- th (p ₂ q ₂ + {log ₂ (m)}) boot input of the control device, q _3rd (q ₃ 1, log ₂ (n)} + log ₂ (L)} + 1), connect the load input of the addressing unit to p ₃ (p ₃ q ₃ + 2 * {log ₂ (m)} + log ₂ (L)} + 1) connect the control device boot input, the reset input of the clause selection block, addressing block, cycle counter and register of the last cycle number to the control input reset input, the disjunction selection block record inputs, address block and the last number register of the cycle, connect to the recording input of the control device, include m inverters, a circuit address decoder, a cell address decoder and L circuit selectors in the disjunction selection block a, and the jth (j 1, m) control input of the disjunction selection block is connected to the 2j-1 control inputs of all the selection circuits and to the input of the jth and inverter, the output of which is connected to the 2jth control inputs of all the selection circuits , connect the output of the lth (l = 1, L) selection circuit with the lth output of the clause selection block, q _4th (q ₄ 1, log ₂ (L)}) connect the boot input of the clause selection block to q ₄ - m the input of the decoder of the circuit address, the 1st output of which is connected to the enable input of the 1st selection circuit, q _5th (q ₅ log ₂ (L)} + 1, log ₂ (m)} + {log ₂ (L) } 1), the load input selection unit connected to disjunctions q ₅ - {log ₂ (L)} - input cell address decoder, j ₁ th (j ₁ 1,2m) whose output is connected to the j -th input sample ₁ all selection circuits, and the reset inputs of each entry selection circuit connected to the reset inputs of disjunctions and write selecting unit, each of the selection schemes include 2m memory elements, 2m AND elements with two inputs, 2m AND elements with three inputs, m OR elements with three inputs, IE element, block of AND elements, and in each selection scheme the direct output is 2j-1st ( j = 1, m) of the storage element to connect with the first input of the j-th element OR, direct output of the 2j-th memory connect the input element to the first input of the 2j-1st element AND with two inputs, connect the inverse output of the 2j-th storage element to the first input of the 2jth element and two inputs, connect the second input of the 2j-1st element AND to two inputs with the 2j-1st control input of the selection circuit, connect the second input of the 2j-th AND element with two inputs to the 2j -th control input of the selection circuit, the outputs of the 2j-1st and 2j AND with two inputs connect to the second and the third inputs of the jth OR element, the output of the jth OR element is connected to the jth input of the block of AND elements, the output of which is dinit with the output of the circuit selection, the direct outputs of the first and second memory elements connected to first and second inputs of the AND-E, whose output is connected to the m + 1-th input block of AND gates, entrance recording unit ₁ j-th (j ₁ 1 2m) connected to the memory element ₁ j-th output of the AND with three inputs, the inputs of zero entries all storage elements are connected to the reset input selecting circuit, a first input of j-th element ₁ and with three inputs connected to the j-th input of the circuit ₁ sample selection, the second inputs of all elements AND with three inputs to connect with enabling them the input of the selection circuit, the third inputs of all elements AND with three inputs to connect to the input records of the selection circuit; include the address decoder of the circuit, the decoder of the cell address, nn ₁ + n ₂ + n ₃ addressing schemes, and le (l 1, L) connect the control inputs of all addressing schemes to the l-th control input of the addressing unit, the first and second connect the outputs of the i-th (i 1, n) addressing circuit with the 2i-1st and 2i-m outputs of the block, q _6th (q ₆ 1, log ₂ (n)}) the load input of the addressing block is connected to q ₆ the input of the decoder of the address of the circuit, the i-th output of which is connected to the enable input of the i-th selection circuit, q _7th (q ₇ log ₂ (n)} + 1, log ₂ (n)} + log ₂ (L) } +1), connect the load input of the addressing block with q ₇ - {log ₂ (n)} - m input address decoder cell, l _1-th (l ₁ 1,2L), whose output is connected to ₁ l -th input sample all addressing schemes, a reset input and recording each addressing circuit connected to the reset inputs of the addressing and writing unit, each of the circuit addressing include 2L memory elements, two blocks of OR elements with L inputs each, 2L keys made in the form of AND elements with two inputs, 2L elements AND with three inputs, with direct outputs of the 2l-1st and 2l-th (l = 1 , L) of storage elements, connect to the first inputs of the 2l-1st and 2l keys, the second inputs of the 2l-1st and 2l keys with connect with the l-th control input of the addressing circuit, connect the outputs of all the odd keys with the inputs of the first block of OR elements, connect the outputs of all the even keys with the inputs of the second logical block OR, connect the outputs of the first and second logical blocks OR with the first and second outputs of the addressing circuit, the input recording unit l ₁ (l ₁ 1, 2L) of the storage element to connect with the output l _1- th element And with three inputs, the inputs of the recording of zero of all storage elements to connect to the reset input of the addressing circuit, the first input l _1- th element AND with three inputs s connected to the ₁ l th input sample addressing scheme, all the second inputs of AND gates with three inputs are connected to the enabling input addressing circuit, the third inputs of AND gates with three inputs connected to the input of recording the addressing scheme.

 It is proposed to include an inverter, two AND logic elements with two inputs, an RS-trigger, three OR logical elements with two inputs, a clock generator, a T-trigger, two delay lines, and connect the first and second inputs of the block to the first and the second inputs of the first OR element, connect the third input of the block to the second input of the second And element, the first input of which is connected to the output Q of the RS trigger, the output of the first OR element through the first delay line connect to the first input of the first And element, the third input b lock through an inverter to connect to the second input of the first AND element, the output of the first AND element to connect to the first output of the block and to the first input of the third OR element, the output of the second AND element to the second input of the second OR element, the first input of which to connect to the fourth input of the synchronization block, the output of the second OR element is connected to the fourth output of the block, with the counting input of the T-trigger, with the input R of the RS-trigger and through the second half-cycle delay line with the input S of the RS-trigger, the output of the T-trigger is connected to the third output of the block, connect the fourth block input to the generator start input, connect the generator output to the second block output, connect the fifth block input to the second input of the third OR element, the output of which is connected to the generator stop input.

RS-триггера соединить с вторым входом первого элемента И, первые входы элементов И соединить с тактовым входом ключа, выход первого элемента И соединить с тактовым выходом ключа, выход второго элемента И соединить с управляющим выходом ключа и через линию задержки с входом R RS-триггера.It is proposed to include L keys with one control input, a control output, a clock input and a clock output in the determinant of the order of disjunctions, while the control input of the lth (l 1, L) key is connected to the lth input of the determinant, the control output of the lth connect the key to the control output of the determinant, connect the clock input of the first key to the L + 1st input of the determinant, connect the clock input of the lth key (l 2, L) to the clock output of the l + 1 key, clock output of the L key connect with the signal output of the determinant, in the composition of each of the keys on assign an RS-trigger, two AND elements with two inputs each, a delay line of half a clock cycle, while the control input of the key is connected to the input S of the RS-trigger, the output of the Q RS-trigger is connected to the second input of the second element And, the output

Connect the RS-flip-flop with the second input of the first element AND, connect the first inputs of the elements And with the clock input of the key, the output of the first element And connect with the clock output of the key, the output of the second element And connect with the control output of the key and through the delay line with the input R of the RS-flip-flop .

The structure of the switch block with L + 2 inputs and 2 (L + 1) outputs is proposed to include an inverter and 2 (L + 1) key, made in the form of a logical element And with two inputs, and connect the L + 2-nd input of the block with the first the inputs of all keys with numbers greater than L + 1 and with the input of the inverter, the output of which is connected to the first inputs of all keys with numbers less than or equal to L + 1, l-th (l 1, L, L + 1), connect the input of the block with the second inputs of the lth and L + l + lth keys, the output of the lth key (l = 1,2L + 1, l ₁ ≠ L + 1)) connect to the lth output of the block, the output 2L + 1- key to connect with L + 2nd block output, output 2L + 2nd class ca connected to the L + 1-th output block.

 It is proposed to include L OR elements with two inputs in the OR block with 2L inputs and L outputs, and connect the 2l-1st (l 1, L) block input to the first input of the l-th OR element, 2l-th (l 1 , L) connect the input of the block to the second input of the l-th OR element, the output of which is connected to the l-th output of the block.

It is proposed to perform an OR logical block with L inputs in the form of a p-level (p [log ₂ L]) cascade of OR elements, and, on the first level, arrange [L / 2] elements ([] denotes the integer part of the number), on the qth (q 1, p) level, arrange s (q) OR elements, while s (q + 1) = [s (q) / 2] all but the last OR elements of all levels should have two inputs, the last element of the first level should have two inputs if L is even, and three inputs if L is odd, the last q + 1 level element should have two inputs if s (q) is even, and three inputs if s (q) is odd, 2l ₁ - 2l minutes and ₁ -1-th (l _1, 1, [L / 2]) in ode unit connected to L ₁ th inputs of the OR gate of the first level, if L is odd, then the last input block is connected to a third input of the OR gate of the first level, and outputs 2l _q 2l _q -1-th (l _q 1, [s ( q) / 2] of the elements of the qth level OR connect to the inputs l of the _qth element of q + 1st level, if s (q) is odd, then the output of the last element of the qth level connect with the third input of the last element q + 1 level, connect the output of the last level element to the output of the block.

The logical block AND with N inputs (N L + 1) is proposed to be performed in the form of a p-level (p [log ₂ N] cascade of AND elements, and, on the first level, arrange [N / 2] elements ([denotes the integer part of the number), at the qth (q 1, p) level arrange s (q) of AND elements, while s (q + 1) = [s (q) / 2] all but the last AND elements of all levels should have two inputs, the last the first level element must have two inputs if N is even, and three inputs if N is odd, the last q + 1 level element must have two inputs if s (q) is even, and three inputs if s (q) is odd , 2l 2l ₁ st and ₁ -1-th (l 1, [N / 2] inputs bl Single connected to the inputs 1 and ₁ th element of the first level, if N is odd, then the last block input connected to the third input of the AND gate of the first level, the outputs 2l _q -th and 2l _q -1-th (l 1, [s ( q) / 2]) of the elements of the qth level OR connect to the inputs l of the _qth element of q + 1st level, if s (q) is odd, then connect the output of the last element of the qth level to the third input of the last element q + 1st level, the output of the last level element is connected to the output of the block.

 It is proposed to include an OR logic block with L inputs and an inverter in the OR-E logic block with L inputs, and connect the output of the OR logical block with L inputs to the inverter input, the output of which should be connected to the output of the OR-E block.

and figure 1 shows a functional diagram of a special processor for solving problems on the feasibility of Boolean formulas; figure 2 functional diagram of the processor matrix; figure 3 is a functional diagram of a parallel write and read unit; figure 4 is a functional diagram of a storage cell; figure 5 is a functional diagram of a parallel address decoder with 2n inputs and 2n outputs (n = 2); Fig.6 functional diagram 2 of the ^N- input cascade of elements And; in FIG. 7 is a functional diagram of a control device; on Fig - functional block diagram of the choice of clauses; Fig.9 is a functional diagram of a selection circuit; in FIG. 10 functional diagram of the addressing unit; figure 11 is a functional diagram of an addressing scheme; 12 is a functional diagram of a synchronization unit; in FIG. 13 functional diagram of the determinant of the order of disjunctions; on Fig functional diagram of the key determinant of the order of disjunctions; on Fig functional block diagram of the switches; on Fig is a functional diagram of a block of elements OR control device; on Fig is a functional diagram of a logical block of elements OR; Fig. 18 is a functional diagram of a logical block of AND elements; in FIG. 19 is a functional diagram of a logical block OR-E.

 A highly parallel special processor for solving the problem of the feasibility of Boolean formulas (Fig. 1) consists of a processor matrix 1, control device 2, and interface 3.

 The processor matrix 1 has 2n address inputs 4, input 5 reset and one output 6.

The control device has a trigger input 7, signal input 8, 2 + 2 {log ₂ (L)} + 2 {log ₂ (m)} + {log ₂ (n)} of the input 9 of the download (where x} denotes the smallest integer greater than or equal to x), reset input 10, write input 11, 2n control outputs 12, three solution outputs 13, 14, 15, m read outputs 16 and reset output 17.

In this case, the i-th (i 1,2n) address input 4 _{i of the} processor matrix 1 is connected to the i-th control output 12 _i of the control device 2, the reset input 5 of the processor matrix 1 is connected to the reset output 17 of the control device 2, the output of the processor matrix 6 1 is connected to the signal input 8 of the control device 2.

The start input 7 of the control device 2 is connected to the output 18 of the interface 3, jth (j 1, m) output 16 _{j of the} reader 2 of the control device is connected to the jth input 19 _{j of the} interface 3, pth (p 1,2 +2 {log ₂ (L)} + 2 {log ₂ (m)} + {log ₂ (n)}), the input 9 _{p of the} boot device 2 control is connected to the p-th output 20 _p boot interface 3. Input 10 reset the control device 2 is connected to the output 21 of the reset interface 3, the input 11 of the recording device 2 control is connected to the output 22 of the record interface 3, the first 13, second 14 and third 15 outputs of the solution of the control device 2 are connected to the first 23, second 24 and t etim 25 inputs interface solutions, respectively.

идентичных блоков 26 записи и считывания с

входами 27 адреса строки,

входами 28 адреса столбца, разрешающим входом 29, входом сброса и одним выходом 30;
дешифратор 31 адреса блока с 2n₁ входами и

выходами 32;

-входовый каскад 33 элементов И.The processor matrix 1 (figure 2) contains:

identical blocks 26 write and read with

inputs 27 line addresses,

inputs 28 of the column address, enabling input 29, reset input and one output 30;
a block address decoder 31 with 2n ₁ inputs and

outputs 32;

input stage 33 elements I.

устройства 1 параллельной записи и считывания, k₁-й (k₁ 1,

) выход

дешифратора 31 адреса блока соединен с разрешающим входом 29 k₁-го блока

.Moreover, the i _1st (i ₁ 1,2n ₁ ) input of the decoder 31 of the block address is the i _1st address input

parallel write and read device 1, k ₁ (k ₁ 1,

) exit

the block address decoder 31 is connected to the enable input 29 k of the _1st block

.

адреса строки каждого блока 26 записи и считывания соединен с i₂+2n₁-м адресным входом

устройства 1 параллельной записи и считывания.i _2nd (i ₂ 1,2n ₂ ) input

the address of the line of each block 26 of the write and read connected to i ₂ + 2n _1- m address input

device 1 parallel recording and reading.

каждого блока 26 соединен с i₃+2n₁+2n₂-м адресным входом

устройства параллельной записи и считывания 1.i _3rd (i ₃ 1,2n ₃ ) column address input

each block 26 is connected to i ₃ + 2n ₁ + 2n _2- th address input

parallel write and reader devices 1.

 The reset input of each block 26 is connected to the reset input 5 of the processor matrix 1.

) блока 26 соединен с k₁-м входом

- входового каскада 33 элементов И, выход которого является выходом 6 процессорной матрицы 1.Exit 30 k _1st (k ₁ 1,

) block 26 is connected to the k _1- th input

- input stage 33 elements And, the output of which is the output 6 of the processor matrix 1.

запоминающих ячеек 35;
дешифратор 36 адреса строки с 2n₂ входами 37 и

выходами 38;
дешифратор 39 адреса столбца с 2n₃ входами 40 и

выходами 41;
n₂

-входовых каскадов 42 элементов И

-входовый главный каскад 43 элементов И;
2n₂ ключей 44, выполненных в виде элементов И с двумя входами.Each block 26 recording and reading (figure 3) contains:
the matrix

storage cells 35;
decoder 36 line addresses with 2n ₂ inputs 37 and

outputs 38;
decoder 39 column addresses with 2n ₃ inputs 40 and

outputs 41;
n ₂

-input stages 42 elements AND

-input main cascade of 43 And elements;
2n ₂ keys 44, made in the form of elements AND with two inputs.

) выход

дешифратора 36 адреса строки соединен с первыми входами 45 выборки всех запоминающих ячеек

k₂-й строки матрицы запоминающих ячеек, k₃-й (k₃ 1,

) выход

дешифратора 39 адреса столбца соединен с вторыми входами 46 выборки всех запоминающих ячеек k₃-го столбца матрицы запоминающих ячеек.Moreover, k _2- th (k ₂ 1,

) exit

the decoder 36 of the row address is connected to the first inputs 45 of the sample of all storage cells

k _2nd row of the matrix of storage cells, k _3rd (k ₃ 1,

) exit

the column address decoder 39 is connected to the second inputs 46 of the sample of all storage cells k of the _3rd column of the matrix of storage cells.

соединен с i₂-м входом

адреса строки блока, второй вход каждого ключа 44 соединен с разрешающим входом 29 блока.The first input i _2- th (i ₂ 1,2n ₂ ) key

connected to i _2nd input

block line address, the second input of each key 44 is connected to the enable input 29 of the block.

дешифратора 36 адреса строки соединен с выходом i₂-го ключа

, i₃-й (i₃ 1,2n₃) вход

дешифратора 39 адреса столбца соединен с i₃-м входом

адреса столбца блока.i _2nd (i ₂ = 1,2n ₂ ) input

decoder 36 line address is connected to the output i of the _2nd key

, i _3rd (i ₃ 1,2n ₃ ) input

the column address decoder 39 is connected to the i _3rd input

block column addresses.

k₂-го ряда матрицы запоминающих ячеек соединен с k₃-м входом

k₂-го каскада

элементов И, выход k₂-го каскада

элементов И соединен с k₂-м входом

-входового главного каскада 43 элементов И, выход которого является выходом блока 26 записи и считывания.The reset input 47 of each of the storage cells is connected to the reset input 34 of the write and read unit 26, the output of the _3rd storage cell

k of the _2nd row of the matrix of storage cells is connected to the k of the _3rd input

k _2nd cascade

elements And, output k of the _2nd stage

elements And connected to the k _2nd input

- input main stage 43 AND elements, the output of which is the output of the block 26 recording and reading.

Each storage cell 35 (figure 4) contains:
storage element 50;
logic element AND 51 with two inputs.

 In this case, the first and second inputs of the logic element And 51 are connected to the first 45 and second 46 inputs of the sample of the memory cell 35, the output of the element And is connected to the recording input of the unit of the memory element 50, the input of the zero recording of the memory element 50 is connected to the reset input 47 of the memory cell 35. The direct output of the storage element is the output of the storage cell 35.

The decoders of the addresses of the block, rows and columns (Fig. 5) are made in the form of parallel address decoders having 2 ^N outputs 52 and 2N address inputs 53 (N n ₁ , n ₂ , n ₃ for the decoders of the block, row addresses and column addresses, respectively) , one independent input for zero and for a single value of each binary bit of the address.

каскада (k₁ 1, 2^N-1) соединены с входами элемента И

первого уровня, выходы элементов И

(k₁ 1,2^N-I) I-го уровня соединены с входами элемента И

I+1-го уровня, выход одного элемента И 54_N,1 N-го уровня является выходом 56 всего каскада.2 ^N- input (Fig. 6) (N n ₁ , n ₂ , n ₃ ) cascade of elements And contains 2 ^N -1 elements And 54 with two inputs located at N levels, while on the I-th (I = 1 , N) level there are 2 ^NI elements, inputs

cascade (k ₁ 1, 2 ^N-1 ) connected to the inputs of the element And

first level, outputs of elements AND

(k ₁ 1,2 ^NI ) I-level connected to the inputs of the element And

I + 1 level, the output of one element And 54 _{N, 1} N level is the output 56 of the entire cascade.

The control device 2 contains (Fig.7):
disjunction selection unit 57 with m control inputs 58, reset input 59, write input 60, log ₂ (m)} + {log ₂ (L)} + 1 boot input 61 and L outputs 62;
addressing unit 63 with m control inputs 64, reset input 65, write input 66, log (L)} + {log (n)} + 1 boot input 67 and 2n outputs 68;
m + 1-bit counter 69 cycles modulo 2 ^{m + 1} with m + 1 output 70 and counting input 71;
block of elements And 72 with 2 (m + 1) inputs 73 and output 74;
m + 1-bit register 75 of the last cycle number with m + 1 output 76, log ₂ (m)} boot inputs 77, write input and reset input;
block OR-E 78 with L inputs 79 and output 80;
block 81 switches with L + 2 inputs 82 (l = 1, L), 83, 84 and 2 (L + 1) output 85;
the first 86 and second 87 determinants of the order of disjunctions with L + 1 input 88, L control outputs 89, signal output 90;
a block of 91 OR elements with 2L inputs 92 and L outputs 93;
block 94 synchronization with five inputs 95-99 and four outputs 100-103;
OR element 104 with two inputs.

In this case, the output of the 76th _jth (j 1, m + 1) discharge of the register of the last cycle number 75 is connected to the 2j-1st input 73 of the _2j-1 block of AND elements 72. The output of the 70th _jth discharge of the counter of 69 cycles is connected with 2j-th input 73 _2j block of elements And 72.

 The output of the logical unit AND 72 is connected to the first output 13 of the solution of the control device 2 and to the first input of the OR element 104.

The output 70 _{j of the} jth (j 1, m) discharge of the cycle counter 69 is connected to the jth control input 58 _j of the disjunction selection block 57, the lth (l 1, L) output 62 _{l of} which is connected to the lth input 82 block 81 switches and with the l-th input 79 _l block OR-E 78.

 The output 80 of the block OR-E 78 is connected to the second output 14 of the solution of the device 2 and to the second input of the OR element 104.

the l-th (l 1.L) output 85 _{l of the} block 81 of the switch is connected to the l-th input 88 _{l of the} first determinant 86 of the order of disjunctions. L + l + 1st output 85 _{L + l + 1} of the 81 switch block is connected to the l-th input 88 _{l of the} second determinant 87 of the switches is connected to the L + 1 input 88 _{L + 1 of the} first determinant 87 of the disjunction order. 2L + 2nd output 85 _{2L + 2 of the} block 81 of the switch is connected to L + 1st input 88 of the second determinant 86 of the order of disjunctions.

the lth outputs 89 _{l of the} first 86 and second 87 determinants of the order of disjunctions are connected respectively to the inputs 92 _2l-1 and 92 _{2l of the} block 91 of the OR elements, the lth output 93 _{l of} which is connected to the lth control input 64 _{l of the} block 63 of the addressing 63 , i-th (i 1,2n nn ₁ + n ₂ + n ₃ ) output 68 _{i of} which is connected by the i-th control output 12 _i of the control device 2.

 The signal output 90 of the first clause order determiner 86 is connected to the first input 95 of the synchronization unit 94, the signal output 90 of the second clause order determiner 87 is connected to the second input 96 of the synchronization block 94.

 The third input 97 of the synchronization unit 94 is connected to the signal input 8 of the control device 2.

 The fourth input 98 of the synchronization unit 94 is connected to the input 7 of the start of the control device 2.

 The fifth input 99 of the block 94 synchronization is connected to the output of the logic element OR 104.

 The first output 100 of the synchronization unit 94 is connected to the third output 15 of the solution of the cell address selector 2.

 The second output 101 of the synchronization unit 94 is connected to the L + 1st input 83 of the switch unit 81.

 The third output 102 of the synchronization unit 94 is connected to the L + 2nd input 84 of the switch unit 81.

 The fourth output 103 of the synchronization unit 94 is connected to the counting input 71 of the counter 69 cycles and to the output 17 of the reset device 2 control.

(p₁ 1,log₂(m)}) загрузки регистра 75 номера последнего цикла соединен с p₁-м входом

загрузки устройства 2 выбора адресов ячеек. q₂-й (q₂ 1,log₂(m)}+{log₂(L)+1) вход

загрузки блока 57 выбора дизъюнкций соединен с p₂-м (p₂ q₂ +log₂(m)}) входом

загрузки устройства 2 управления, q₃-й (q₃ 1,log₂(n)}+{log₂(L)}+1) вход

загрузки блока 63 адресации соединен с p₃-м (p₃ q₃+2*{log₂(m)}+{log₂(L)}+1) входом

загрузки устройства 2 выбора адресов ячеек.p _1st entry

(p ₁ 1, log ₂ (m)}) the load register 75 of the last cycle number is connected to the p ₁ input

device boot 2 select cell addresses. q _2nd (q ₂ 1, log ₂ (m)} + {log ₂ (L) +1) input

the boot block 57 disjunction selection is connected to the p _2- th (p ₂ q ₂ + log ₂ (m)}) input

boot control device 2, q _3rd (q ₃ 1, log ₂ (n)} + {log ₂ (L)} + 1) input

load block 63 addressing is connected to the p _3- th (p ₃ q ₃ + 2 * {log ₂ (m)} + {log ₂ (L)} + 1) input

device boot 2 select cell addresses.

 The reset inputs of the disjunction selection block 57, the addressing block 63, the counter 69 cycles and the register 75 of the last cycle number are connected to the reset input 10 of the control device 2.

 The input 60 of the recording block 57 of the choice of disjunction, the input 66 of the recording block 63 of the addressing and the input of the register register 75 of the last cycle number are connected to the input 11 of the recording of the control device 2.

The disjunction selection block 57 (Fig. 8) contains:
m inverters 105;
the decoder 106 addresses the circuit withlog ₂ (L)} inputs 107 and L outputs 108;
a decoder 109 of the cell address with log ₂ (m)} + 1 input 110 and 2m outputs 111;
L selection circuits 112 with 2m control inputs 113, 2m sample inputs 114, enabling input 115, reset input 116, write input 117, and one output.

Moreover, the jth (j 1, m) control input 58 _j of the disjunction selection block 57 is connected to 2j-1 control inputs 113 _{2j-1 of} all selection circuits 112 and to the input of the j-th inverter 105 _j , the output of which is connected to 2j control inputs 113 _{2j of} all selection circuits 112.

The output of the l-th (l 1, L) selection circuit 112 _{l is} connected to the l-th output 62 _l of the disjunction selection block 57.

загрузки блока 57 выбора дизъюнкций соединен с q₄-м входом

дешифратора 106 адреса схемы, l-й выход 108_l которого соединен с разрешающим входом 115 l-й схемы 112_l выбора, q₅-й (q₅ log₂(L)} +1,log₂(m)}+{log₂(L)}+1) вход

загрузки блока 57 выбора дизъюнкций соединен с q₅-{log₂(L)}-м входом

дешифратора 109 адреса ячейки, j-й (j 1,2m) выход 111 которого соединен с j-ми входами 114_j выборки всех схем 112 выбора. Входы сброса 116 и записи 117 каждой схемы 112 выбора соединены с входами сброса 59 и записи 60 блока.q _4th (q ₄ 1, log ₂ (L)}) input

the boot block 57 disjunction selection is connected to q _4th input

decoder 106 of the circuit address, the lth output 108 _{l of} which is connected to the enable input 115 of the lth circuit 112 _{l of} choice, q _5th (q ₅ log ₂ (L)} + 1, log ₂ (m)} + {log ₂ (L)} + 1) input

boot block 57 disjunction selection is connected to q ₅ - {log ₂ (L)} - m input

a decoder 109 of the cell address, the j-th (j 1,2m) output 111 of which is connected to the j-th inputs 114 _{j of the} sample of all selection circuits 112. The reset inputs 116 and records 117 of each selection circuit 112 are connected to the reset inputs 59 and the block record 60.

Each selection circuit 112 (FIG. 9) contains:
2m storage elements 118;
2m elements And 119 with two inputs 120, 121;
2m elements And 122 with three inputs 123, 124, 125;
m elements OR 126 with three inputs 127, 128, 129;
one element IE 130 with two inputs 131, 132;
block of elements And 133 with m + 1 input 134.

In this case, the direct output 135 of the 2j-1st (j = 1, m) memory element 118 _{2j-1 is} connected to the first input of the 127th j-element OR 126 _j , the direct output 135 of the 2j-th memory element 118 _{2j is} connected to the first input 120 2j-1st element And 119 _2j . The inverse output 136 of the 2j-th storage element 118 _{2j is} connected to the first input 120 of the 2j-th element AND 119 _2j .

The second input 121 of the 2j-1st element AND 119 _{2j-1 is} connected to the 2j-1st control input 113 _2j-1 of the selection circuit 112. The second input 121 of the 2jth element AND 119 _{2j is} connected to the 2jth control input 113 _2j of the selection circuit 112.

The outputs of the 2j-1st 119 119 _2j-1 and 2j-th 119 _2j AND elements are connected to the second 128 and third 129 inputs of the j-th OR element 126.

The output of the j-th OR element 126 _{j is} connected to the j-th input 134 _{j of the} logical block AND 133, the output of which is connected to the output of the selection circuit 112.

Direct outputs 135 of the first 118 ₁ and second 118 ₂ storage elements are connected to the first 131 and second 132 inputs of the element IE 130, the output of which is connected to the m + 1-m input of the logical block And 133.

The entry entry of the unit 137 j _{1 st} (j ₁ 1,2 m) of the storage element 118 _{j1 is} connected to the output of the j _{1 st} element AND 122 _j1 . The zero recording inputs 138 of all storage elements 118 are connected to a reset input 116 of a selection circuit 112.

The first input 123 j of the _1st element AND 122 _{j1 is} connected to the j _1st input of the sample 114 _j1 of the selection circuit 112, the second inputs 124 of all the elements AND 122 are connected to the enable input 115 of the selection circuit 112, the third inputs 125 of all the elements AND 122 are connected to the input of the recording 117 of the selection circuit 112.

Block 63 addressing (figure 10) contains:
a decoder 139 of the address of the circuit withlog ₂ (n)} inputs 140 and nn ₁ + n ₂ + n ₃ outputs 141;
a decoder 142 of the address of the cell with log ₂ (L)} + 1 input 143 and 2L outputs 144;
n addressing circuits 145 with L control inputs 146, 2L sample inputs 147, enable input 148, reset input 149, write input 150, and two outputs 151, 152.

Moreover, the l-th (l 1, L) control inputs 146 _{l of} all addressing circuits 145 are connected to the l-th control input 64 _l of the addressing unit 63.

загрузки блока 63 адресации соединен с q₆-м входом

дешифратора 139 адреса схемы, i-й выход 141_i которого соединен с разрешающим входом 148 i-й схемы 145_i адресации. q_q7-й (q₇log₂(n)}+1,log₂(L)}+1) вход

загрузки блока 63 адресации соединен с q₇-{log₂(n)}-м входом

дешифратора 142 адреса ячейки, l₁-й (l₁ 1,21) выход

которого соединен с l₁-ми входами

выборки всех схем 145 адресации. Входы сброса 149 и записи 150 каждой схемы 145 адресации соединены с входами сброса 65 и записи 66 блока 63.The first 151 and second 152 outputs of the ith (i 1, n) addressing circuit 145 are connected to the 2i-1th and 2i-m outputs 68 _2i-1 and 68 _{2i of} block 63, q _6th (q ₆ 1, log ₂ (n)}) input

loading block 63 addressing is connected to q _6th input

the decoder 139 of the address of the circuit, the i-th output 141 _{i of} which is connected to the enable input 148 of the i-th address circuit 145 _i . q _q7th (q ₇ log ₂ (n)} + 1, log ₂ (L)} + 1) input

load block 63 addressing is connected to q ₇ - {log ₂ (n)} - m input

decoder 142 cell addresses, l _1st (l ₁ 1.21) output

which is connected to l ₁ inputs

samples of all addressing schemes 145. The reset inputs 149 and records 150 of each addressing circuit 145 are connected to the reset inputs 65 and records 66 of block 63.

Each addressing circuit 145 (FIG. 11) comprises:
2L of storage elements 153;
two logical blocks OR 154 with L inputs 155 each;
2L keys 156, made in the form of elements And with two inputs 157, 158;
2L elements And 159 with three inputs 160, 161, 162.

In this case, the direct outputs of 163 2l-1st 153 _2l-1 and 2l 153 _2l (l 1, L) storage elements are connected to the first inputs of 157 2l-1st 156 _2l-1 and 2l 156 _2l keys, respectively . The second inputs 158 2l-1st 156 _2l-1 and 2l 156 _2l keys are connected to the l-th control input 146 _l of the addressing circuit 145.

 The outputs of all the odd keys 156 are connected to the inputs 155 of the first logical block OR 154, the outputs of all the even keys 156 are connected to the inputs 155 of the second logical block OR 154. The outputs of the first 154 and second 154 logical blocks OR are connected to the first 151 and second 152 outputs of the addressing circuit 145 .

соединен с выходом i-го элемента И

с тремя входами, входы 165 записи нуля всех запоминающих элементов 153 соединены с входом сброса 149 схемы 145 адресации.Input 164 recording unit l _1- th (l 1,2L) storage element

connected to the output of the i-th element And

with three inputs, the inputs 165 of the recording of zero of all storage elements 153 are connected to the reset input 149 of the addressing circuit 145.

соединен с l₁-м входом выборки

схемы 145 адресации, первые входы 160 всех элементов И 159 соединены с разрешающим входом 148 схемы 145 адресации, третьи входы 162 всех элементов И 159 соединены с входом 150 записи схемы 145 адресации.The second input 161 l of the _1st element AND

connected to l _1st sampling input

addressing circuit 145, first inputs 160 of all AND elements 159 are connected to enable input 148 of addressing circuit 145, third inputs 162 of all AND elements 159 are connected to recording input 150 of addressing circuit 145.

Block 94 synchronization contains (Fig):
inverter 166;
two logical elements And 167, 168 with two inputs 169, 170 and 171, 172 each;
RS trigger 173;
three logical elements OR 174, 175, 176 with two inputs 177, 178; 179, 180 and 181, 182 each;
a clock generator 183 with a start input 184 and a stop input 185;
T-trigger 186 with counting input 187;
two delay lines 188 and 189.

 Moreover, the first 95 and second 96 inputs of block 94 are connected to the first 177 and second 178 inputs of the first OR element 174, the third input 97 is connected to the second input 172 of the second AND element 168, the first input of which 171 is connected to the output Q of the RS flip-flop 173.

 The output of the first element OR 174 through the first delay line 188 is connected to the first input 169 of the first element And 167.

 The third input 97 of block 94 through an inverter 166 is connected to the second input 170 of the first element And 167. The output of the first element And 167 is connected to the first output 100 of block 94 and to the first input 181 of the third element OR 176.

 The output of the second AND element 168 is connected to the second input 180 of the second OR element 175, the first input of which 179 is connected to the fourth input 98 of the synchronization unit 94.

 The output of the second OR element 175 is connected to the fourth output 103 of block 94, with the counting input 187 of the T-flip-flop 186, with the input R of the RS-flip-flop 173 and through the second delay line 189 with the input S of the RS-flip-flop 173.

 The output of the T-trigger 186 is connected to the third output 102 of block 94.

 The fourth input 98 of the block 94 is connected to the input 184 of the start of the generator 183. The output of the generator 183 is connected to the second output 101 of the block 94.

 The fifth input 99 of block 94 is connected to the second input 182 of the third OR element 176, the output of which is connected to the stop input 185 of the generator 183.

 Each of the two determinants of the order of clauses 86, 87 (Fig. 13) contains L keys 190 with a control input 191, a control output 192, a clock input 193 and a clock output 194.

соединен с тактовым выходом 194 l₁-1-го ключа

. Тактовый выход 194 L-го ключа 190 соединен с сигнальным выходом 90 определителя.Moreover, the control input 191 of the l-th (l 1, L) key 190 _{l is} connected to the l-th input 88 _{l of the} determinant. The control output 192 of the l-th key 190 _{l is} connected to the l-th control output 89 _{l of the} determinant. Clock input 193 of the first key 190 is connected to the L + 1-m input 88 _{L + 1} determinant. Clock input 193 l _1st key (l ₁ 2, L)

connected to clock output 194 l ₁ -1st key

. Clock output 194 of the L-th key 190 is connected to the signal output 90 of the determinant.

Each of the keys 190 contains (Fig):
RS flip-flop 195;
two elements And 196, 197 with two inputs 198, 199 and 200, 201, respectively;
a delay line 202 at half the clock cycle.

RS-триггера 195 соединен с вторым входом 199 первого элемента И 196. Первые входы 198 и 200 элементов И 196 и 197 соединены с тактовым входом 193 ключа.Moreover, the key control input 191 is connected to the input S of the RS flip-flop 195. The output Q of the RS flip-flop 195 is connected to the second input 201 of the second element AND 197. The output

The RS flip-flop 195 is connected to the second input 199 of the first AND element 196. The first inputs 198 and 200 of the AND elements 196 and 197 are connected to the key clock input 193.

 The output of the first element And 196 is connected to the clock output 194 of the key. The output of the second element And 197 is connected to the control output 192 of the key and through the delay line 202 with the input R of the RS-flip-flop 195.

The switch block 81 (Fig.15) contains:
inverter 203;
2 (L + 1) key 204, made in the form of a logical element And with two inputs 205, 206.

(l L+2,2L+2) и с входом инвеpтора 203, выход которого соединен с первыми входами 205 всех ключей 204_l (l 1,L+1).In this case, the L + 2nd input 84 of block 81 is connected to the first inputs 205 of all keys

(l L + 2,2L + 2) and with the input of the inverter 203, the output of which is connected to the first inputs 205 of all keys 204 _l (l 1, L + 1).

The l-th input 82 _l (l 1.L) of block 81 is connected to the second inputs 206 of the l-th and L + 1 + l-th keys of 204 _l and 204 _{L + l + 1} .

L + 1st input 83 of block 81 is connected to second inputs 206 of L + 1st and 2L + 2nd keys of 204 _{L + 1} and 204 _{2L + 2} .

(l₂ ≠ 1,2L+1, l L + 1) соединен с l₂ выходом

блока 81.L key output

(l ₂ ≠ 1,2L + 1, l L + 1) connected to l ₂ output

block 81.

The output of L + 1st key 204 _{L + 1 is} connected to 2L + 2nd output 85 of _{2L + 2 of} block 81.

The output of 2L + 2nd key 204 _{2L + 2 is} connected to the L + 1st output 85 _{L + 1 of} block 81.

 Block 91 elements OR (Fig. 16) contains L elements OR 207 with two inputs 208, 209.

In this case, the 2l-1st (l 1, L) input 92 _{2l-1 of the} block 91 is connected to the first input 208 of the l-th element OR 207 _l , the 2l-1st (l 1, L) input 92 _{2l of the} block 91 is connected to the second input 209 of the l-th element OR 207 _2l , the output of which is connected to the l-th output 93 of the block 91.

The OR logical block 154 with L inputs (Fig. 17) is made in the form of a p-level (plog ₂ L} where x} denotes the smallest integer greater than or equal to x) the cascade of OR elements, and, on the first level, [L / 2} OR elements are located ([denotes the integer part of the number), at the qth (q 1, p) level there are s (q) OR elements.

 Moreover, s (q + 1) [s (q) / 2] All but the last, OR elements of all levels have two inputs, the last element of the first level has two inputs if L is even, and three inputs if L is odd . The last element of q + level 1 has two inputs if s (q) is even, and three inputs if s (q) is odd, the 2lth and 2l-1st (l 1, [L / 2]) inputs block are the inputs of the l-th element OR first level. If L is odd, the last block input is the third input of the last OR element of the first level.

 The outputs of the 2nd lth and 2ndlth (l 1, [s (q) / 2]) ORs of the qth level are inputs of the lth element of q + 1st level. If s (q) is odd, the output of the last element of the qth level is the third input of the last element of q + 1th level. The output of the last level element is the output of the block.

The logical block And 133 with NL + 1 inputs (Fig. 18) is made in the form of a level (plog ₂ N} where x} denotes the smallest integer greater than or equal to x) the cascade of elements And, moreover, [N / 2] elements And are located on the first level ([denotes the integer part of the number), at the qth (q 1, p) level there are s (q) elements of I.

 Moreover, s (q + 1) [s (q) / 2] All but the last elements of And at all levels have two inputs, the last element of the first level has two inputs if N is even, and three inputs if N is odd . The last element of q + level 1 has two inputs if s (q) is even, and three inputs if s (q) is odd, the 2lth and 2l-1st (l 1, [N / 2]) inputs block are the inputs of the l-th element OR first level. If N is odd, the last input of the block is the third input of the last OR element of the first level.

 The outputs of the 2nd lth and 2ndlth (l 1, [s (q) / 2]) gates of the qth level are inputs of the lth element of q + 1st level. If s (q) is odd, the output of the last element of the qth level is the third input of the last element of q + 1th level. The output of the last level element is the output of the block.

 Block OR-E 78 with L inputs (Fig.19) contains a block of elements OR 154 with L inputs and an inverter. At the same time, the output of the logical block OR with L inputs is connected to the input of the inverter, the output of which is the output of block 78.

 The work of a special processor. The sequence of solving the problem.

 If the disjunction D is actually independent of the variable z, we say that the variable z is indifferent to the disjunction D.

the collection of a ₁ , a ₂ , a _n values of variables will be called non-fulfilling for some disjunction D if
D (a ₁ , a ₂ , a _n ) 0.

 Obviously, for each disjunction its non-performing set is defined up to the variables indifferent for the given disjunction. In addition, a non-performing set for a set of clauses is equal to a union of non-performing sets for individual clauses of this set. For this reason, it is easier to find non-performing sets than performing ones.

For each disjunction D _j and each variable z _i, we define the function St (D _j , z _i ), which we call the status of the variable x in the disjunction D:
St (D _j , z _i ) 0 if z _i enters D in the form of the literal z _i .

St (D _j , z _i ) 1 if z _i enters D in the form of the literal z _i .

St (D _j , z _i ) = * if z _{i is an} indifferent variable for D.

 Hereinafter * a special symbol, a sign of logical negation.

 Obviously, if we take its status in the disjunction D as the value of each variable (the symbol * means that you can take any value of this variable, either 0 or 1), we get one of the sets that do not perform this function. Those.

D (St (D, z _i ), St (D, z ₂ ), St (D, z _n )) 0
For example, if there are 4 variables z ₁ , z ₂ , z ₃ , z ₄ and the disjunction D has the form: z ₂ + z ₄ , then the variables z ₁ and z ₃ are indifferent to D.

St (D, z ₁ ) *, St (D, z ₂ ) 0, St (D, z ₃ ) *, St (D, z ₄ ) 1
The following sets of variables are executing:
z ₁ 0, z ₂ 0, z ₃ 0, z ₄ 1;
z ₁ 0, z ₂ 0, z ₃ 1; z ₄ 1;
z ₁ 1, z ₂ 0, z ₃ 0, z ₁ 1;
z ₁ 1, z ₂ 0, z ₃ 1, z ₄ 1;
It is easy to see that the number of non-performing sets is 2 ^nr , where r is the number of variables indifferent to the disjunction under consideration.

 In order to optimize the operation of the special processor, various sets of variable values are considered in parallel-sequential fashion. All logical variables appearing in the problem are divided into two types. Subsets of variables of the second type are considered sequentially.

We shall call the work special processor subset at a given fixed cycle b _{j}, j}} corresponding podnaborub Thus, the cycle with a binary number b ₂ b ₁ .b _m +1 corresponds to subset b _1, b _2, b _m values of the variables y _1, y ₂ , y _m . A subset of variables of the first type that is performing on a given cycle is a subset that, together with the current subset of values of variables of the second type, gives a non-performing set of variables.

For each fixed subset b ₁ .b _{m of} values of variables of the second type and for each of the disjunctions under consideration D ₁ , D _l, all subsets of ₁ , a _{n of the} values of variables x ₁ , x _{n of the} first type are considered in parallel, among them non-performing given subset cycle.

 An executing subset of variables of the second type is a subset that, together with at least one subset of the values of variables of the first type, provides a non-performing set of values of variables.

Obviously, a subset of b ₁ , b ₂ , b _{m of} values of the variables y ₁ , y ₂ , y _m will be non-fulfilling for clauses D} if and only if for any j one of two conditions is satisfied:
St (D _l , y _j ) * or St (D _l , y _j ) b _j .

For a given fixed subset b _j } of values of the variables y _j , only those disjunctions D _l for which the subset b _j } is non-fulfilling can influence the solution of the problem of finding non-fulfilling the whole set of clauses of a subset of _i } variables x _i . We will call such clauses valid for a given subset b _j } Accordingly, we can talk about clauses acting on a given cycle.

 In the course of solving the problem for each cycle, the disjunctions acting on it are determined. If none of the clauses is valid, conclude that the current subset of the values of the variables of the second type together with any subset of the values of the variables of the first type gives a solution to the problem. Otherwise, for each active disjunction, successive sets of values of variables of the first type are found.

 Combining non-performing subsets of variables of the first type for all disjunctions acting on a given cycle of the set under consideration, we obtain non-performing subsets of variables of the first type for the entire set of disjunctions. If all subsets of variables of the first type turn out to be non-fulfilling, we proceed to consider the next subset of variables of the second type, i.e. to the next cycle. Otherwise, one of the subsets of variables of the first type is selected that is not non-performing.

 To do this, the current subset of the values of the variables of the second type is fixed and the variables of the first type are divided into two subtypes. Variables of the first subtype are considered in parallel, the second in series. In this case, only disjunctions acting on the last cycle are taken into account. Those. again solve the problem of the feasibility of Boolean formulas, but with fewer disjunctions and variables. The procedure is repeated until the executing set is uniquely determined.

 If after consideration of all subsets of the second type a solution is not found, a conclusion is made that there is no solution.

The special processor works in two modes:
1. Download mode (preparatory) (see the operation of the control device below).

 2. The main mode.

 At the beginning of the main mode operation, the Host machine, through the output 18 of the interface 3, provides a single main mode start pulse to the start input 7 of the control device 2, after which the processor matrix starts operation in the first cycle of the main mode. (In this case, the boot mode is conveniently regarded as a zero cycle of the main mode).

The processor matrix works only in the main mode. It is intended for:
1. The selection of all subsets of variables of the first type that are non-performing on this cycle. Those. together with the current subset of values of variables of the second type, they give a non-performing set of clauses.

 2. Issuance of a control signal in the event that all subsets of values of variables of the first type turned out to be non-fulfilling on this cycle.

где a_j (j 1,n₁+n₂+n₃), принимают значения 0 или 1. При этом, двоичное число a₁,

, называемое первой частью адреса, соответствует номеру блока, в котором находится запоминающая ячейка, двоичное число

, называемое второй частью адреса, соответствует номеру ряда, в котором находится запоминающая ячейка, двоичное число

, называемое третьей частью адреса, соответствует номеру запоминающей ячейки в ряду. Ячейке с адресом

ставят в соответствие поднабор

значений переменных x₁,x_n первого типа. Если D_r дизъюнкция, чей порядковый номер среди действующих на данном цикле дизъюнкций равен l, то на l-м тексте цикла записывают единицы в те ячейки, адреса которых соответствуют невыполняющим дизъюнкцию D_r поднаборам. Разряды адресов этих ячеек соответствуют статусам переменных в дизъюнкции D_r. Если St(x_i, D_r) 1, то i-е разряды адресов ячеек, соответствующих невыполняющим поднаборам, содержат единицы. Если St(x_i, D_r) 0, то i-е разряды адресов ячеек, соответствующих невыполняющим поднаборам, содержат нули. Если St(x_i, D_r) * то i-е разряды адресов ячеек, соответствующих невыполняющим поднаборам, содержат как нули, так и единицы.The address of each storage cell of the processor matrix has the form

where a _j (j 1, n ₁ + n ₂ + n ₃ ), take the values 0 or 1. Moreover, the binary number a ₁ ,

, called the first part of the address, corresponds to the number of the block in which the storage cell is located, a binary number

, called the second part of the address, corresponds to the number of the row in which the storage cell is located, a binary number

, called the third part of the address, corresponds to the number of the storage cell in the row. Cell with address

match a subset

values of variables x ₁ , x _{n of the} first type. If D _{r is a} disjunction whose sequence number among the disjunctions acting on a given cycle is l, then on the l-th text of the cycle, units are written in those cells whose addresses correspond to non-performing disjunction D _r subsets. The address bits of these cells correspond to the statuses of the variables in the disjunction D _r . If St (x _i , D _r ) 1, then the ith bits of the addresses of the cells corresponding to non-performing subsets contain units. If St (x _i , D _r ) 0, then the ith bits of the addresses of the cells corresponding to non-performing subsets contain zeros. If St (x _i , D _r ) * then the ith bits of the addresses of the cells corresponding to non-performing subsets contain both zeros and ones.

 Access to the storage cells of the processor matrix device 1 is provided by parallel address decoders of the addresses of the block, row and column, which allows you to write units simultaneously to all cells corresponding to non-performing subsets. For this, it is necessary to apply control signals to those inputs of parallel decoders that correspond to the desired values of the address bits. (The value 0 of the i-th digit of the address corresponds to the 2i-1th control input of the decoder. The value 1 of the i-th digit of the address corresponds to the 2i-1st control input of the decoder).

At the beginning of the next cycle, a reset signal is received at the reset input 5 of the processor matrix 1, which sets all storage cells 35 of all write and read blocks 26 to zero. and the lth step of the cycle under consideration (where l is the disjunction sequence number D _r among the disjunctions acting on the given cycle), the signals of the address inputs of device 1 are received according to the following rule:
if St (D _r , x _i ) 1, one goes to the input 4 _{2i of the} device 1, and zero goes to the address input 4 _2i-1 ;
if St (D, x) 0, the address input 4 _2i enters zero, and to the address input 4 _2i-1 unit receives;
if St (D, x) *, _one arrives at both address inputs 4 _2i and 4 _2i-1 .

(i_o 1,2n) одновременно. Сигналы с входов

(i₁ 1.2n₁), соответствующих первой части адреса, поступают на входы дешифратора 31 адреса блока.Signals arrive at all inputs.

(i _o 1,2n) at the same time. Input Signals

(i ₁ 1.2n ₁ ) corresponding to the first part of the address are supplied to the inputs of the decoder 31 of the address of the block.

, которые содержат ячейки, соответствующие невыполняющим дизъюнкцию D_r поднаборам значений переменных первого типа. С выходов

дешифратора 31, соответствующих этим блокам, на разрешающие входы 29 блоков 26 поступают единицы.Parallel block address decoder 31 performs parallel decryption of addresses of all those blocks

, which contain cells corresponding to non-performing disjunction D _r subsets of values of variables of the first type. With exits

of the decoder 31 corresponding to these blocks, one arrives at the permitting inputs 29 of the blocks 26.

(i₂ 1,2n₂) устройства 1, соответствующих второй части адреса, поступают параллельно на входы

адреса строки всех блоков 26.Input Signals

(i ₂ 1,2n ₂ ) of the device 1 corresponding to the second part of the address are received in parallel to the inputs

line addresses of all blocks 26.

с номером k₁ (k₁ 1,

) (фиг.3). Если существует хотя бы один невыполняющий поднабор, первая часть адреса которого равна k₁, на разрешающий вход 29 блока

поступает единица, отпирающая все ключи 44. Вследствие этого разряды вторых частей адресов невыполняющих поднаборов поступают на входы

(i₂ 1,2n₂) параллельного дешифратора 36 адреса строки.Consider the operation of the block

with the number k ₁ (k ₁ 1,

) (Fig. 3). If there is at least one non-performing subset, the first part of the address of which is k ₁ , to the block 29 allowing input

a unit arrives that unlocks all the keys 44. As a result of this, the discharges of the second parts of the addresses of non-performing subsets go to the inputs

(i ₂ 1,2n ₂ ) parallel decoder 36 line addresses.

, соответствующих вторым частям адресов невыполняющих поднаборов, единицы поступают на входы 45 тех ячеек 35, которые находятся в рядах, соответствующих невыполняющим поднаборам (фиг.3).After the operation of the decoder 36 from its outputs

corresponding to the second parts of the addresses of non-performing subsets, the units arrive at the inputs of those 45 cells 35, which are in rows corresponding to non-performing subsets (figure 3).

(i₃ 1,2n₃) устройства 1 параллельно поступают на входы

адреса столбца всех блоков 26 параллельной записи и считывания.Input Signals

(i ₃ 1,2n ₃ ) devices 1 in parallel are fed to the inputs

column addresses of all blocks 26 parallel write and read.

параллельного дешифратора 39 адреса столбца.Inside each block, the signals go to the inputs.

parallel decoder 39 column address.

 After the operation of the decoder 39 with its outputs 41, corresponding to the third parts of the addresses of non-performing subsets, the units go to the inputs 46 of the memory cells corresponding to non-performing subsets (Fig. 4).

 As a result, a unit will be recorded in those memory cells 35 in which units are supplied to both inputs 46, 45.

Thus, on the l-th measure, to all memory cells in which units were recorded on the previous measures, cells corresponding to non-performing disjunction D _r sets are added.

(k₂ 1,

) непрерывно подается на вход

каскада элементов И 42, на выходе которого единица появляется только в том случае, если на все входы 48 подаются единицы.The contents of the storage element 50 of each storage cell

(k ₂ 1,

) continuously fed to the input

a cascade of elements AND 42, at the output of which a unit appears only if units are supplied to all inputs 48.

сигнал поступает на k₂-й вход

каскада 43 (фиг.3). Если на все входы 49 подаются единицы, на выходе 30 каскада элементов И 43 появляется 1. С выхода 30 блока

(k₁ 1,

) сигнал поступает на вход

каскада элементов И 33 (фиг.2), на выходе 6 которого единица появляется в случае, если все поднаборы значений переменных первого типа оказались невыполняющими на данном цикле.From the output of the cascade of elements AND

the signal goes to the k _2nd input

cascade 43 (figure 3). If units are supplied to all inputs 49, output 30 of the cascade of elements AND 43 appears 1. From output 30 of the block

(k ₁ 1,

) the signal is input

a cascade of elements And 33 (figure 2), at the output 6 of which the unit appears in the event that all subsets of the values of the variables of the first type were non-performing on this cycle.

The control device is intended for:
1. Definitions in the course of the next cycle of disjunctions acting on the next cycle.

 2. Issuance at each clock cycle of the current cycle of units to those address inputs of the processor matrix 1 that correspond to the values of the bits of the addresses of the cells corresponding to non-performing subsets of the values of the variables of the first type on this clock.

 Interface 3 is intended for communication of the HOST machine with device 2 for selecting cell addresses.

 The operation of the control device in boot mode.

 Before starting the loading of device 2, a reset signal is sent to its reset input 10 through the reset output 21 of interface 3, which then goes to the reset inputs of the disjunction selection block 57, addressing block 63, register 75 of the last cycle number, and counter 69 cycles. As a result, zeros are entered in all memory cells of the disjunction selection block 57, addressing block 63 and register 75, and units are entered in all memory cells of the counter of 69 cycles. Thus, in the counter 69, the number 11.1 appears, which is -1 in the additional code.

After that, the status cells of the variables of the second type in each of the disjunctions are entered into the memory cells of the disjunction selection block 57. In the storage cells of the addressing unit 63, bits of the addresses of the cells corresponding to non-performing sets of variables of the first type are entered for all disjunctions. In the register 75, the numbers of the last cycle are entered in the number of the last working cycle, equal to 2 ^m , where m is the number of variables of the second type considered in the problem.

Data is written to blocks 57 and 63 according to the following rules:
Let L be the number of disjunctions considered in the problem.

For all 1 <= L _o :
If the j-th variable of the second type Y _{j is} not included in the clause D _l , in the 2j-1st memory element 118 _2j-1 of the 1st circuit 112 _{l of the} selection block 57 of the choice of clauses write 1, in the 2j-th memory element 118 _2j 1st circuit 112 _{l of the} selection block 57 disjunction selection do not record anything.

If the j-th variable of the second type Y _j is included in the disjunction D _l in the form of the literal Y _j (without negation), in the 2j-1st memory element 118 _2j-1 of the 1st circuit 112 _{l of the} selection block 57 of the disjunction selection and in 2j the storage element 118 _2j of the 1st circuit 112 _{l of} selecting the block 57 does not record anything.

If the jth variable of the second type y enters the disjunction D in the form of the literal y _j (with negation), nothing is written to the 2j-1st memory element 118 _2j-1 of the 1st circuit 112 _{l of the} selection block 57 of the choice of disjunction, The 2jth storage element 118 _2j of the 1st circuit 112 _{l of} selecting the block 57 is recorded 1.

For all 1> L _o :
In the first and second storage elements 118 ₁ and 118 ₂ of the 1st selection circuit 112 _l of the disjunction selection unit 57, write 1.

 The operation of the control device in the main mode.

The last cycle number register 75 stores the number of the last cycle (number 2 ^m ).

 The counter 69 cycles contains the number of the current cycle, reduced by one.

and the rth cycle processes the subset of the values of the variables y ₁ , y ₂ , y _j corresponding to the number r-2 and prepares for the processing of the subset of the values of the variables y ₁ , y ₂ , y _j corresponding to the number r-1. The hive cycle is considered the boot mode. Since the last m digits of the number -1 in the additional code coincide with the digits of the number 2 ^m -1, the first cycle processes the subset of the values of the variables y ₁ , y ₂ , y _j corresponding to the number 2 ^m -1.

 the number r-1 in the loop counter is bitwise fed to the odd inputs of the AND 72 logic block and to the control inputs 58 of the disjunction selection block 57. and the even inputs of the logical block 72 receive the bits of the register numbers of the last cycle. If the value of the cycle counter coincides with the number of the last cycle at the output of the AND block, which is connected to the first output 13 of the solution of the control device 2, a unit appears, which means that the problem has no solution. Through the OR element 104, the unit also enters the input 99 of the synchronization unit 94 and stops its operation.

and control inputs 62 of block 57, corresponding to disjunctions acting on the r + 1th cycle, appear units, on the other control outputs 62 - zeros. These values are supplied to the inputs 79 of the block 78 OR-E and to the inputs 82 _l (l 1, L) of the block 81 switches. If none of the disjunctions is valid on the r + 1th cycle, at the output of the 80 block OR-E, which is connected to the second output 14 of the solution of the device 2 select cell addresses, a unit appears, meaning that a subset of the values of variables of the second type, corresponding to the contents of the loop counter, together with any subset of the values of the variables of the first type, gives a solution to the problem.

 In this case, through the OR element 104, the unit also enters the input 99 of the synchronization unit 94 and stops its operation.

 The block 81 of the switches can be in two states zero and first, the numbers of which are determined by the values of the signal supplied to the input 84 of the block 81 from the output 102 of the block 94 synchronization.

In the zero state, the l-th (l 1, L) input 82 _{l of} block 81 is connected to the l-th output 85 _l , and through it to the l-th input 88 _{l of the} determinant 86. The input 83 of the block is connected to 2L + 2-nd output 85 _{2L + 2} , and through it with the L + 1st input 88 _{L + 1 of the} determinant 87.

In a single state, the l-th input 82 _{l of} block 81 is connected to the 1 + L + 1-m output 85 _{l + L + 1} , and through it with the l-th input 88 _{l of} determinant 87. The input 83 of the block is connected to L + 1- m output 85 _{L + 1} , and through it with L + 1-m input 88 _{L + 1} determinant 86.

 For definiteness, we assume that on the cycle under consideration the block of switches is in the zero state.

 Then, the first determinant of the order of clauses 86 operates in the load mode, and the second determinant of the order of 87 clauses acts in the operating mode.

and the control inputs 88 _l (l 1, L) of the determinant 86, corresponding to the disjunctions acting on the r + 1-th cycle, units come from the outputs 85 of the block 81, after which the triggers 195 of the keys 190 (Figs. 13, 14) of the determiner 86 enter. units corresponding to disjunctions acting on the r + 1st cycle, units are entered.

 Devices 57, 78, 81, and 86 operate asynchronously.

 The device 87 operates synchronously with the clock pulses coming from block 94. The clock pulses from the output 101 of the synchronization block 94 are fed to the L + 1st input 83 of the switch unit 81, and from there to the clock input 88 of the determiner 87. Each clock pulse passes unhindered through those keys 190, in the trigger of which 195 (Figs. 14, 13) no units are entered, i.e. through those keys that do not correspond to the clauses acting on this cycle. As soon as the clock pulse reaches the key 190, which corresponds to the next disjunction acting on the given cycle, it does not go to the input of the next key, but goes to the output 192 of this key and to the input of the delay line 202. From the input 192 of the key 190, the unit goes to the output 89 of the determinant 87, which corresponds to the next disjunction acting on this cycle.

 From the output of the delay line 202, the pulse delayed by half the clock is fed to the input R of the trigger 195 and writes zero to it. The next clock pulse freely passes through the key 190 and moves to the next key, corresponding to the current clause.

After all the keys 190 corresponding to the current clauses are passed, the clock pulses go to the output 90 of the determinant 87, and from there
to the input 96 of the device 94, signaling that the identifier 87 has finished work.

Thus, if l _r disjunction acts on the rth cycle, then the rth cycle includes l _r machine clocks. If the disjunction D _s is valid on the rth cycle and the order of its action is l _s (l _s ∈1, .... L), then on the l _s tact of the rth cycle on the kth output 89 _{k of the} determinant 87 a unit arrives that, through a block of 91 OR elements, enters the kth control input 64 _k of the addressing block 63, as a result of which block 63 outputs units from outputs 68 corresponding to the bits of cell addresses corresponding to disjunction D _s subsets of the values of variables x ₁ , x ₂ , x _n .

 Until zero is recorded in at least one of the memory cells of the device 2 for parallel recording and reading, zero continues to be received from the output 6 of the device 1 to the signal input 8 of the device 2 and then to the input 97 of the signaling unit 94.

If there are units recorded in all storage cells of device 2 (i.e., if all subsets of values of variables of the first type turned out to be non-fulfilling on this cycle and further work in this cycle does not make sense), from output 6 of device 1 to signal input 8 of device 2 and then, unit 97 enters the input 97 of block 94. If enough time has passed since the start of the cycle so that units are recorded in the triggers 195 of the keys 190 of the determinant 86 corresponding to the disjunctions acting on the r + 1st cycle, block 94 initiates the execution of the next cycle. To do this, he:
1. Issues a single signal from output 103 to the counting input 71 of the counter 69 cycles (after which the counter increases its value by one) and to output 17 of the reset device 2. From output 17, the unit goes to input 5 of the reset device 1, which leads to zeroing its memory cells.

 2. Changes its value of the signal at the output 102 to the opposite, which leads to a change in the opposite state of the block 81 of the switches.

 If after entering 96, the unit signaling that the determinant 87 has finished working, zero continues to arrive at the input 97 of block 94 during the time required to complete the operation of device 1, this means that among the subsets of values of variables of the first type there is at least one that performs. Block 94 provides a single signal to output 100, which then enters output 15 of device 2, and stops operation.

 Block 94 also stops when a unit arrives at input 99.

 The operation of block 94 synchronization.

Upon receipt of a unit at the input 98 of block 94, the clock generator 183 is started, the OR element 175 is triggered, and block 94 starts synchronizing the execution of the first cycle:
The generator 183 provides the output 101 of the block 94 clock pulses.

 From the output of the OR element 175, the unit goes to the input of the T-flip-flop 186, translating it into the opposite state, to the input R of the RS-flip-flop 173, to the input of the delay line 189 and through the output 103 of the block 94 to the counting input of the counter 69, increasing its value by 1 , and to the output 17 of the device 2, and from there to the input 5 of the cleaning device 1.

 When a signal is received at the input R of the RS-flip-flop 173, a zero is entered into the trigger, which then arrives at the input 171 of the And 168 element and locks it.

 Delay line 189 delays the signal for the time required to load the clause determinant. After that, the unit enters the input S of the RS-flip-flop 173. The unit is entered into the trigger, which then enters the input 171 of the And 168 element and unlocks it.

 When a unit arrives at the first 95 or second 96 block inputs, the OR element 174 is triggered and gives a unit to the input of the delay line 188. After the lapse of time required to write the units to the cells of device 1 and to trigger the cascades of And elements of this device, the unit from the output of the delay line 188 arrives at the input 169 of the And 167 element. If at this time the input 97 of the block 94 continues to receive zero, a unit arrives from the output of the inverter 166 to the second input 170 of the And 167 element, the element 167 is triggered and issues units to the output 100 of the device 94 and to the input 181 elements and OR 176. From the output signal of the OR gate 176 to the input 185 of the generator 183. The generator stops Stop 183 also occurs when the unit 99 arrives at the input section 94.

 If the And 168 element is open, then when the unit arrives at the input 97 of the block 94, it is triggered, the unit goes to the input 180 of the OR element 175, as a result of which the block 94 starts synchronizing the execution of the next cycle.

 The operation of the block 57 of the choice of clauses.

From the j-th input 58 _{j of} block 57, the value of the j-th bit of the counter content is supplied to the 2j-i-th inputs 113 _{2j-1 of} all selection circuits 112 and through the inverter 105 _m to the 2j-th inputs 113 _{2j of} all selection circuits 112.

If the j-th variable Y _{j is} not included in the l-th disjunction D _l , the unit recorded in the trigger 118 _2j-1 of the selection circuit 112 _l goes to the input of the OR element 126, at the output of which the unit appears regardless of what value came in inputs 113 _2j-1 and 113 _2j .

If the j-th variable Y _j enters the l-th disjunction D _l , and therefore, the trigger 118 _2j-1 contains zero, then the unit appears at the output of the OR element 126 _j only if it appears at the output of the AND element 119 _2j-1 or AND element 119 _2j , which occurs when the contents of trigger 118 _2j coincide with the value received at input 58 _{j of} block 57. (If the value received at input 58 _j is 1 and the content of trigger 118 _2j is 1, element 119 _{2j-1 is} triggered. If the value received at input 58 _j is 0 and the contents of trigger 118 _2j is 0, element 119 _{2j is} triggered).

A unit at the output of the element And 133 of the selection circuit 112 _l (and, therefore, at the l-th output 62 _{l of the} block 57 of the choice of disjunction) appears if and only if for all j at the outputs of the elements And 126 _j appear units. That is, the variable Y _j either does not belong to the disjunction D, or its value b _j considered in this cycle is included in the set that does not fulfill the disjunction D _l , in other words, when the disjunction D _l is valid on this cycle.

If the disjunction D _l is not considered at all, then (and only in this case) one is written in both triggers 118 ₁ and 118 ₂ . The IE-130 element outputs zero to the input 134 of the AND 133 element, and the unit at the k-th output 62 _l of the clause selection block 57 does not appear in any case.

 The operation of block 63 addressing.

and at the next step of operation of the special processor, the unit goes to the input 64 _l of the addressing unit 63, which corresponds to the disjunction D _l considered at this beat, and from there to the inputs 146 _{l of} all addressing circuits 145. In this case, all the 2nd and 2nd keys are opened 156 _2l-1 and 156 _{2l of} all addressing schemes 145, and the contents of 2l-x and 2l-1-x memory elements 153 _2l-1 and 153 _{2l of} all addressing schemes through blocks of 154 elements OR simultaneously enters the outputs 151, 152 of all addressing schemes and through them to the outputs 68 of the block 63 addressing. AND

Claims (10)

1. High-parallel special processor for solving Boolean formula feasibility problems, consisting of a processor matrix, a control device and an interface, characterized in that the ith (i 1, 2n) address input of the processor matrix is connected to the i-th control output of the control device, input the reset of the processor matrix is connected to the reset output of the control device, the output of the processor matrix is connected to the signal input of the control device, the trigger input of which is connected to the trigger output of the interface, the jth (j 1, m) read output of the control device eniya connected to the j-th reading interface input, the p-th
(p = 1,2 + 2 {log ₂ (L)} + 2 {log ₂ (m)} + {log ₂ (n)} x} indicates the smallest integer greater than or equal to x), the boot input of the control device is connected to pth output of the interface load, the reset input of the control device is connected to the reset output of the interface, the recording input of the control device is connected to the output of the interface record, the first, second and third outputs of the control device solution are connected to the first, second and third inputs of the interface solution, respectively, processor matrix contains

identical write and read blocks, block address decoder,

input cascade of AND elements, with the i _1st (i ₁ 1, 2n ₁ ) input of the block address decoder being the i _1st address input of the processor matrix, k _1st

the output of the block address decoder is connected to the enable input k of the _1st write and read block, the _2nd (i ₂ 1, 2n ₂ ) line address input of each write and read block is connected to the i ₂ + 2n _1st address of the processor matrix , i _3rd (i ₃ 1, 2n ₃ ) the column address input of each write and read block is connected to the i ₃ + 2n ₁ + 2n _2nd address input of the processor matrix, the reset input of each write and read block is connected to the reset input of the processor matrices, output k _1st

the write and read unit is connected to the k _1- th input

-in the input cascade of elements And, the output of which is the output of the processor matrix, with each recording and reading unit contains a matrix

storage cells, row address decoder, column address decoder,

- input cascades of elements AND,

-input main cascade of AND elements, 2n ₂ keys made in the form of AND elements with two inputs, with k ₂

the output of the address decoder of the row is connected to the first inputs of the sample of all storage cells k the _2nd row of the matrix of storage cells, k the _3rd

output a column address decoder connected to the second inputs of all the sample storage cells ₃ k -th column of memory cells, a first input ₂ i -th (i _{February 1,} 2n ₂₎ key is ₂ i-th input line write and read address block, the second the input of each key is connected to the enable input of the write and read unit, i _2nd (i ₂ 1, 2n ₂ ) input of the line address decoder is connected to the output of i _2nd key, i _3rd (i ₃ 1, 2n ₃ ) input the column address decoder is connected to the i _3rd input of the column address of the write and read unit, the reset input of each of the memory cells of the connection is connected with the reset input of the write and read unit, the output of the k _3rd storage cell of the k _2nd row of the matrix of storage cells is connected to the k _3rd input of the k _2nd cascade of elements AND, the output of the k _2nd cascade of elements AND is connected to k _2nd entrance

input main cascade of elements AND, the output of which is the output of the recording and reading unit, each memory cell contains a memory element and element And with two inputs, the first and second inputs of the element And connected to the first and second inputs of the sample memory cell, the output of the element And connected to the recording input of the unit of the storage element, the input of recording the zero of the storage element is connected to the reset input of the storage cell, the direct output of the storage element is the output of the storage cell, the decoding the block address, row and column addressators are made in the form of parallel address decoders having 2 ^N outputs and 2N address inputs (N n ₁ , n ₂ , n ₃ ) for block decoders, row addresses and column addresses, respectively), one independent input for zero and for a single value of each binary digit of the address, 2 ^N- input (N n ₁ , n ₂ , n ₃ ) cascade of elements And contains 2 ^N 1 elements And with two inputs located at N levels, while on the I-th I 1, N) level there are 2 ^{N - 1} elements, the inputs of the cascade with numbers 2k ₁ 1 and 2k ₁ (k ₁ 1, 2 ^{N - 1} ) are connected to the inputs of the element that And with the number k _{1 of the} first level, the outputs of the elements And with the numbers 2k ₁ 1 and 2k ₁ (k ₁ 1, 2 ^{N - 1} ) of the 1st level are connected to the inputs of the element And the number k ₁ I + 1 of the level, output element And the N-th level is the output of the whole cascade, the control device contains a block for selecting disjunctions, an addressing block, m + 1-bit cycle counter modulo 2 ^{m + 1} , a block of elements And, m + 1-bit register of the last cycle number, block OR NOT, switch block, first and second clause order determinants, OR element block, synchronization block, OR element with two inputs, and you the jth (j 1, m + 1) discharge stroke of the register of the last cycle number is connected to the (2j 1) th input of the And block of elements, the output of the jth bit of the cycle counter is connected to the 2jth input of the And block of elements, the output of the block of elements And it is connected to the first output of the solution of the control device and to the first input of the OR element, the output of the jth (j 1, m) discharge of the cycle counter is connected to the jth control input of the disjunction selection block, the lth (l = 1, L) output which is connected to the lth input of the switch block and to the lth input of the OR-NOT block, the output of the OR-NOT block is connected to the second output of the control device and with the second input of the OR element, the lth output of the switch block is connected to the lth input of the first clause order determinant, L + l + the 1st output of the switch block is connected to the lth input of the second clause order determinant, L + 1- the 1st output of the switch block is connected to the L + 1st input of the first clause order determinant, 2L + the 2nd output of the switch block is connected to the L + 1st input of the second clause order determinant, the lth outputs of the first and second clause order determinant with (2l-1) -m and 2l-m inputs of the block of elements OR, l- whose output is connected to the l-th control input of the addressing unit, the i-th (i 1, 2n, nn ₁ + n ₂ + n ₃ ) control output of which is connected to the i-th control output of the control device, the signal output of the first disjunction order determinant connected to the first input of the synchronization unit, the signal output of the second determinant of the order of disjunctions is connected to the second input of the synchronization unit, the third input of the synchronization unit is connected to the signal input of the control device, the fourth input of the synchronization unit is connected to the start input of the control unit phenomena, the fifth input of the synchronization block is connected to the output of the OR element, the first output of the synchronization block is connected to the third output of the control device solution, the second output of the synchronization block is connected to the L + 1-m input of the switch block, the third output of the synchronization block is connected to L + 2-m the input of the switch block, the fourth output of the synchronization block is connected to the counting input of the cycle counter and to the reset output of the control device, p _1st input (p ₁ 1, log ₂ (m)}) loading register of the last cycle number is connected to p ₁ device downloads Control-keeping, q ₂ th (q = 1, _2, log ₂ (m)} + {log ₂ (L)} + 1) load input selection unit disjunctions connected to a p th ₂ (p ₂ = q ₂ + {log ₂ (m)}) the boot input of the control device q _3rd (q ₃ = 1, log ₂ (n)} + {log ₂ (L)} + 1 the boot input of the addressing unit is connected to p ₃ (p ₃ = q ₃ + 2 • {log ₂ (m)} + {log ₂ (L)} + 1) the boot input of the control device, the reset inputs of the disjunction selection block, addressing unit, cycle counter and register of the last cycle number are connected to the reset input of the control device , the recording inputs of the clause selection block, the addressing block and the register of the last cycle number are connected to the input records of the control device, while the disjunction selection block contains m inverters, a circuit address decoder, a cell address decoder and L selection circuits, and the j-th (j 1, m) control input of the disjunction selection block is connected to 2j 1-control inputs of all circuits selection and with the input of the j-th inverter, the output of which is connected to the 2j-th control inputs of all the selection circuits, the output of the l-th (l = 1, L) selection circuit is connected to the l-th output of the disjunction selection block, q _4th ( _4, q = 1, log ₂ (L)}) boot block selection input connected to disjunctions q ₄ th input address decoder circuit, l-th output to orogo connected to the enabling input l-th selection circuit, q _{is 5-th} (q ₅ = log ₂ (L)} + 1log ₂ (m)} + {log ₂ (L)} + 1) boot block selection input connected to disjunctions q ₅ - / log ₂ (L) / - th input cell address decoder, j ₁ th (j _1, 1, 2m) whose output is connected to ₁ j -th sample inputs of all the selection circuits, and the reset inputs of each entry selection circuit connected with reset and record inputs of a disjunction selection block, each selection circuit contains 2m memory elements, 2m AND elements with two inputs, 2m AND elements with three inputs, m OR elements with three inputs, AND-NOT element, block of AND elements, n why in each selection circuit, the direct output of the 2j 1st (j 1, m) storage element is connected to the first input of the jth OR element, the direct output of the 2j 1st storage element is connected to the first input of the (2j 1) th AND element with two inputs, the inverse output of the 2j-th storage element is connected to the first input of the 2j-th element And with two inputs, the second input 2j of the 1st element And with two inputs is connected to the (2j 1) -th control input of the selection circuit, the second input 2j- of the And element with two inputs is connected to the 2j-th control input of the selection circuit, the outputs of the (2j 1) and 2j-th And element with two inputs are connected to the second and third inputs of the jth OR element, the output of the jth OR element is connected to the jth input of the AND block, the output of which is connected to the output of the selection circuit, the direct outputs of the first and second storage elements are connected to the first and second inputs element AND NOT, the output of which is connected to the (m + 1) -th input of the block of AND elements, the input of the recording unit j _{1 of the 1st} (j ₁ 1, 2m) storage element is connected to the output j of the _1st element AND with three inputs, recording all zero inputs of storage elements coupled to the reset input selection circuit, the first input ₁ -r j AND gate with three inputs connected to a j ₁ th input sample selection circuit, the second inputs of AND gates with three inputs are connected to the enabling input selection circuit, the third inputs of AND gates with three inputs are connected to the input record selection circuit, the addressing unit comprises a decoder address of the circuit, decoder of the cell address, nn ₁ + n ₂ + n ₃ addressing schemes, and the l-th (l = 1, L) control inputs of all addressing schemes are connected to the l-th control input of the addressing block, the first and second outputs i- the th (i 1, n) addressing schemes are connected to the (2i 1) -th and 2i-th outputs of the block, q _6th (q ₆ 1, log ₂ (n)}) the load input of the addressing unit is connected to the q _6th input of the circuit address decoder, the i-th output of which is connected to the enable input of the i-th selection circuit, q _7th (q ₇ = log ₂ ( n)} + 1log ₂ (n)} + {log ₂ (L)} + 1) the load input of the addressing unit is connected to q ₇ - / log ₂ (n) / - m input of the cell address decoder, l _1st (l ₁ = 1,2L) whose output is connected with ₁ l -th input sample all addressing schemes, the reset inputs of each recording and addressing circuit coupled to the reset inputs of the addressing block and writing, each addressing scheme includes a 2L storage elements, two elements of the group OR with L input each, 2L keys made in the form of AND elements with two inputs, 2L elements AND with three inputs, and the direct outputs of the 2l-1st and 2l (l = 1, L) storage elements are connected to the first inputs (2l- 1) of the 2nd and 2nd keys, the second inputs of the (2l-1) and 2nd keys are connected to the l-th control input of the addressing circuit, the outputs of all odd keys are connected to the inputs of the first block of OR elements, the outputs of all even keys connected to the inputs of the second block of OR elements, the outputs of the first and second blocks of OR elements connected to the first and second outputs of the addressing circuit, recording unit stroke l ₁ -th (l ₁ = 1,2L) storage element connected to the output l -th element ₁ and with three inputs, the inputs of zero entries all storage elements are connected to the reset input of the addressing circuit, a first input of ₁ l th element And with three inputs it is connected to the l _1st input of the addressing circuit sample, the second inputs of all elements And with three inputs are connected to the allowing input of the addressing circuit, the third inputs of all elements And with three inputs are connected to the recording input of the addressing circuit.  2. The special processor according to claim 1, characterized in that the synchronization unit contains an inverter, two AND elements, an RS-trigger, three OR elements, a clock generator, a T-trigger, two delay lines, the first and second inputs of the unit being connected to the first and the second inputs of the first OR element, the third input of the block is connected to the second input of the second And element, the first input of which is connected to the Q-output of the RS-trigger, the output of the first OR element through the first delay line is connected to the first input of the first And element, the third input of the block is the inverter is connected to the second the input of the first AND element, the output of the first AND element is the first output of the block and connected to the first input of the third OR element, the output of the second AND element is connected to the second input of the second OR element, the first input of which is the fourth input of the synchronization block, the output of the second OR element is connected to the fourth the output of the block, with the counting input of the T-trigger, with the R-input of the RS-trigger and through the second delay line with the S-input of the RS-trigger, the output of the T-trigger is the third output of the block, the fourth input of the block is connected to the start input of the generator a, the output of the generator is connected to the second output of the block, the fifth input of the block is connected to the second input of the third OR element, the output of which is connected to the stop input of the generator. 3. The special processor according to claim 1, characterized in that the determinant of the disjunction order contains L keys, while the control input of the lth (l = 1,2L) key is connected to the lth input of the determinant, the control output of the lth key is connected to the control output of the determinant, the clock input of the first key is connected to the L + 1st input of the determinant, the clock input of the l-th key (l = 2, L) is connected to the clock output of the L-1st key, the clock output of the L-key is connected to the signal output of the determinant, and each of the keys contains an RS-trigger, two And elements, a delay line half the machine act, with the control key input coupled to an S-input of RS-flip-flop, Q-output RS-flip-flop is connected to the second input of the second AND gate,

the output of the RS-trigger is connected to the second input of the first element And, the first inputs of the elements And are connected to the clock input of the key, the output of the first element And is connected to the clock output of the key, the output of the second element And is connected to the control output of the key and through the delay line with the R-input RS -trigger. 4. The special processor according to claim 1, characterized in that the block of switches contains an inverter and 2 (L + 1) keys, moreover, the L + 2nd input of the block is connected to the first inputs of all keys with numbers greater than L + 1 and with the input of the inverter , the output of which is connected to the first inputs of all keys with numbers less than or equal to L + 1, l-th (l = 1, L, L + 1), the input of the block is connected to the second inputs of l-th and (l + 1) - key, the output of the l _1st key (l ₁ = 1,2L + 1, l ₁ ≠ L + 1) is connected to the l _1st output of the block, the output of the L + 1st key is connected to (2L + 2) - m block output, the output 2L + of the 2nd key is connected to the L + 1st output of the block.  5. The special processor according to claim 1, characterized in that the block of OR elements contains L OR elements, and the 2l-1st (l = 1, L) input of the block is connected to the first input of the lth OR element, 2lth (l = 1, L) the input of the block is connected to the second input of the l-th OR element, the output of which is the l-th output of the block. 6. The special processor according to claim 1, characterized in that the group of OR elements with L-inputs is made in the addressing scheme in the form of a p-level p = [log ₂ L] cascade of OR elements, the first level containing L / 2 OR elements ([ ] denotes the integer part of the number), the qth (q 1, p) level contains S (q) OR elements, with S (q + 1) [S (q) / 2] 2l _1st and (2l ₁ - 1) -th (l ₁ = 1, [L / 2]) the inputs of the group are the inputs of the _1st element OR of the first level, with L odd the last input of the group is the third input of the last OR element of the first level, outputs 2l _q- th and The (2l _q 1) th (l _q 1, [S (q) / 2]) elements of the OR level q is are the inputs of the lth _q element OR q + of the 1st level, for S (q) the odd output of the last OR element of the qth level is the third input of the last OR of q + 1st level, the output of the last level OR element is the output of the group . 7. The special processor according to claim 1, characterized in that the block of AND elements with N (N = L + 1) inputs is made in the form of a p-level (p [log ₂ N]) cascade of And elements, and the first level contains [N / 2] elements of AND ([] denotes the integer part of the number), the qth (q 1, p) level contains S (q) of AND elements, while S (q + 1) [S (q) / 2] 2l ₁ - the th and (2l ₁ 1) th (l ₁ 1, [N / 2]) inputs of the block are the inputs of the l _1st element of the first level, with N odd the last input of the block is the third input of the last element of the first level, outputs 2l _q- th and (2l _q 1) -th (l _q 1, [S (q) / 2]) elements of the q-th level are inputs of the l _q- th element of And (q + 1) level, with S (q) the odd output of the last AND element of the qth level is the third input of the last AND element of the (q + 1) level, the output of the And element of the last level is the output of the block. 8. The special processor according to claim 1, characterized in that the storage element is made in the form of an RS flip-flop, the S-input of which is the input recording unit of the element, the R-input is the input of the recording zero, Q-input is the direct output of the element,

input by inverse output of the element. 9. The special processor according to claim 1, characterized in that the reset input of the (m + 1) -th bit cycle counter modulo 2 ^{m + 1 is} connected to the recording entries of the unit of all counter registers. 10. The special processor according to claim 1, characterized in that the (m + 1) -bit register of the last cycle number contains a decoder with log ₂ (m)} inputs (where} denotes the smallest integer greater than or equal to x) and m outputs, with p- the th (plog ₂ (m)} decoder input is connected to the pth input of the register load, and the jth (j 1, m) decoder output is connected to the recording input of the jth bit of the register.

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