CN217213701U

CN217213701U - Circuit for multi-clock switching, FPGA and electronic equipment

Info

Publication number: CN217213701U
Application number: CN202220537243.9U
Authority: CN
Inventors: 黄金煌
Original assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Current assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date: 2022-03-11
Filing date: 2022-03-11
Publication date: 2022-08-16
Anticipated expiration: 2032-03-11

Abstract

The application relates to the technical field of integrated circuits, and discloses a circuit for switching multiple clocks, which comprises: n clock sources configured to generate N clock signals; n clock circuits, wherein the ith clock signal is input into the ith clock circuit, i is 0, …, N-1; an OR gate having N input terminals, wherein the ith input terminal is connected to the output terminal of the ith clock circuit; and the output end of the OR gate is used as the output end of the circuit to output one path of clock signal in the N clock sources. The utility model discloses an input as the OR gate of a plurality of clock sources, and the clock circuit corresponding with the clock source has to the circuit that many clocks that output clock signal relates switched, circuit structure is simple, and the rear end is realized not having the obstacle. And no other logic is additionally arranged, so that the logic is simple and the circuit area is small. Therefore, the complexity of the multi-clock circuit is effectively reduced, and the applicability of the multi-clock switching circuit is improved. The application also discloses an FPGA and an electronic device.

Description

Circuit for multi-clock switching, FPGA and electronic equipment

Technical Field

The present application relates to the Field of integrated circuit technology, and for example, to a circuit for multi-clock switching, an FPGA (Field Programmable Gate Array), and an electronic device.

Background

The clock design is a core module of the high-speed circuit design, and the quality of the clock circuit design directly influences whether the chip can safely and reliably run. The conventional clock switching circuit may cause glitches on the output clock due to the clock switching signal not being synchronized with all the input clocks, and the glitches on the output clock may cause functional errors of the subsequent circuits.

At present, in order to avoid the clock from causing glitch at the output, the related art discloses a switching circuit supporting multiple clocks, including: the device comprises a register, an AND gate, a first selector, a register group, a decoding circuit, a multi-clock interlocking circuit and a clock selector; the register samples the input according to the system clock clk _ sys; the input clock switching request clk _ s _ req is connected to the D end of the register and one input end of the AND gate; the output of the Q end of the register is inverted and then connected with the other input end of the AND gate; the input system clock clk _ sys is respectively connected to the clk ends of the register and the register group; n input clock inputs are connected to a glitch-free clock management circuit in the multi-clock interlocking circuit, wherein N is a positive integer; the input asynchronous reset signal is connected to all the reset ends of the registers in the circuit; the input clock selection signal clk _ sel is input to one input terminal of the first selector; the output end of the AND gate is connected to the control end of the first selector; the output end of the first selector is connected with the D end of the register group, and the Q end of the register group is respectively connected with the other input end of the first selector and the input end of the decoding circuit; the N-bit decoding result clk _ pre _ en output by the decoding circuit is transmitted to the multi-channel clock interlocking circuit of the multi-channel clock interlocking circuit, and the N-bit clock signal, the monitoring result CR and the N-bit turn-off flag signal clk _ gate _ s are output to the clock selector according to the N-channel clock input and the N-bit decoding result; when the monitoring result CR is at a high level, the clock selector gates a clock corresponding to only one high-level bit in the N-bit off flag signal CLK _ gate _ s to the clock output CLK _ O of the circuit according to the one-to-one correspondence between the N-bit off flag signal CLK _ gate _ s and the N-bit clock signal.

In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:

in the multi-clock switching circuit related in the prior art, multi-clock switching is required to be completed through a denoising circuit, a plurality of groups of registers, a plurality of groups of comparators, a plurality of groups of selectors and a multi-clock interlocking circuit. The circuit area of the prior art is large, the circuit structure is complex, and the applicability of the multi-clock switching circuit is reduced.

SUMMERY OF THE UTILITY MODEL

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview nor is intended to identify key/critical elements or to delineate the scope of such embodiments but rather as a prelude to the more detailed description that is presented later.

The embodiment of the disclosure provides a circuit, an FPGA and an electronic device for multi-clock switching, so as to reduce the complexity of a multi-clock circuit.

In some embodiments, the circuit for multi-clock switching comprises:

n clock sources configured to generate N clock signals;

n clock circuits, wherein the ith clock signal is input into the ith clock circuit, i is 0, …, N-1;

an OR gate having N input terminals, wherein the ith input terminal is connected to the output terminal of the ith clock circuit; the output end of the OR gate is used as the output end of the circuit and outputs one path of clock signal in the N clock sources;

wherein, the ith clock circuit comprises:

an input AND gate having N input terminals;

the input end of the register group is connected with the output end of the input AND gate, the ith path of clock signal is used as the clock signal of the register group, and the negation output end of the register group is connected with the ith input end of the input AND gate of the clock circuit except the ith path;

the output AND gate is provided with two input ends, wherein one input end is connected with the output end of the register group, and the other input end is connected with the ith clock signal; the output end of the output AND gate is used as the output end of the ith clock circuit;

the register set includes two or more registers in cascade.

Optionally, the register set includes:

the signal input end of the first-stage register is connected with the output end of the input AND gate, and the clock input end of the first-stage register is connected with the ith clock signal;

the signal input end of the last stage register is connected with the output end of the first stage register, and the clock input end of the last stage register is connected with the ith clock signal; the output end of the last stage register is used as the output end of the register group.

Optionally, the last stage register performs falling edge sampling on the ith clock signal.

Optionally, the ith input end of the input and gate is connected to the corresponding clock selection signal, and the value of the ith input signal corresponding to the input and gate is determined according to the clock selection signal.

Optionally, the clock selection signal is a clock selection signal in the form of a one-hot code.

Optionally, the reset end of the register group is connected to the total reset signal.

In some embodiments, the FPGA comprises:

such as the circuit for multi-clock switching described above.

In some embodiments, the electronic device comprises:

such as an FPGA as described above.

The circuit, the FPGA and the electronic equipment for multi-clock switching provided by the embodiment of the disclosure can realize the following technical effects:

the utility model discloses an input as the OR gate of a plurality of clock sources, and the clock circuit corresponding with the clock source has to the circuit that many clocks that output clock signal relates switched, circuit structure is simple, and the rear end is realized not having the obstacle. And no other logic is additionally arranged, so that the logic is simple and the circuit area is small. Therefore, the complexity of the multi-clock circuit is effectively reduced, and the applicability of the multi-clock switching circuit is improved.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:

FIG. 1 is a schematic diagram of a circuit for multi-clock switching provided by an embodiment of the present disclosure;

FIG. 2 is a diagram of another register set for multi-clock switching according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of another circuit for multi-clock switching provided by an embodiment of the present disclosure;

fig. 4 is a schematic diagram of the input and output of a circuit for multi-clock switching according to an embodiment of the present disclosure.

Detailed Description

So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.

The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged as appropriate for the embodiments of the disclosure described herein. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.

The term "plurality" means two or more unless otherwise specified.

In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.

The term "correspond" may refer to an association or binding relationship, and a corresponds to B refers to an association or binding relationship between a and B.

Referring to fig. 1, a circuit for multi-clock switching according to an embodiment of the present disclosure includes:

n clock sources configured to generate N clock signals;

an OR gate having N input terminals, wherein the ith input terminal is connected to the output terminal of the ith clock circuit; and the output end of the OR gate is used as the output end of the circuit to output one path of clock signal in the N clock sources.

In the technical scheme, the clock source is communicated with each clock circuit, and the ith clock signal generated by the ith clock source is input into the i clock circuits. The or gate 104 serves as an output unit of the circuit for multi-clock switching in the present embodiment, and a plurality of input terminals of the or gate 104 are respectively communicated with output terminals of the corresponding clock circuits. It should be understood that, in the embodiment of the present disclosure, the or gate is used as the output end of the circuit, and one of the output N clock sources may be understood as that the output clock signal takes 1 in the logical or operation, and the clock signals output by the other circuits take 0 in the logical or operation except the output clock signal, that is, the output of multiple clock signals is realized by performing the logical or operation on the or gate 104 through each clock circuit. In the embodiment of the present disclosure, the number of or gates 104 is not particularly limited as long as it can be used to determine the clock signal by a logical or operation.

An input and gate 101 having N input terminals;

the input end of the register group 102 is connected with the output end of the input AND gate, the ith path of clock signal is used as the clock signal of the register group, and the negation output end of the register group is connected with the ith input end of the input AND gate of other clock circuits;

an output and gate 103 having two input terminals, wherein one input terminal is connected to the output terminal of the register set, and the other input terminal is connected to the ith clock signal; and the output end of the output AND gate is used as the output end of the ith clock circuit.

Alternatively, a plurality of input terminals of the input and gate 101 are respectively connected to corresponding clock selection signals. Wherein the clock select signal is used to select the type of clock signal corresponding to the ith input terminal of the input and gate 101. The types of the clock signals comprise an inverted output end signal and a clock selection signal of the register group.

In this technical solution, inputting a clock signal corresponding to the ith input terminal of the and gate 101 includes: the ith inverted clock signal and the ith clock signal output by the inverted output end of the register group. When the circuit is not switched to the ith clock circuit, the clock signal corresponding to the ith input end of the input and gate 101 is the ith inverted clock signal output by the inverted output end of the register group. When the circuit is switched to the ith clock circuit, the clock signal corresponding to the ith input terminal of the input and gate 101 is the ith clock signal. It should be understood that, the ith inverted clock signal output from the inverted output terminal of the register set is represented by — "i" in the figure, and can be understood as performing a logical not operation with the ith clock signal. That is, when the ith clock signal takes 1 in the logic operation, the ith inverted clock signal output from the inverted output terminal of the register group takes 0.

In practical applications, when the ith clock signal is selected or the clock circuit is switched to the ith clock signal, the type of the clock signal input to the ith input terminal of the and gate 101 is the ith clock signal. When the clock signal of the ith path is not selected or the clock circuit is not switched to the ith path, the type of the clock signal corresponding to the ith input end of the input and gate 101 is the ith inverted clock signal.

In practical application, the 1 st path is switched to the N-1 st path, the clock signal corresponding to the 1 st input end of the 1 st path input AND gate 101 is switched from 1 to 0, and the clock signal corresponding to the N-1 st input end of the N-1 st path input AND gate 101 is switched from 0 to 1.

In this embodiment, two input terminals of the output and gate 103 are respectively connected to the ith clock signal and the output terminal of the register set 102. It should be understood that the output signal of the register set 102 is determined according to the output result of the input and gate 101 and the ith clock signal, and the output signal of the register set 102 can be understood as an enable signal, wherein the enable signal of the ith clock signal includes the state of the clock signal corresponding to the ith clock signal. And only at most one path of enabling signals with the clock signal state of 1 exist in the N paths of clock circuits. That is, the output and gate 103 performs a logical and operation on the ith clock signal and the enable signal of the ith clock, and the ith clock signal determined by the enable signal is used as the output signal of the ith clock circuit.

The register group includes: two or more cascaded registers.

In the embodiment of the present disclosure, two or more cascaded registers may be D flip-flops or other types of flip-flops, which are not specifically limited in this application, as long as the cascaded registers can be used for reflecting storage units that can only act when triggered by a clock signal, and change an output state according to an input signal. It should be understood that, for the convenience of understanding, the D flip-flop is used in the following embodiments for description.

Optionally, the register group is at least three cascaded registers.

In the disclosed embodiment, three cascaded registers, register 102-1, register 102-2, and register 102-3, are shown in FIG. 1 for ease of illustration. Register 102-1 and register 102-2 may be understood as first-stage registers, register 102-3 may be understood as the last-stage register, and the output of register 102-3 serves as the output of the register bank. In the first stage of registers, the inputs of registers 102-1 and 102-2 may be in an asynchronous relationship with the clock signal. When the input signal encounters the edge jump of the clock signal, the input signal will be in a metastable state. The meta-stable state can cause the clock switching circuit to hang up and fail to operate at all except for reset. By cascading the register 102-1 with the register 102-2, the clock signal can be normalized to a clock domain, and the input signal is prevented from generating a metastable state. In the first stage register, if the input clocks are the same source clocks and have a definite phase with each other. The output clock after the clock switching and the two-frequency division clock of the output clock have the same direction function.

Optionally, the register group is at least two cascaded registers.

In the disclosed embodiment, it is understood for convenience of description that only the register 102-1 and the register 102-3 exist, i.e., the register 102-1 is cascaded with the register 102-3. Register 102-1 serves as the first stage register, register 102-3 serves as the last stage register, and the output of register 102-3 serves as the output of the register bank. By normalizing the clock signal to a clock domain by the register 102-1, signal metastability is avoided. Compared with the first-level register composed of the register 102-1 and the register 102-2, the clock switching speed can be improved due to the fact that the data transmission process between the registers is reduced.

By adopting the register set switched by multiple clocks provided by the embodiment of the disclosure, the metastable state of the input signal can be effectively avoided. And there are many embodiments, and different embodiments can bring about the effects including increasing the clock switching speed and generating the clock signal having the same direction as the two-division clock.

Referring to fig. 2, another register set for multi-clock switching provided by the disclosed embodiments includes:

a signal input end of the first-stage register 201 is connected with an output end of the input AND gate, and a clock input end of the first-stage register is connected with an ith clock signal;

a signal input end of the last-stage register 202 is connected with an output end of the first-stage register, and a clock input end of the last-stage register is connected with an ith clock signal; the output end of the last stage register is used as the output end of the register group.

In the disclosed embodiment, it should be understood that the output of the last stage register 202 also includes an inverting output. And the signal of the negation output end is used as the negation output end of the register group and is connected with the ith input end of the input AND gate of the clock circuit except the ith path. The output end of the last stage register is used as the output end of the register group to output the enable signal of the ith clock signal, namely, the enable signal of the ith clock signal is used as the output end signal of the register group.

Optionally, the last stage register performs falling edge sampling on the clock signal.

In the embodiment of the present disclosure, as shown in fig. 2, the ith clock signal Clk [ i ] of the last stage register is sampled at the clock input end, so as to ensure that the clock signal sampled by the ith clock signal is in a low level state, thereby ensuring that glitch-free switching is achieved in the multi-clock switching process.

In practical application, the last stage register receives the enable signal from the first stage register, and outputs the enable signal of the ith clock signal after the clock signal is subjected to falling edge sampling. In the last stage register, the clock signal is subjected to falling edge sampling, no matter whether the clock signal input is in a high level state or a low level state, only the low level state is collected, and if the low level state is represented as 0, the enable signal of the ith path of clock signal output by the last stage register can be represented as 0. When the output and gate performs logical and operation, the enable signal of the ith clock signal and the ith clock signal are and-connected, and the determined output signal of the ith clock circuit is in a low level state.

By adopting the multi-clock switching circuit provided by the embodiment of the disclosure, the output clock generates burrs when switching among a plurality of clocks is effectively avoided.

As shown in FIG. 3, another circuit for multi-clock switching provided in the embodiments of the present disclosure takes the 0 th clock circuit as an example, clksel [0] to-Q [ N-1] are represented as clock selection signals, and an input AND gate is connected to the clock selection signals. Q0, Q1 and Q2 are registers, the D end of the register is a signal input end, and the Q end is a signal output end. Wherein q0 and q1 can be understood as the first stage register, and q2 can be understood as the last stage register. Connected to the output Q of Q2 is an output and gate. The output end of the output and gate is connected with an or gate, and the or gate outputs one path of clock signals in the N clock sources, namely the CLKOUT.

In the embodiment of the present disclosure, a value of an i-th input signal corresponding to the input and gate is determined according to the clock selection signal, the clock selection signal may be understood as a circuit switching signal, and when the circuit is not switched to the i-th circuit, the clock signal corresponding to the i-th input terminal of the input and gate 101 is an i-th inverted clock signal output by the de-inversion output terminal of the register group. When the circuit is switched to the ith circuit, the clock signal corresponding to the ith input terminal of the input and gate 101 is the ith clock signal. And the negation output end of the register group is connected with the ith input end of the input AND gate of other clock circuits.

Taking the 0 th clock circuit as an example in the figure, the input end of the 0 th bit of the input AND gate is connected with the clock selection signal of the 0 th clock circuit, the 0 th input signal corresponding to the input AND gate is determined to be clksel [0] according to the clock selection signal, the input ends of the rest bits of the input AND gate are connected with the inverting output end-Q of the Q2 register of the rest clock circuit, and the other input signals corresponding to the input AND gate are determined to be Q [1], -Q [2] to-Q [ N-1] according to the clock selection signal.

In practical application, the clksel clock selection signal with N bits is encoded by using one-hot code, which is also called one-bit effective encoding, and N states are encoded by using an N-bit register, wherein only one bit is effective, the state decoding is simple, the combinational logic can be reduced, and the processing speed can be increased.

In practical application, all registers of the circuit are connected with the same reset source, so that when a clock signal changes and after the clock switching circuit is switched, the register group is controlled by the same reset source, and the controlled circuit works normally.

By adopting the multi-clock switching circuit provided by the embodiment of the disclosure, the input result of the OR gate is formed by the AND operation of the clock selection signal and the input AND gate in the form of the one-hot code, the NOT operation at the inverting end of the NOT and the AND operation of the output AND gate. And finally determining a target clock signal through OR operation of an OR gate, thereby effectively reducing the influence of metastable state and burr on the circuit through register groups and various logic operations, and further improving the reliability and stability of the multi-clock switching circuit.

As shown in fig. 4, an embodiment of the present disclosure provides a schematic diagram of the input and output of a circuit for multi-clock switching.

The input is N paths of clocks, and the serial numbers of the clocks are from 0 to N-1, namely CLK [0], CLK [1], … … CLK [ N-1 ]; the input select signal clksel is also corresponding to N bits, numbered from 0 to N-1. CLKOUT is the output clock. In the process of switching the clock signal to 1 path, to N-2 paths and to N-1 paths, the CLKOUT has a clock switching process, and the specific switching process includes:

and controlling the multi-clock circuit to output the ith clock signal according to the clock selection signal.

The control clock circuit is switched from the ith clock signal to the jth clock signal.

And controlling the multi-clock circuit to output the jth clock signal according to the clock selection signal. In practical application, the multi-clock circuit outputs the ith clock signal, namely at the input end of the or gate, the ith clock signal is represented as 1, and the other clock signals are represented as 0, namely the ith clock signal is output through the logical or operation of the or gate.

The control clock circuit is switched from the ith clock signal to the jth clock signal. In practical application, the ith clock signal is switched to the jth clock signal. The process of outputting the ith clock signal by the multi-clock circuit, stopping outputting the ith clock signal by the multi-clock circuit and outputting the jth clock signal by the multi-clock circuit is needed. The multi-clock circuit stops outputting the ith clock signal, and it is understood that at the input end of the or gate, the ith clock signal is represented as 0, and the other clock signals are represented as 0, that is, no clock signal is output through the logical or operation of the or gate.

And controlling the multi-clock circuit to output the jth clock signal according to the clock selection signal. In practical application, namely at the input end of the or gate, the jth clock signal is represented as 1, and the other clock signals are represented as 0, namely the jth clock signal is output through the logical or operation of the or gate.

The FPGA provided by the embodiment of the disclosure comprises the circuit for multi-clock switching. The logic instructions in the FPGA can be implemented in the form of software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products.

The electronic equipment provided by the embodiment of the disclosure comprises the FPGA.

The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. Furthermore, the words used in the specification are words of description only and are not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises" and/or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other like elements in a process, method or apparatus that comprises the element. In this document, each embodiment may be described with emphasis on differences from other embodiments, and the same and similar parts between the respective embodiments may be referred to each other. For methods, products, etc. of the embodiment disclosures, reference may be made to the description of the method section for relevance if it corresponds to the method section of the embodiment disclosure.

Claims

1. A circuit for multi-clock switching, comprising:

n clock sources configured to generate N clock signals;

wherein the ith clock circuit comprises:

an input AND gate having N input terminals;

the register bank includes two or more cascaded registers.

2. The circuit for multi-clock switching according to claim 1, wherein the register set comprises:

the signal input end of the last-stage register is connected with the output end of the first-stage register, and the clock input end of the last-stage register is connected with the ith clock signal; the output end of the last stage register is used as the output end of the register group.

3. The circuit for multi-clock switching of claim 2,

and the last stage register performs falling edge sampling on the ith path of clock signal.

4. The circuit for multi-clock switching of claim 1,

and the ith input end of the input AND gate is connected with the corresponding clock selection signal, and the value of the ith input signal corresponding to the input AND gate is determined according to the clock selection signal.

5. The circuit for multiple clock switching of claim 4, wherein the clock select signal is a one-hot code form of the clock select signal.

6. The circuit for multi-clock switching according to any of claims 1 to 5, wherein the register set further comprises:

the reset end of the register group is connected with a total reset signal.

7. An FPGA comprising a circuit for multi-clock switching as claimed in any one of claims 1 to 6.

8. An electronic device comprising the FPGA of claim 7.