RU2573732C2 - Programmable logical device - Google Patents

Abstract

FIELD: physics, computation hardware.

SUBSTANCE: invention relates to computation and can be used for computation of logical function systems in programmable logical IC. Claimed device comprises the set of n inverters, n sets of transmitting transistors, set of 2ⁿ inverters, inverter, 2ⁿ sets of zero constituents and m sets of functions computation.

EFFECT: lower hardware input to realisation of logical functions of the great number of variables.

6 dwg, 1 tbl

Description

The invention relates to computer technology and can be used to calculate systems of logical functions in programmable logic integrated circuits (FPGA).

A programmable logic device is known that contains the first, second, and third groups of D-flip-flops of m · 2 ^{n each} (n is the number of input variables, m is the number of output functions), the third group of D-flip-flops of 2 (n-1) m, group m (n-1) AND elements, counter, a group of m · 2 ⁿ AND elements with three output states, a decoder, a group of m (n-1) OR elements, a second group of m · 2 ⁿ AND elements with three output states and m blocks calculation functions, each function calculating unit comprises a group 4 · 2 ⁿ elements and a tri-state output, two D-flip-flop, T rigger, RS-trigger pulse fixation five elements or three elements and four inverter, n groups of elements 2 x 2 NAND-OR (in each i-th group includes 2 ^n-1 elements, i = 1, n) , delay element, an additional group of AND elements with three states at the output (RF patent No. 2146840 dated 03.20.2000, class G11C 17/00, G06F 7/00).

A disadvantage of the known device is the high hardware costs, expressed in the number of transistors, for the implementation of a logical function in programmable logic integrated circuits (FPGAs).

The closest device of the same purpose to the claimed invention in terms of features is a programmable logic device containing a group of n inverters, n groups of transmitting transistors (n is the number of input variables), 2 ⁱ , i = 1, n transistors in a group, a group of 2 ⁿ inverters settings, output inverter, inputs of n variables, group of 2 ⁿ configuration inputs, device output,

moreover, the gate of each odd transistor of the i-th group of transmitting transistors i = 1, n is connected to the output of the i-th inverter of the group of n inverters, the gate of each even transistor of the i-th group of transmitting transistors is connected to the i-th input of the inputs of n variables, sources 2 ⁿ transistors of the n-th group are connected to the outputs of the inverters of a group of 2 ⁿ tuning inverters, the inputs of which are a group of 2 ⁿ tuning inputs, the drains of the even and odd transistors of the n-th group are combined and connected to the sources of the corresponding 2 ^n-1 transistors of the n-1-th group whose drains are about edineny and connected to the sources of the respective 2 ^n-2 transistors are n-2nd group last two drains of transistors the first group are combined and connected to the input of the inverter output, the output of which is the output device (Stroganov, S. Tsybin Programmable switching in FPGA: inside view // Components and Technologies. - 2010. - No. 11. P.56-62 Fig. 9, [Electronic resource]. - URL: http://www.kit-e.ru/articles/plis/ 2010_11_56.php 11/12/12).

A disadvantage of the known device adopted as a prototype is the inability to implement more than one function in one device, and therefore, m devices require m devices to implement m functions, which in turn leads to high hardware costs in the number of transistors for implementing logical functions systems of a large number of variables in FPGA.

This is due to the following circumstances. The technical means of the prototype are oriented towards implementation, depending on the configuration of one particular logical function of n variables in perfect disjunctive normal form (SDNF). To implement a system of m logical functions of the same n variables, m devices are needed, although constituents (SDNF elements) can be repeated in these functions.

In this regard, the hardware costs in the number of transistors for implementing systems of m logical functions of the same n variables even increase for relatively small n - of the order of 8 ... 10.

Currently, in leading programmable logic integrated circuits (FPGAs) of leading companies there has been a transition to programmable logic devices (also called LUTs - Look Up Table) of 6.7 variables, however, blocks of 4.5 variables are mainly used.

Signs of the prototype, which coincides with the essential features of the claimed invention - contains a group of n inverters, n groups of transmitting transistors (n is the number of input variables), 2 ⁱ , i = 1, n transistors in a group, a group of 2 ⁿ inverters, an inverter, inputs of n variables, the gate of each odd transistor of the i-th group of transmitting transistors i = 1, n is connected to the output of the i-th inverter of the group of n inverters, the gate of each even transistor of the i-th group of transmitting transistors is connected to the i-th input of the inputs of n variables.

The objective of the invention is to enable the implementation of several functions in one device and thereby reduce hardware costs for the implementation of logical functions of a large number of variables in the FPGA.

The problem was solved due to the fact that in the inventive device containing a group of n inverters, n groups of transmitting transistors (n is the number of input variables), 2 ⁱ , i = 1, n transistors in the group, a group of 2 ⁿ inverters, inverter, inputs n variables, and the gate of each odd transistor of the i-th group of transmitting transistors i = 1, n is connected to the output of the i-th inverter of the group of n inverters, the gate of each even transistor of the i-th group of transmitting transistors is connected to the i-th input of the inputs of n variables,

additionally introduced 2 ⁿ blocks of zero constituent, and m blocks of function calculation,

moreover, the inverter input is connected to a zero volt bus, the inverter output is connected to the sources of two transistors of the first group of transmitting transistors, the drains of transistors of the first group of transmitting transistors are connected to the combined sources of even and odd four transistors of the second group of transmitting transistors, and so on, that is, the combined sources of even and odd transistors from 2 ^n-1 transistors of the n-1st group are connected to the drains of 2 ^n-2 transistors of the n-2nd group, i = 1, n, the drains of transistors from 2 ⁿ transistors last, nth group connected to the input m inverters group 2 ⁿ inverters and to the outputs of the respective 2 ⁿ blocks constituents ,, zero inputs of which are connected to respective input variable or variables n inversions variables with respective outputs for implementing zero constituents inverters group n inverters, the outputs of inverters group 2 ⁿ inverters are connected to 2 ⁿ inputs of the constituent of the SDNF m function calculation blocks, groups of 2 ⁿ inputs of which are m groups of device configuration inputs, and the outputs of m function calculation blocks are device outputs,

each implementation block of the zero constituent contains n transmitting transistors, the sources of which are combined and are the output of the block, the drains of which are combined and connected to the zero-volt bus, the gates of the transistors are connected to the corresponding bits of the variables n variable inputs, or to the inversions of the variables from the outputs of the corresponding inverters of the group n inverters, so that in the jm block for the implementation of the constituent zero, a denial of the constituent unit with decimal number j-1 is formed,

each j-th block of function calculation contains a group of 2 ⁿ transmitting transistors, the sources of which are connected to the outputs of 2 ⁿ inverters of a group of 2 ⁿ inverters to include the corresponding set in the corresponding function, the drains of the transmitting transistors are combined and connected to the input of the inverter, the output of which is the output unit, the gates of the transmitting transistors are connected to the corresponding bits of the j-th group of the device configuration input groups.

Signs of the proposed technical solution, distinctive from the prototype — contains 2 ⁿ blocks of zero constituent, and m function calculation blocks, the inverter input is connected to the “zero volt” bus, the inverter output is connected to the sources of two transistors of the 1st group of transmitting transistors, the drains of transistors 1- the second group of transistors are connected to transmit the combined origins of odd and even four transistors 2nd group transmitting transistors, and so on, i.e. the combined sources of odd and even transistors of 2 ^n-1 n-transistors 1st group s are connected to the drains of two ^n-2 transistors are n-2nd group, i = 1, n, the transistors drains of 2 ⁿ final transistors, n-th group are connected to the inputs of inverters group 2 ⁿ inverters and to the outputs of the corresponding one of 2 ⁿ blocks a zero constituent, the inputs of which are connected to the inputs of n variables or variable inversions from the outputs corresponding to the implementation of a zero constituent of inverters of a group of n inverters, outputs of inverters of a group of 2 ⁿ inverters are connected to 2 ⁿ inputs of a constituent of an SDNF m of function calculation blocks, of a group of 2 ⁿ inputs which are m groups of device configuration inputs, and the outputs of m function calculation blocks are device outputs,

each implementation block of the zero constituent contains n transmitting transistors, the sources of which are combined and are the output of the block, the drains of which are combined and connected to the zero-volt bus, the gates of the transistors are connected to the corresponding bits of the variables n variable inputs, or to the inversions of the variables from the outputs of the corresponding inverters of the group n inverters, so that in the jm block for the implementation of the constituent zero, a denial of the constituent unit with decimal number j-1 is formed,

each j-th block of function calculation contains a group of 2 ⁿ transmitting transistors, the sources of which are connected to the outputs of 2 ⁿ inverters of a group of 2 ⁿ inverters to include the corresponding set in the corresponding function, the drains of the transmitting transistors are combined and connected to the input of the inverter, the output of which is the output of the block, the gates of the transmitting transistors are connected to the corresponding bits of the jth group of groups of tuning inputs of the device, to the i-th input of which, i = 1,2n, one is supplied if the i-th constitution of the unit is included in the SDNF of the implemented j-th function and zero - if not.

Distinctive features in combination with the known ones make it possible to implement in one device not one but several functions - a system of logical functions depending on the same members of a perfect disjunctive normal form (SDNF), by turning them on or off by setting them in different m functions, which allows to reduce hardware costs in the number of transistors for the implementation of logical functions of a large number of variables in the FPGA.

, для конституенты единицы $${\overline{x}}_1{\overline{x}}_2{\overline{x}}_3{\overline{x}}_4$$

(номер 0) альтернативная цепочка - конституента нуля имеет вид: $$x_1\vee x_2\vee x_3\vee x_4$$

.The introduction of 2 ⁿ blocks of zero constituent ensures the exclusion of the states of unconnected (“dangling”) inputs of inverters of a group of 2 ⁿ inverters when one of 2 ⁿ paths is implemented in a “transmitting transistor tree” pyramidally constructed from n groups of transmitting transistors (n is the number of input variables) by 2 ⁱ , i = 1, n transistors in the group, for each output inverter an alternative circuit is created in the form of a zero constituent in 2 ⁿ zero constituent blocks, guaranteed to translate the output of the corresponding inverter to unity by connecting a bus "Zero volts" in at least one variable in case of inactivation of this path in the transistor tree. So, for the constituent unit x ₁ x ₂ x ₃ x ₄ (number 15), an alternative chain - the zero constituent takes the form: $${\overline{x}}_{\mathrm{one}}\vee {\overline{x}}_2\vee {\overline{x}}_3\vee {\overline{x}}_{\mathrm{four}}$$

for constituent units $${\overline{x}}_{\mathrm{one}}{\overline{x}}_2{\overline{x}}_3{\overline{x}}_{\mathrm{four}}$$

(number 0) an alternative chain - the zero constituent has the form: $$x_{\mathrm{one}}\vee {\mathrm{<figure-callout\; id="2"\; label="x"\; filenames="00000022.png,00000023.png"\; state="\{\{state\}\}">x</figure-callout>}}_2\vee x_3\vee x_{\mathrm{four}}$$

.

The introduction of m function calculation blocks allows, by tuning, to ensure the inclusion or not inclusion of SDNF members in various m functions.

Changing the connections in comparison with the known device provides a “turn”, a “reverse” of the device — to implement decryption, the SDNF constituent by transmitting one of the 2 ⁿ paths in the “transmitting transistor tree” from a logical zero not to the root of the “tree”, but from the “root” that is fixed by an active zero at the output of one of 2 ⁿ inverters of the group of 2 ⁿ inverters.

Figure 1 shows an electrical structural diagram of a programmable logic device.

.Figure 2 is an electrical functional diagram of the j-th block of 2 ⁿ blocks constituting zero, $$\text{j}=\overline{\text{one}{\text{, 2}}^{\text{n}}}$$

.

.Figure 3 - electrical functional diagram of the j-th block of m blocks of function calculation, $$\text{j}=\overline{\text{one}\text{, m}}$$

.

On Fig 4 is a graph of changes in the gain in the number of transistors when using one of the proposed device instead of m devices - prototypes with the number of functions m = 8.

In Fig. 5 is a graph of the change in gain in the number of transistors when using one proposed device instead of m devices - prototypes with the number of functions m = 16.

On Fig 6 is a graph of changes in the gain in the number of transistors when using one proposed device instead of m devices - prototypes with the number of functions m = 32.

The programmable logic device contains

транзисторов в группе, группу 2ⁿ инверторов 3, инвертор 4, 2ⁿ блоков конституент нуля 5, и m блоков вычисления функций 6, входы n переменных 7, m выходов устройства 8, m групп 2ⁿ настроечных входов 9, вход «ноль вольт» 10.a group of n inverters 1, n groups of transmitting transistors 2 (n is the number of input variables) by $$2^i,i=\overline{\mathrm{one,}n}$$

transistors in a group, a group of 2 ⁿ inverters 3, an inverter 4, 2 ⁿ blocks of constitutions of zero 5, and m blocks of calculating functions 6, inputs of n variables 7, m outputs of the device 8, m groups of 2 ⁿ tuning inputs 9, a zero volt input 10.

The gate of each odd transistor of the i-th group of transmitting transistors 2 i = 1, n is connected to the output of the i-th inverter of the group of n inverters 1, the gate of each even transistor of the i-th group of transmitting transistors 2 is connected to the i-th input of the inputs of n variables 7, the inverter 4 input is connected to the zero-volt bus 10, the inverter 4 output is connected to the sources of two transistors of the 1st group of transmitting transistors 2.1, the drains of the transistors of the 1st group of transmitting transistors 2.1 are connected to the combined sources of even and odd four transistors of the 2nd group transmitting transistors 2.2, and so on, that is, the combined sources of even and odd transistors 2 of 2 ^n-1 transistors of the n-1st group are connected to the drains of 2 ^n-2 transistors of the p-2nd group, i = 1, n, drains transistors from 2 ⁿ transistors of the last, nth group are connected to the inputs of inverters of group 2 ⁿ inverters 3 and to the outputs of the corresponding of 2 ⁿ blocks of zero constitutive 5, the inputs of which are connected to the corresponding variables of the inputs of n variables 7 or inversions of the variables from the outputs corresponding to the implementation constituents of zero inverters of the group of n inverters 1, Exit inverter group of inverters 2 ⁿ 3 ⁿ 2 are connected to the inputs of the m blocks constituents PDNF calculation functions 6, group 2 ⁿ inputs of which are m groups of 9.1 ... 9.m tuning device inputs and outputs m computation functions are the outputs of blocks 6 8.1 ... 8. m devices.

Each block of realization of the zero constituent contains n transmitting transistors 11, the sources of which are combined and are the output of the block, the drains of which are combined and connected to the zero-volt bus 12, the gates of the transistors are connected to the corresponding bits of the variable outputs of the variables 7, or to the inversions of the variables from the outputs of the corresponding inverters of the group of n inverters 1, so that in the jm block for the implementation of the constituent zero, a denial of the constituent unit with decimal number j-1 is formed.

Each j-th block of function calculation 6 contains a group of 2 ⁿ transmitting transistors 13, the sources of which are connected to the outputs of 2 ⁿ inverters of a group of 2 "inverters to include the corresponding set in the corresponding function, the drains of the transmitting transistors 13 are combined and connected to the input of the inverter 14, the output of which is the output of the unit, the gates of the transmitting transistors are connected to the corresponding bits of the j-th group 9.j of the 9 tuning inputs of the device, the i-th input of which, i = l, 2n, is supplied with a unit if the i-th constitution units are included in the SDNF of the implemented j-th function and zero if not.

A programmable logic device operates as follows:

1. Programming mode. In this mode, the m 2 groups of ⁿ inputs 9 tuning settings are set signals m logic functions depending on no more than ⁿ variables.

If the ith constituent is included in the jth logical function, then at the input 9.jI of group 9.j of m groups of 2 ⁿ tuning inputs 9, one is set to zero, otherwise zero. Thus, all the necessary m blocks for calculating functions 6 are programmed by activating the gates of the corresponding transistors 13.

Example. Suppose, for example, you need to implement the following system of seven logical functions depending on four variables y ₂ y ₁ x ₂ x _z :

y ₂ (t + 1) = 4,5,6,7,12,13,14,15;

y ₁ (t + 1) = 0,1,2,3,4,5,6,7,14,15;

z ₁ = 0,1,2,3;

z ₂ = 4,5,6,7,14,15;

z ₃ = 12.14;

z ₄ = 8.9;

z ₅ = 10, ll.

In the known device, only one of these seven functions can be implemented. In this regard, 7 known devices are required.

In the proposed device, seven function calculation blocks 6.1-6.7 are configured according to the configuration inputs 9.1-9.7 in accordance with table 1:

2. The mode of calculation. In this mode, the values of the input variables are received at the inputs of n variables 7, and the output of the i-th inverter from the group of 2 ⁿ inverters 3 is activated (becomes zero), if the binary code corresponding to the decimal number i is installed at the inputs of n variables 7. That is, one of 2 ⁿ paths is implemented in the reverse tree of transistors 2 from the output of the inverter 4 - the logical unit is fed to the input of the inverter 3.i. This path is fixed by activating the gates of all transistors in it by the signals of the inputs of n variables 7 and the outputs of the inverters of the group n of inverters 1.

Moreover, in the ith of 2 ⁿ blocks, the zero constituent 5.i has the gates of all transistors 11.i not activated, and in all the rest, except the i-th, at least one gate of the transistors 11 is activated, which ensures the connection of the “zero volt” bus 12 to the inputs of all but 3.i inverters, which fixes their outputs in an inactive (single) state.

Accordingly, the inputs of inverters 14 are activated in those blocks of m function calculating blocks 6 that are configured to turn on the set (constituents) i through the i-th transistor 13. Therefore, logical units appear on the corresponding outputs 8.

, логическая единица с выхода инвертора 4 поступает на вход инвертора 3.15, на выходе которого формируется логический ноль.So, to configure the above example, if you set n variables 7 (7.4, 7.3, 7.2, 7.1) of the binary set y ₂ y ₁ x ₂ x ₁ equal to 1110 at the inputs, the transistor chain corresponding to the constitution is activated

, the logical unit from the output of the inverter 4 is fed to the input of the inverter 3.15, the output of which is a logical zero.

, которая на наборе переменных 1110 равна нулю $$(\overline{1}\vee \overline{1}\vee \overline{1}\vee 0=0)$$

затворы всех транзисторов 11 не активированы, поэтому цепь от шины «ноль вольт» 12 ко входу инвертора 3.15 разомкнута.At the same time, in block 5.15 that implements the zero constitution No. 14 (15-1)

which on the set of variables 1110 is equal to zero $$(\overline{\mathrm{one}}\vee \overline{\mathrm{one}}\vee \overline{\mathrm{one}}\vee 0=0)$$

the gates of all transistors 11 are not activated, so the circuit from the zero-volt bus 12 to the input of the inverter 3.15 is open.

, которая на наборе переменных 1110 не равна нулю $$(\overline{1}\vee \overline{1}\vee 1\vee \overline{0}=1)$$

затворы двух транзисторов 11 активированы, поэтому цепь от шины «ноль вольт» 12 ко входу инвертора 3.14 имеется, поэтому выход инвертор 3.13 удерживается в состоянии логической единицы. Аналогично происходит с остальными инверторами 3.16, 3.12, 3.11…3.1.In block 5.14, for example, implements the constituent zero

which is not equal to zero on the set of variables 1110 $$(\overline{\mathrm{one}}\vee \overline{\mathrm{one}}\vee \mathrm{one}\vee \overline{0}=\mathrm{one})$$

the gates of the two transistors 11 are activated, so there is a circuit from the zero-volt bus 12 to the input of the inverter 3.14, so the output of the inverter 3.13 is kept in the state of a logical unit. Similarly happens with other inverters 3.16, 3.12, 3.11 ... 3.1.

Further, in the function calculation blocks 6.1, 6.2, 6.4, 6.5, which are configured in accordance with Table 1 to enable constitution 14, the inputs of inverters 14 are activated. Therefore, logical units appear on the corresponding outputs 8.1, 8.2, 8.4, 8.5, which means equality to the unit of functions

y ₂ (t + 1), y ₁ (t + 1), z ₂ , z ₃ ,

in the working (single) sets of which the constitution is included 14.

Assessment of technical and economic efficiency

In complexity L, we compare the well-known programmable device, LUT L (n) and the proposed one, DC LUT (Ldc). The complexity of the prototype that implements one function is determined by the expression:

Where

2 ^{n + 1} -2 + 2 = 2 ^{n + 1}

transistors in the tree of transmitting transistors + two transistors in the output inverter 4,

2n

transistors in the inverter group 1,

2 · 2 ⁿ

transistors in the inverter group 3.

The complexity of the proposed, realizing m functions of n variables, is determined by the expression:

Where

2 ^{n + 1} -2 + 2 = 2 ^{n + 1}

transistors in the tree transmitting transistors + two transistors in the inverter 4,

2n

transistors in the inverter group 1,

2 · 2 ⁿ

transistors in the inverter group 3,

m2 ⁿ + 2m

transistors in m function calculation blocks 6,

n2 ⁿ

transistors in blocks constituent zero 5.

Thus, we get a gain:

Win graphs are shown in FIGS. 4-6

Figure 4. The change in the gain in the number of transistors when using one of the proposed device instead of m devices - prototypes

at m = 8.

Figure 5. The change in the gain in the number of transistors when using one of the proposed device instead of m devices - prototypes

at m = 16.

6. The change in the gain in the number of transistors when using one of the proposed device instead of m devices - prototypes

at m = 32.

Thus, a gain of several tens of percent is possible with m = 8 to hundreds of percent m = 16, 32.

So, for the given example n = 4, m = 7 (you need one proposed device against 7 devices - prototypes) we get a gain of 45.6%:

The achievement of the technical result of the invention is confirmed by the above estimates.

Claims (1)

A programmable logic device containing a group of n inverters, n groups of transmitting transistors (n is the number of input variables) by $$2^i,i=\overline{\mathrm{one,}n}$$

transistors in a group, a group of 2 ⁿ inverters, an inverter, inputs of n variables, m groups of 2 ⁿ tuning inputs 9, a zero volt input, and the gate of each odd transistor of the i-th group of transmitting transistors is connected to the output of the i-th inverter of the group of n inverters , the gate of each even transistor of the i-th group of transmitting transistors is connected to the i-th input of the inputs of n variables,
characterized in that 2 ⁿ blocks of zero constituent and m function calculation blocks are additionally introduced, the inverter input connected to a zero volt bus, the inverter output connected to the sources of two transistors of the 1st group of transmitting transistors,
the drain of the first transistor of the 1st group of transmitting transistors is connected to the combined sources of the first and second of four transistors of the 2nd group of transmitting transistors,
the drain of the second transistor of the 1st group of transmitting transistors is connected to the combined sources of the third and fourth of four transistors of the 2nd group of transmitting transistors,
the drain of the first transistor of the 2nd group of transmitting transistors is connected to the combined sources of the first and second of eight transistors of the 3rd group of transmitting transistors,
the drain of the second transistor of the 2nd group of transmitting transistors is connected to the combined sources of the third and fourth of eight transistors of the 3rd group of transmitting transistors,
the drain of the third transistor of the 2nd group of transmitting transistors is connected to the combined sources of the fifth and sixth of eight transistors of the 3rd group of transmitting transistors,
the drain of the fourth transistor of the 2nd group of transmitting transistors is connected to the combined sources of the seventh and eighth of eight transistors of the 3rd group of transmitting transistors,
transistors in groups 3, 4 ... n-2 are connected in a similar way, the combined sources of even and odd transmitting transistors from 2 ^n-1 transistors of the n-1 group are connected to the drains of the corresponding 2 ^n-2 transistors of the n-2 group, i = 1, n, drains of 2 ⁿ transistors of the last, nth group are connected to the inputs of the inverters of the group of 2 ⁿ inverters and to the outputs of the corresponding of 2 ⁿ blocks of zero constants, the inputs of which are connected to the corresponding variables of the inputs of n variables or inversions of the variables from the outputs corresponding to the implementation constituents of zero inverters gru PP n inverters, inverter outputs of a group of 2 ⁿ inverters connected to 2 ⁿ inputs of the SDNF constituent m function calculation blocks, groups of 2 ⁿ inputs of which are m groups of device configuration inputs, and the outputs of m function calculation blocks are device outputs,
in this case, each implementation block of the zero constitution contains n transmitting transistors and a zero volt bus, the sources of the transmitting transistors are combined and are the output of the unit, the drains of which are combined and connected to the zero volt bus, the gates of the transistors are connected to the corresponding bits of the variable variable outputs or to the inversions of the variables from the outputs of the corresponding inverters of the group of n inverters, so that in the jm block of the implementation of the constituent zero, the denomination of the constituent unit with decimal number j-1 is formed,
each j-th block of function calculation contains a group of 2 ⁿ transmitting transistors and an inverter, the sources of transmitting transistors are connected to the outputs of 2 ⁿ inverters of a group of 2 ⁿ inverters to include the corresponding set in the corresponding function, the drains of the transmitting transistors are combined and connected to the inverter input whose output is the output of block valves transmitting transistors connected to the corresponding j-th discharge group groups tuners inputs to i-th input of which, i = 1,2 ^n, is fed edi Itza, if the i-th unit is included in the constituent PDNF implemented the j-th function, and zero - if not included.

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