SU1233274A1 - Programmed logic module - Google Patents

Abstract

The invention relates to devices for implementing controlled logic functions. Can be used in computing. The purpose of the invention is to expand the functionality of the proposed logical module, achieved through the implementation of a large number of logical functions. The programmable logic module is implemented on field-effect transistors 1-70, contains input buses 71-81 and two power buses 82 and 83. To achieve this goal, five input buses and fifty eight field-effect transistors were introduced into it. 1 il. (L to 00 from about 4;

Description

i1Invention otisosit to usgroy (1-1zam implementation of controlled logical functions and can be used in computing.

The purpose of the invention is the expansion of the functional possible programmable logic module for the implementation of a larger number of logical functions.

The drawing shows a block diagram of a programmable logic module.

The programmable logic module contains seventy field-effect transistors 1-70, eleven input lines 71-81, and two power lines 82 and 83, the first input line 71 is connected to the gates of the first 1 and second 2 field-effect transistors, the sources of which are connected to the first power line 82, the drain of the first field-effect transistor 1 is connected to the source of the third field-effect transistor 3, the drain of the second field-effect transistor 2 is connected to the source of the fourth field-effect transistor 4, the second input bus 72 is connected to the gate of the fifth field-effect transistor 5, the source and drain of which connected to the first bus 82 of the power supply and the source of the sixth field-effect transistor 6, the gate of which is connected by the third input line 73, the fourth input line 74 is connected to the gateways of the seventh 7 and eighth 8 field effect transistors, and the first input bus 75 is connected to the gateways of the ninth 9 and tenth of 10 field-effect transistors, pole input bus 76 is connected to the gates of the eleventh 11 and twelfth 12 field-effect transistors, the seventh input bus 77 is connected to the gate of the thirteenth field-effect transistor 13, the source of which is connected to the drain the twentieth field effect transistor 14 and the first power supply bus 82 which is connected to the drains of the third 3, fourth 4, fifteenth 15, eighth 8, tenth ten, twelfth 12, sixth sixteen, sixteenth 16 seventeenth 17, eighth eighteen and nineteenth 19 field-effect transistors, and also with the beginnings of the seventh 7, nine nine, eleventh eleven, twentieth 20, twenty-first 21, twenty second 22, twenty-third 23, twenty-fourth 24, twenty nth 25, twenty-sixth 26, twenty seven seventh 27, twenty-eighth 28 and twenty maidens 29 pm.

TiKiii-.iiiC i-opiji- ;, iv. The rjpaH of Tina 83 is connected to the sources and gates of the thirtieth K), tridiat. first 31, thirty second 32, third and third, ei o 33, thirty-fourth 34, thirty-one; In addition, 35 and thirty-sixth 36 field effect transistors, as well as with the gates and drains of the thirty-seventh 37, thirty-eight o 38, thirty

nine ninety thirty, forty 40, forty-first 41, forty second) 42, forty-third 43, forty-fourth 44, forty-five, 45, forty-sixth 46, forty-seventh 47, forty, eighth 48,

Forty-nine, 49, five of the 50 field-effect transistors, the first power supply bus 82 is also connected to the sources of the fifty first 51, fifty the second 52, fifty the third 53 and fifteen of the fourth field effect transistors and fifty the fifth 55 and fifty sixth 56 field-effect transistors, the drain of the fifth field-effect transistor 5 is connected to the drain of the thirtieth 30 and

the twenty-second gates 22 and fifty-seventh 57 field-effect transistors, the drain fifty-seventh field-effect transistor 57 is connected to the source of the thirty-seventh 37 and the gate fifty-eighth to eighth 58 field-effect transistors, the source of the fifty seventh seventh field-effect transistor 57 is connected to the drain of the twenty-third field-effect transistor 23, the gate of which is connected to the eighth 78 input bus, which is connected to. the gate of the sixteenth field-effect transistor 16, the source of which is connected to the drain of the twenty-second field-effect transistor 22 and the source of the fifty-eighth field-effect transistor 58, the drain of which is connected to the source of the thirty-eighth 38 and gate of the third 3 field-effect transistors, is connected to the drain of the third field-effect transistor 3 thirty-fifth field-effect transistor 35 and gates of the twentieth 20 and fifty and fifty-nine 59 field-effect transistors; a drain of fifty fifty-nine and fifty-nine field-effect transistors is connected to the source of the forty fifth and 45 gates and six the tenth of the 60 field-effect transistors, the source of the fifty-ninth field-effect transistor 59 is connected to the drain of the twenty-first field-effect transistor 21, the gate of which is connected to the gate of the fifteenth 15,

the source of the fortieth 40 and the drain of the sixty of the first 61 field-effect transistors, the source of the sixtieth field

3

the transistor 60 is connected to the source of the fifteenth 15 and the drain of the twentieth 20 field-effect transistors, the drain of the sixty-six 60 field-effect transistor is connected to the source of the forty-sixth 46 and the gate of the fourteenth 14 field-effect transistors, the source of the fourteen-four of the field-effect transistor 14 is connected to the drain of the thirteenth 13 and stock of the sixth 36 field-effect transistors, as well as fifty-fourth and fifty-five 54th and sixty-second second gates, 62 field-effect transistors, the drain of the sixtyth second field-effect transistor 62 is connected to the source of forty-ninth 49 and gate six with the third 63 field-effect transistor, the source of the sixty-second second 62 field-effect transistor is connected to a drain of fifty of the third field-effect transistor 53, the gate of which is connected to the gate of the fifty-sixth 56, source of the forty-eighth 48 and drain of the sixty fourth fourth 64 field-effect transistors, source The fifty of the sixth field-effect transistor 56 is connected to the drain of the fifty-fourth of the fourth field-effect transistor 54 and the source sixty of the third field-effect transistor 63, the drain of which is connected to the source of the fifty-five field-effect transistor 50 and is output ohm 84 programmable logic module, the source of the sixty fourth fourth 64 transistor connected to the source of the fifty and fifty second fifty second 52 field-effect transistors, the gate of the fifty fifth field-effect transistor 55 is connected to the gate fifty of the first 51, the source the forty-fourth 44 and the drain of the sixty-fifty fifth 65 field-effect transistors, the drain of the fifty of the first field-effect transistor 51 is connected to the source of the sixty-sixth sixth field-effect transistor 66, the drain of which is connected to the gate of the sixty fourth 64 and the source of the forty-seventh 47 field-effect transistors, a sixth sixth field-effect transistor of the sixth field-effect transistor 66 is connected to a fifty-second field-effect transistor 52 and a thirty-fourth stack 34, a second 2 and source of the fourth 4 field-effect transistors, the source of the sixty fifth fifth 65 field-effect transistor connected to the drain of the twenty-sixth 26 and the source of the twelfth field-effect transistors, the gate of the sixty-fifth of the field-effect transistor 65 is connected to is332744

with current c; o)) ok t egtegch 43 and the drain of the sixty seventh field-effect transistors 67, the source of the sixty seventh field-effect transistor 67 is connected to the drain 5 of the eleventh field-effect transistor 11, the sixty-seventh field effect transistor 67 is connected to the gate of the twenty-sixth field-effect transistor 2' , drains twenty-seventh) Q th 27 and thirty-third 33, as well as the source of nine-nineteenth 14 field-effect transistors, the second control bus 72 is connected to the twenty-seventh gate 27, twenty-eighth 28 and

5 twenty-nine 29 field-effect transistors, the ninth control to the bus 79 is connected to the gate of the seventeenth field-effect transistor 17, the source of which is connected to the drain of twenty de2Q in that 29, thirty-first 31 and gate of the sixty eighth 68 and twenty-fourth 24 field-effect transistors, the drain of the seventh field-effect transistor 7 is connected to the source of sixteen 25 tons of the eighth of the field-effect transistor 68, the drain of which is connected to the source of the thirty-nine ninety-nine and the gate of sixty of the first 61 field-effect transistors; The stopper 61 is connected to the drain of the twenty-fourth 24 and the source of the eighth 8 field-effect transistors, the tenth control bus 80 is connected to the gate of the eighteenth field-effect transistor 18, the source of which is connected to the drain of the twenty-eighth 28, drain of the thirty second 32 and gates of twenty-fifth and sixty the nine 69 field-effect transistors, the drain of the sixty-nine-ninth field-effect transistor 69 is connected to the source of the forty-first 41 and the gate of the seventy-one 70 field-effect transistors, the source of the sixty-nine-ninth 69 field-effect transistor is connected to

  the drain of the nine 9 field-effect transistor, the drain of the twenty-fifth field-effect transistor 25 is connected to the source of the tenth 10 and the source of the seventy-seventh 70 field-effect transistors, and the drain of the second half of the field-effect transistor 70 is connected to the source of the forty-second and 42 gate of the fourth 4 field-effect transistors, and An eleventh control bus 8t is connected to a gate de55 in the thirteenth field-effect transistor 19. The input buses 71, 72 and 77 are information inputs. The input buses 73 - 76 and 78 - 81 are tuning 30.

five

NYA entrances. Transistors 5, 6 and 30 form the first element And 85, transistors 17, 29 and 31 form the second element And 86, transistors 18, 28 and 32 form the third element And 82, transistors 19, 27 and 33 form the fourth element And 88, transistors 1 , 3 and 35 form the fifth element And 89, transistors 2, 4 and 34 form the sixth element And 90, transistors 13, 14 and 36 form the seventh element And 91, transistors 16, 22, 23, 37 „38., 57 and 58 form the first element EQUIPMENT 92, transistors 7, 8, 24, 39 ,, 40, 61 and 68 form the second element EQUITY 93, transistors 9, 10, 25, 41, 42, 48 and 69 form the third element EQUAL OSG 94, transistors 11, 12,, 26, 43, 44, 65 and 67 form the fourth element of the EQUITY 95, transistors 15, 20, 21, 45, 46, 59 and 60 form a five element of the EQUITY 96, transistors 47, 48, 51, 52, 55, 64, and 66 form the sixth element of the UNIMINITY 97, transistors 49, 50, 53, 54, 56, 62, and 69 form the seventh element of the EQUITY 98.

Programmable logic module operates as follows.

The control inputs of the module 73, 78, 79, 74, 80, 75, 81, and 76 are provided with the tuning signals U, U., U, U,, Uj, Ug, and,, Ug, which can be O, 1, x, from the outputs of the first 92, second 93, third 94 and fourth 95 elements EQUALITY, respectively, logical dependences are removed

f,, U, U, v x, 0, V0, U ,;

,, vxjil ,,,;

f,,. U. , x, rU,,

which implement any Boolean functions of two nepeMeFfHbix x, x; from the outputs of the fifth 96 and sixth 97 elements EQUALITY, respectively, the fluid dependences are removed

fj p, f. , "; f. - J.f. f. f, 2)

At output 84 of the module, the module has a dependency

- X. F, f

f.

 - f. .

(3)

ten

Q s

Q

five

In order to prove that the proposed module implements the Boolean functions of four variables, we show that the logical dependence / /, which is taken into account from the output of the module, implements the function, and four variables.

Any logical function variable that you need to implement can be represented by the following expression

, F () (3r -;) vx, M (x77x; j (4)

We transform the expression C3), the dominant terms f f by 1 (x., V x.), Half-square () x f VX, R (f, f), (5)

comparing expressions (4) and (5), it can be seen that fH / x ,, x) (6)) R (f,, fj (7).

their,

-five

From expression (7), it follows that with known functions f and h, the functions fp, f. must be equal to f RCf (x.x), (LP,)) (8). S - h

From the expression (8) it follows that for the function of four variables there are always functions f and f, the substitution of which into expression (3) will result in: the nth function of four variables. Similarly, it can be shown that these logical dependencies implement the functions of three variables, i.e. fj and fg are functions of three variables depending on the variables x, xj, x, since the alphabet of settings is 0.1, x, x, provided that the training signals (- {are simultaneously with the information signals.

Claims (1)

Invention Formula Programmable logic module, which has twelve field-effect transistors, six input lines and two power buses, the first input line is connected to the gates of the first and second field-effect transistors, whose sources are connected to the first power supply, the drain of the first field-effect transistor is connected to the source of the third field-effect transistor, the drain of the second field-effect transistor is connected to the source of the fourth field-effect transistor, the second input line is connected to the gate of the fifth field-effect transistor, the source and the drain of which are connected respectively with the first power bus and the source, the sixth field effect transistor, the gate of which is connected to the third input Egin, the fourth wire is connected to the gate of the seventh and eighth field E) 1X transistors, the fifth input bus is connected to the gate of the tenth and tenth field effect transistors, the pole input bus is connected to the gate of the eleventh and twelfth field effect transistors, characterized in that, in order to expand the functionality opportunities due to the implementation of a larger number of logical functions, it additionally introduced five input bus and fifty-eight field-effect transistors, the seventh input bus connected to the gate of the thirteenth field-effect transistor, the source of which is connected to the drain of the fourteenth field-effect transistor and the first power bus, which is connected to the drains of the third, fourth, fifteenth, eighth, tenth, twelfth, sixth, sixteenth, seventeenth eighteenth and nineteenth field-effect transistors, as well as with the sources of the seventh, nine In addition, the eleventh, twentieth, twenty-first, twenty-second, twenty-third, twenty-fourth, twenty-five, twenty-sixth, twenty-seventh, twenty-eighth and twenty-ninth field-effect transistors , The second bus connected to a power source and the gate of the thirtieth, thirty-first, thirty-second, tryd tsat third, thirty-fourth. thirty-fifth and thirty-sixth, field effect transistors, as well as with the gates and drains of the thirty-seventh, thirty-eighth, thirty-nineth, fortyth, forty-first, forty-second, forty-third, forty-fourth, forty-fifth, forty-sixth, H: o- The rock of the seventh, forty-eighth, forty, nine and fifty field-effect transistors, the first power supply line is also connected to the sources of the fifty first, fifty the second, fifty the third and fifty fourth field-effect transistors and the drain fifty Fifth and fifty of the sixth field x transistors, the drain of the fifth field-effect transistor is connected to the drain of the thirtieth and the gates of the twenty-second and fifty of the seventh field transistors, the drain of the fifty seventh field-effect transistor is connected to the source of the thirty-seventh and the gate fifty-eighth of the eighth field-effect transistors. ten 15 20 0 five 0 five five The tiCToK l of the seventh field transistor is connected to the drain of the twenty-third psch transistor, the gate of which is connected to the eighth input bus, which is connected to the gate of the sixteenth field transistor, the source of which is connected to the drain of the twenty-second field-effect transistor and the source of fifty the eighth field-effect transistor, the drain of which is connected to the source of the thirty-eighth and the gate of the third field-effect transistor, the source of the third field-effect transistor is connected to the drain of the thirty-fifth and field-effect transistor the twentieth and fifty-ninth field-effect transistors, the drain of fifty-nine ninth field-effect transistor is connected to the source of the forty-fifth and the gate of the sixtieth field effect transistor, the source of the fifty-ninth field effect transistor is connected to the drain of the twenty-first field-effect transistor, the gate of which connected to the gate of the fifteenth, the source of the fortieth and the drain of the sixty of the first field-effect transistors, the source of the sixtieth field-effect transistor is connected to the source of the fifteenth and the drain of the twentieth field-effect transistors, the drain of the The same field-effect transistor is single with the source of the forty-sixth and the gate of the four-way field-effect transistors, the source of the fourteenth field-effect transistor is connected to the drain of the thirtieth and the drain of the thirty-sixth field-effect transistors, as well as with fifty-fourth and sixty-second two field-effect transistors, the drain is sixty the second field-effect transistor is connected to the source of forty-nine and the gate sixty third third field-effect transistors, the source of sixty second second field-effect transistor is connected to the drain of the fifty, third The field-effect transistor, the gate of which is connected to the fifty-sixth gate, the forty-eighth source and the drain of the sixty fourth fourth field-effect transistors, the fifty-sixth source of the sixth field-effect transistor is connected to the fifty-fourth drain of the fourth field transistor and the source of the sixty third third transistor. , the drain of which is connected to the source of the fifth field-effect transistor and is the output of a programmable logic module gp, the source of six C of the fourth field wizard transistor is connected to the source of the first 50 and five of the second field-effect transistors, the gate of the fifty-fifth of the field-effect transistor is connected to the gate of the fifty-first, the source of the forty-fourth and the drain of the sixty-fifth field-effect transistors, the drain of the fifty-fifty of the first field-effect transistor is connected to the source-sixty of the sixth field-effect transistor, the drain of which is connected to the gate I1 of the tenth of the fourth and source of the forty-seventh field-effect transistors The ora is connected to the gate of the fifty second field-effect transistor and to the thirty-fourth drain, the second drain and source of the fourth field-effect transistor, the source of the sixty fifth field-effect transistor is connected to the drain of the twenty-sixth and source of the twelfth fifth transistor. connected to the source of the forty-third and the drain of the sixty seventh field-effect transistors, the source of the sixty-seventh seventh field-effect transistor connected to the drain of the eleventh field-effect transistor, the gate of the sixty the seventh field-effect transistor is connected to the gate of the twenty-sixth field-effect transistor, the drain of the twenty-seventh and thirty-third, as well as the source of the nine-ninth field-effect transistors, the second control is connected to the gate of the twenty-seventh, twenty-eighth and twenty-nine field Editor A. Sabo (. O. Okvortsov's Leader Tr hred O.SopkoKorrektor E. Sirohman Order 278А / 7 Edition 816 Subscription VNIIPI GocyDc pcтvPnnoJ (l to - ist on the boards of inventions and discoveries 113035, Moscow, Zh-35, PayiiRKJin lab ", d, A / 5 11th Season | -t11en} ng-polygrp} ichcheg h -; -.krp tp; -, Mr. V rofii; ,, you ts 0 5 o five transistors, den tg input bus connected to the gate of the seventeenth field-effect transistor, the source of which is connected to the drain of the twenty-ninth, thirty-first and gates of the sixty eighth and twenty-fourth field-effect transistors, the drain of the seventh field-effect transistor is connected to the source of the sixty-eighth field transistor, the drain of which The source is connected to the source of thirty ninety-one o and the gate of the sixty-one first field-effect transistors, the source of the sixty-fourth fourth field-effect transistor is connected to the drain of the twenty-fourth and the source the eighth field-effect transistor, the tenth input bus is connected to the gate of the eighteenth field-effect transistor, the source of which is connected to the twenty-eighth drain, the thirty-second drain and the twenty-fifth and sixty-nine ninth field-effect transistors, the drain of the sixty-ninth field-effect transistor is connected to the source the forty-first and the gate of the seven-hundred field-effect transistors, the source of the sixty-nine-ninth field-effect transistor is connected to the drain of the ninth field-effect transistor, the drain of the twenty fifth field-effect transistor is connected It is connected to the source of the tenth and the source of the seventy-one field-effect transistors, the drain of the seventy-one field-effect transistor is connected to the source of the forty-second and the gate of the fourth field-effect transistor, and the eleventh input busbar is connected to the gate of the nineteenth field-effect transistor.