KR100372684B1 - Sense amplifier for reading value of memory cell - Google Patents

Abstract

The present invention provides a sense amplifier for reading a memory cell value capable of operating in any situation by performing a read operation according to a DC voltage state without initialization of a timer.

Accordingly, the sense amplifier according to the present invention supplies a predetermined amount of current at all times and compares a low or high voltage set by comparing a voltage state of a current source unit grounded through the memory cell and a contact node of the current source unit and the memory cell. An inverter unit for outputting, a level shifting unit for maintaining an output state of the inverter unit, and an output unit for outputting an output signal in a state held constant by the level shifting unit, and according to a state of a DC voltage Allows reading of.

Description

Sense amplifier for reading memory cell values {SENSE AMPLIFIER FOR READING VALUE OF MEMORY CELL}

The present invention relates to a sense amplifier for reading a memory cell value, and more particularly, to a sense amplifier for reading a memory cell value operable without initialization of a timer.

In general, data input to a memory, for example, an erasable programmable read-only memory (EPROM) is stored in each memory cell, and reading data stored in the memory reads the value of each memory cell at the corresponding address.

In this case, a circuit called a sense amplifier is used to read each memory cell.

1 is a circuit diagram illustrating a conventional sense amplifier, and includes a plurality of timing signal input terminals nODOT, nOPRE, nOSA, ODIS, and ODOT, and a memory cell 11 as an output terminal at an appropriate time point by a combination of timing signals. ) Is configured to output the stored value.

That is, the timing diagram of the signal input to the input terminals nODOT, nOPRE, nOSA, ODIS, ODOT is shown in FIG.

Referring to FIGS. 1 and 2, the conventional operation of the sense amplifier will be described. In order to read the value of the memory cell 11, the sense amplifier is initialized according to a timing initialized by a power on reset. It should work.

That is, in the read mode, the nOPRE signal turns on the fifth transistor M5 to charge the node N1 and then into the nOSA signal inverted by the first and second transistors M1 and M2. The sixth transistor M6 is turned on to discharge the occupied node N1. In this case, when the value of the memory cell 11 is “low,” the memory cell 11 operates as an “on cell,” and thus, the node ( When the charge of N1 is discharged, the voltage of the node N1 is lowered, and conversely, when the value of the memory cell 11 is "high", the memory cell 11 is an 'off cell'. ', The charge of the node (N1) is not discharged, the voltage at the node (N1) is high.

Accordingly, the inverter circuit implemented by the eighth transistor M8 to the eleventh transistor M11 is operated using the ODOT signal and the nODOT signal, and outputs the value of the node N1 to the output terminal vout.

When the value is not read from the memory cell 11, the seventh transistor M7 is turned on by the ODIS signal to discharge the charge of the node N1 to the ground.

In the read mode, the VPX signal shown in FIG. 1 is a dc voltage for biasing the memory cell 11.

However, the conventional sense amplifier operating by the timing signal initialized by the above power on reset has a problem that the sense amplifier does not operate when the power on reset does not operate.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the conventional problems as described above, and its object is to provide a read operation according to a DC voltage state without initialization of a timer so that a memory cell value reading sense amplifier can operate in any situation. To provide.

1 is a circuit diagram showing a conventional configuration of a sense amplifier for reading memory cell values.

FIG. 2 is a timing diagram of an external clock signal for driving the conventional sense amplifier shown in FIG.

3 is a circuit diagram showing the configuration of a sense amplifier for reading memory cell values according to the present invention.

* Description of the symbols for the main parts of the drawings *

30: sense amplifier 31: current source unit

32: inverter section 33: level shifting section

34: output unit

As a construction means for achieving the above object of the present invention, the sense amplifier according to the present invention

A current source unit which supplies a constant amount of current at all times and is grounded through the memory cell;

An inverter unit configured to compare the voltage state of the contact node of the current source unit and the memory cell to output a low or high voltage;

A level shifting unit for maintaining an output state of the inverter unit; And

And an output unit for outputting an output signal in a state constantly maintained by the level sheeting unit.

2 is a circuit diagram showing the configuration of a memory cell reading sense amplifier according to the present invention;

The current source I outputs a certain amount of current and the first transistor M21 which connects the current source I and the memory cell in an always on state to supply a constant amount of current and is grounded through the memory cell. And the inverter circuits M22 and M23 connected to the input terminal of the contact point of the current source I and the first transistor M21 to the contact node of the current source part 31 and the memory cell 11. An inverter unit 32 for outputting a low or high voltage set by comparing voltage states, a fourth transistor M24 having a gate terminal connected to an output terminal of the inverter circuits M22 and M23, and a source terminal of which is grounded, and the inverter Between the drain terminal and the power supply terminal VDD of the seventh transistor M27 and the fourth transistor M24 and the seventh transistor M27 each having a gate terminal connected to the output terminal of the circuits M22 and M23 and grounded. 5,6 transistors provided in the emitter-source coupled to each other A level shifting unit 33 for maintaining the output state of the inverter unit 32, and a fifth transistor M25 and a seventh transistor M27 of the level shifting unit 33; It consists of an inverter circuit (M28, M29) and a buffer (I20) connected to the input terminal of the contact of the output section 34 for outputting the output signal of the state maintained constant by the level sheeting section (33).

Unlike the conventional sense amplifier, the sense amplifier configured as described above reads the value of the memory cell 11 according to the state of the dc voltage.

In a state in which the power sources VCC, VDD, and VSS are applied, the sense amplifier 30 operates in a read mode.

First, the node N20 is charged with the current source I providing a certain amount of current I. When the value of the memory cell 11 is HIGH, the memory cell 11 becomes 'off cell', and the node N20 is maintained in the charged state by the current supplied from the current source I.

On the contrary, when the value of the memory cell 11 is LOW, the value becomes 'on cell', and the current supplied from the current source I is in the on state of the first transistor M21 and the on state memory cell. Discharged by (11), and the voltage of the node N20 is kept low.

In the above-described sense amplifier circuit, although the node N1 has a current for charging or discharging only for a short time by timing control, in the circuit according to the present invention, since the current flows in a DC state, in order to reduce current consumption. VCC (1.2V), a voltage lower than VDD (3V), was used as a power source for the current source. In addition, in order to protect the memory cell 11, the bypass transistor M30 is manipulated so that the current continuously supplied from the current source I flows through the transistor M30.

When the voltage of the node N20 is high, the voltage opposite to the voltage state is output from the inverter unit 32 by the inverter circuits M22 and M23. When the voltage of the node N20 is low, The high voltage is output to the output terminals of the inverter circuits M22 and M23.

The voltage output from the inverter section 32 is output as a predetermined level signal by the level shifter 33, and the output voltage is inverted by the inverter circuits M28 and M29 of the output section 34 and the buffer I20. ), The value recorded in the memory cell 11 is output to the output terminal vout.

As described above, the sense amplifier is driven without inputting the timing signal to read the value of the memory cell, thereby eliminating the inability to read the value of the memory cell because the timing signal is not properly applied as in the prior art. There is always an excellent effect of stably reading the value of the memory cell.

Claims (3)

In the sense amplifier for reading the value of the memory cell, A current source unit which supplies a constant amount of current at all times and is grounded through the memory cell; An inverter unit configured to compare the voltage state of the contact node of the current source unit and the memory cell to output a low or high voltage; A level shifting unit for maintaining an output state of the inverter unit; And And an output unit for outputting an output signal in a state held constant by the level sheeting unit. The method of claim 1, The current source unit includes a current source I for outputting a predetermined amount of current, and a first transistor M21 connecting the current source I and a memory cell to be always on, The inverter unit is composed of inverter circuits M22 and M23 in which contacts of the current source I and the first transistor M21 are connected to an input terminal. The level shifting unit may include a fourth transistor M24 having a gate terminal connected to an output terminal of the inverter circuits M22 and M23 and a source terminal grounded, and a gate terminal connected to an output terminal of the inverter circuit M22 and M23 and having a source. 5th and 6th emitters source-coupled to the seventh transistor M27 having the ground connected to each other, and between the drain terminal and the power supply terminal VDD of each of the fourth transistor M24 and the seventh transistor M27. Consisting of transistors M25 and M26, The output unit is configured to read the value of the memory cell, characterized in that the inverter circuit (M28, M29) and the input terminal is connected to the contacts of the fifth transistor (M25) and the seventh transistor (M27) of the level shifting portion (I20). Sense amp. The method of claim 1, wherein the sense amplifier And a transistor (M30) for turning on / off by a bias voltage to bypass a current applied from the current source to the memory cell.