RU2573758C2 - Programmable logic device - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: device comprises a group of n inverters, n groups of transmitting transistors, a group 2n of inverters of setting, an output inverter, a group 2n of transistors of variables, a group 2n of transistors of shut-off of setting, an inverter of controlling the group of transistors of variables, a transistor of test control.

EFFECT: reduction of time of performance testing.

4 dwg, 9 tbl

Description

The invention relates to computer technology and can be used to calculate systems of logical functions in programmable logic integrated circuits (FPGA).

A programmable logic device is known that contains the first, second, and third groups of D-flip-flops of m · 2 ^{n each} (n is the number of input variables, m is the number of output functions), the third group of D-flip-flops of 2 (n-1) m, group m (n-1) AND elements, counter, a group of m · 2 ⁿ AND elements with three output states, a decoder, a group of m (n-1) OR elements, a second group of m · 2 ⁿ AND elements with three output states and m blocks calculation functions, each function calculating unit comprises a group 4 · 2 ⁿ elements and a tri-state output, two D-flip-flop, T rigger, RS-trigger pulse fixation five elements or three elements and four inverter, n groups of elements 2 x 2 NAND-OR (in each i-th group includes 2 ^n-1 elements, i = 1, n) , delay element, an additional group of AND elements with three states at the output (RF patent No. 2146840 dated 03.20.2000, class G11C 17/00, G06F 7/00).

A disadvantage of the known device is the high hardware costs, expressed in the number of transistors, for the implementation of a logical function in programmable logic integrated circuits (FPGAs).

The closest device of the same purpose to the claimed invention in terms of features is a programmable logic device containing a group of n inverters, n groups of transmitting transistors (n is the number of input variables), 2 ⁱ , i = 1, n transistors in a group, a group of 2 ⁿ inverters settings, output inverter, inputs of n variables, group of 2 ⁿ configuration inputs, device output,

moreover, the gate of each odd transistor of the i-th group of transmitting transistors i = 1, n is connected to the output of the i-th inverter of the group of n inverters, the gate of each even transistor of the i-th group of transmitting transistors is connected to the i-th input of the inputs of n variables, sources 2 ⁿ transistors of the n-th group are connected to the outputs of the inverters of a group of 2 ⁿ tuning inverters, the inputs of which are a group of 2 ⁿ tuning inputs, the drains of the even and odd transistors of the n-th group are combined and connected to the sources of the corresponding 2 ^n-1 transistors of the n-1 group whose drains dineny and connected to the sources of the respective 2 ^n-2 transistors are n-2nd group, and so on, flows past two transistors of group 1 are combined and connected to the input of an output inverter whose output is the output of the apparatus, inputs n variables connected to the inputs of the respective inverters from the group of n inverters (Stroganov A., Tsybin S. Programmable switching in FPGAs: an inside look // Components and Technologies. - 2010. - No. 11. P. 56-62 Fig. 9, 12 [Electronic resource]. - URL: http://www.kit-e.ru/articles/plis/2010_11_56.php 11/12/12)

A disadvantage of the known device adopted for the prototype is the high temporal complexity of the health check (diagnosis).

This is due to the following circumstances. The technical means of the prototype are oriented towards implementation, depending on the configuration of one particular logical function of n variables in perfect disjunctive normal form (SDNF). Therefore, in order to verify operability, in the general case, it is required to check the activation of all 2 ⁿ chains of transmitting transistors, that is, 2 ⁿ steps (cycles) are necessary. All 2 ⁿ sets of variable values to carry out such a check must be fixed on the corresponding n inputs of the device and the output reaction is evaluated - the implemented logical function.

тактов.In addition, it is necessary to check the implementation of all functions - this is necessary $$2^{2^n}$$

beats.

In this regard, essentially a complete enumeration of the values at the inputs of the device is required.

The objective of the invention is to reduce the time complexity of a health check (diagnosis) by introducing a "quick" diagnosis mode along with the usual diagnosis mode.

The problem was solved due to the fact that in the inventive device containing a group of n variable inverters, n groups of transmitting transistors (n is the number of input variables) 2 ⁱ , i = 1, n transistors in the group, a group of 2 ⁿ tuning inverters, output inverter, inputs of n variables, 2 ⁿ configuration inputs, device output,

moreover, the gate of each even transistor of the i-th group of n groups of transmitting transistors is connected to the i-th input of the inputs of n variables, the drains of the even and odd transistors of the n-th group are combined and connected to the sources of the corresponding 2 ^n-1 transistors of the n-1 group the drains of which are combined and connected to the sources of the corresponding 2 ^n-2 transistors of the n-2nd group and so on, the drains of the last two transistors of the 1st group are combined and connected to the input of the output inverter, the output of which is the output of the device, the inputs of n variables are connected to the entrance m corresponding inverters from the group of n inverters,

additionally introduced a group of 2 n variable transistors, a group of 2 ⁿ tuning off transistors, a variable transistor control inverter, a test control transistor, a signal reference input, diagnostic outputs, a test control input,

moreover, the sources of 2 ⁿ transistors of the nth group of 2 ⁿ are the diagnostic outputs of the device and are connected to the drains corresponding to 2 ⁿ transistors of the group 2 ⁿ tuning off transistors, the sources of which are connected to the outputs of the corresponding inverters of the group 2 ⁿ tuning inverters, the inputs of which are group 2 ⁿ tuning inputs, gates of transistors of group 2 ⁿ transistors of disconnecting settings connected to the gates of odd transistors of group 2 n transistors of variables and to the output of the inverter control group trans sources, and the gates of even transistors of group 2 n variable transistors are connected to the test control input, the input of the control inverter group of variable transistors, the signal input input is connected to the source of the test control transistor, the drain of which is connected to the input of the output inverter, and the gate of the test control transistor is connected to the input test management.

Signs of the prototype, coinciding with the essential features of the claimed invention, the following:

contains a group of n variable inverters, n groups of transmitting transistors (n is the number of input variables) of 2 ⁱ , i = 1, n transistors in a group, a group of 2 ⁿ tuning inverters, an output inverter, n variable inputs, 2 ⁿ tuning inputs, a device output .

The features of the proposed technical solution, distinguishing from the prototype, are as follows: contains a group of 2 n variable transistors, a group of 2 ⁿ tuning off transistors, a control group of variable transistors, a test control transistor, a signal input, diagnostic outputs, a test control input.

Distinctive features in combination with the known ones reduce the time complexity of operability (diagnosis) testing by simultaneously checking all transistors in n groups of transmitting transistors using additional variable transistors, using a group of 2 ⁿ tuning transistors, an inverter controlling a group of variable transistors, a test control input, an input signal settings, diagnostic outputs, test control input.

The introduction of a group of 2 n transistors of variables allows one to provide activation (setting to a state of a logical unit) of the gates of all or individual transistors in n groups of transmitting transistors by signals at the inputs of n variables.

The introduction of a group of 2 ⁿ tuning off transistors allows you to disable the outputs of the inverters of a group of 2 ⁿ tuning inverters to evaluate the results of supplying a reverse signal simultaneously for all transistors in n groups of transmitting transistors.

The introduction of an inverter to control a group of variable transistors allows you to block the outputs of inverters in a group of n variable inverters to provide a “quick” diagnosis.

The introduction of the test control transistor allows during the “quick” diagnostic mode to apply a reverse signal passing through all the transistors in n groups of transmitting transistors from the input of the signal reference.

The introduction of the input signal assignment allows you to apply the test signal "unit" or "zero" through the test control transistor, which passes through all the transistors in n groups of transmitting transistors.

The introduction of diagnostic outputs makes it possible to remove the output response to test signals both in the proposed “fast” diagnostic mode — to assess the passage of the test across all transistors in n groups of transmitting transistors, and in conventional diagnostic mode — to evaluate the performance of inverters in a group of 2 ⁿ tuning inverters .

The introduction of the test control input allows you to switch the test modes from normal (at the test control input - “zero”) to “quick” diagnostics (at the test control input - “one”).

Changing the connections in comparison with the known device provides the implementation of both a calculation mode of logic functions programmed for the inputs and diagnostics — usual in the transistor tree — along one of the branches in n groups of transmitting transistors, as well as “quick” diagnostics.

In FIG. 1 shows an electrical structural diagram of a programmable logic device.

In FIG. 2 shows a graph of changes in relative hardware costs in transistors of a programmable logic device compared to the prototype.

In FIG. 3. shows a graph of the Markov circuit of a programmable logic device.

In Fig 4. shows a graph of the availability coefficient of the prototype KG2 depending on the increase in the test time k T3 compared with the availability factor of the proposed device KG1 with λ = 10 ^-9 ; µ = 10 ⁻³ ; ξ = 1.7; T _d = 10 ^-4 ; T ₃ = 10 ^-7 .

The programmable logic device contains a group of n inverters of variables 1, n groups of transmitting transistors 2 (n is the number of input variables) 2 ⁱ , i = 1, n transistors in a group, a group of 2 ⁿ inverters 3, an output inverter 4, inputs of n variables 5 , 2 ⁿ tuning inputs 6, device 7 output, group 2n variable transistors 8, group 2 ⁿ tuning off transistors 9, variable transistor control inverter 10, test control transistor 11, signal input 12, diagnostic outputs 13, test control input 14 .

The gate of each even transistor of the i-th group 2.i of n groups of transmitting transistors 2 is connected to the i-th input of the inputs of n variables 5.i.

The flows of even and odd transistors of the n-th group 2.n are combined and connected to the sources of the corresponding 2 ^n-1 transistors of the n-1st group 2.n-1, the drains of which are combined and connected to the sources of the corresponding 2 ^n-2 transistors of n- 2nd group 2.n-2 and so on, the drains of the last two transistors of the 1st group 2.1 are combined and connected to the input of the output inverter 4.

The output of the inverter 4 is the output of the device 7.

The inputs of i-x inverters of the group of n inverters of variables 1.i are connected to the corresponding i-th inputs of the inputs of n variables 5.i.

The gate of each odd transistor of the i-th group 2.i of the transmitting transistors 2 i = 1, n is connected to the combined sources of the corresponding odd and even transistors of the group 2 n transistors of variables 8, the odd of which is connected to the output of the i-th inverter of the group of n variable inverters 1 .i, and the even of which is connected to the i-th input of the inputs of n variables 5.i.

The sources of 2 ⁿ transistors of the n-th group 2.n of 2 ⁿ are the diagnostic outputs 13 of the device and are connected to the drains of the corresponding 2 ⁿ switching transistors of setting 9, the sources of which are connected to the outputs of the corresponding inverters of group 2 ^{n of the} inverters of setting 3, the inputs of which are group 2 ⁿ setting inputs 6.

The gates of the transistors of group 2 ^{n of the} off-switch transistors 9 are connected to the gates of the odd transistors of the group 2n of transistors of variables 8 and to the output of the inverter 10 of the control group of transistors.

The gates of the even transistors of the group 2n transistors of the variables 8 are connected to the control input of the test 14 and the input of the inverter 10 of the control of the group of variable transistors.

The input signal 12 is connected to the source of the transistor of the reverse 11, the drain of which is connected to the input of the output inverter 4, and the gate of the transistor of the reverse 11 is connected to the control input of the test 14.

The programmable logic device operates in the following modes:

1) programming; 2) calculation; 3) routine testing; 4) “quick” testing.

The device can also be used after failure detection in the proposed manner - in the mode of limited functionality.

1) Programming. In this mode, the device works similarly to the prototype. Logic zero is set at the test control input 14, which leads to the activation of the gates of the odd transistors in the group of 2 variable transistors 8 through the control inverter of the group of transistors of the variable 10, the gates of the group of 2 ⁿ transistors to turn off the settings, while the even transistors in the group of 2n transistors of the variable 8 are turned off, turned off and a test control transistor 11. When this via external to the device hardware into 2 ⁿ inputs setting 6 set the logic levels corresponding to logical tion function of n variables, which is necessary to calculate (given the truth table of the logical function n variables comprising 2 ⁿ rows). So, for the implementation of the addition function modulo two (exclusive OR) four variables (n = 4) x4⊕х3⊕х2⊕х1, where xi is the signal at inputs 5.4, 5.3, 5.2, 5.1 - at inputs 6 (6.0 ... 6.15) the following logical levels are established (A. Stroganov, S. Tsybin. Programmable switching in FPGAs: an inside view // Components and Technologies. - 2010. - No. 11. P. 56-62 Fig. 9 [Electronic resource]. - URL: http: //www.kit-e.ru/articles/plis/2010_11_56.php Date of treatment 01/12/13 g) - Table. one

At the outputs of inverters of group 2 ⁿ inverters of setup 3, values are set that are inverse to the logic levels set at 2 ⁿ inputs of setup 6.

2) Calculation. In this mode, a logic zero is set at the test control input 14, which leads to the activation of the gates of the odd transistors in the group of 2n transistors of variables 8 through the inverter to control the group of transistors of variables 10, the gates of the group of 2 ⁿ transistors to turn off the settings 9, with even transistors to the group of 2 n transistors variables 8 are disabled, and the transistor control test 11 is disabled. Therefore, the device works similarly to the prototype.

When n variables 5 are received at the inputs using some of 2 ⁿ sets external to the device (table 1 - 5.4 ... 5.1) one of 2 ⁿ chains in n groups of 2 transmitting transistors is activated (even transistors directly from the corresponding input n variables 5, if it is equal to a logical unit, odd ones through the corresponding inverter of the group of n variable inverters 1 and an odd transistor of the group 2 n variable transistors 8, if it is zero) from the output of the corresponding inverter of the group 2 ⁿ inverters for 3 hours Through the transistors of group 2 ⁿ transistors disconnect settings 9, through the output inverter 4 to the output of the device 7.

So, when n variables 5 of set 0101 (set No. 5) are received at the inputs, the “even transistor” chain is “dialed” 2.4.6-2.3.3-2.2.2-2.1.1 from input 6.5, on which a logical zero is set, through inverter 3.6, through inverter 4 - and output 7 forms a logical zero: 0⊕1⊕0⊕1 = 0.

3) Routine testing. In this mode, a logic zero is set at the test control input 14, which leads to the activation of the gates of the odd transistors in the group of 2n transistors of variables 8 through the inverter to control the group of transistors of the variables 10, the gates of the group of ²ⁿ transistors of the off setting 9, and even transistors in the group of 2n transistors of variables 8 are disabled, the transistor control test 11 is disabled. Therefore, the device operates similarly to the prototype.

Using technical means external to the device, at 2 ⁿ inputs of setting 6, logical levels are set that correspond to some test logic function of n variables that needs to be calculated (the truth table of a given logical function of n variables containing 2 ⁿ rows).

Then, on the inputs of n variables 5, with the help of technical means external to the device, all 2 ⁿ sets are fed in turn. All 2 ⁿ circuits in n groups of transmitting transistors are activated from the output of the corresponding inverter of group 2 ⁿ tuning inverters 3, through group 2 ⁿ tuning off transistors 9, through output inverter 4 to the output of device 7, by which technical means external to the device evaluate the operability devices.

In general, there should be several test functions to eliminate the possible incorrect influence of different sets on each other, both in group 2 ⁿ tuning inverters 3 and in n groups 2 of transmitting transistors (all zeros, all ones, alternating zeros and ones, etc.) . Therefore, in the general case, more than 2 ⁿ cycles are required.

The status of group 2 ⁿ tuning inverters can be monitored using diagnostic outputs 13.

4) "Quick" testing

In this mode, the logic unit is set at test control input 14, which activates the gates of even transistors in group 2n of variable 8 transistors, the odd transistors in group 2n of variable 8 transistors are turned off, and the transistors of group ^{2n of} transistors of setting off 9. The transistor shutter is activated. test control 11, through which the test logic level comes from the test control input.

Disconnected odd transistors in group 2n transistors of variables 8 lead to the fact that the odd transistors of n groups of transmitting transistors 2 (n is the number of input variables) receive 2 ⁱ , i = 1, n transistors in the group, the same signal from the corresponding input of n inputs variables 5.

The disconnected transistors of group 2 ^{n of} the tuning off transistors 9 disconnect the outputs of the inverters of group 2 ^{n of the} tuning inverters 3 and the status of the last nth group of n groups of transmitting transistors 2 can be observed at the diagnostic outputs 13 using technical means external to the device.

Logical units are set on n inputs of variables 5 (for example, 1111 for n = 4), which activate the gates of all transistors of n groups of transmitting transistors 2 through even transistors of group 2n of transistors of variables.

When using the technical means external to the device for inputting the signal 12 of the test signal “logical unit” to the diagnostic outputs 13 using external technical means, 2 ⁿ logical units should be observed, and when applying using external the device hardware to "logical zero" reference input signal 12 to the diagnostic test signal output 13 via external to the hardware device should be observed 2 ⁿ logical Beehive in the absence of failures.

To check the absence of failures of the “constant unit on gate” type in transistors of n groups of transmitting transistors 2, n sets with one zero in one of n positions can be fed to the inputs and variables 5, for example, 1110, 1101, 1011, 0111 for n = 4.

5) Limited functionality mode

The mode is set upon detection, as a rule, of one failure according to the test results.

If one failure is detected in the tree of transmitting transistors, n groups of transmitting transistors 2 or inverters of group 2 ⁿ inverters of tuning 3, it is possible to use a “half” device - a working half.

This is achieved by a constant signal at the highest input from the inputs of n variables 5 and using the device to implement the functions of the n-1 variable. Then the corresponding half of the tuning inputs and transistors of a group of 2 ⁿ tuning inverters is used. For example, with a workable upper half of transistors of n groups of transmitting transistors 2, it is possible to configure for the addition function modulo two (exclusive OR) three variables (n = 3) instead of four - Table. 2.

With a working lower half of the transistors n groups of transmitting transistors 2 - Tab. 3.

Such a setting is also possible when detecting failures of the “constant zero”, “constant unit” type on the highest input 5.4.

Upon detection of an additional failure to the above failure, failure at input 5.3, or in inverter 1.3, of a group of n variable inverters relative to Tab. 2 the following settings are required - Tab. 4, 5.

If an additional failure is detected at input 5.2, or in inverter 1.2, a group of n variable inverters relative to Tab. 2 the following settings are required - Tab. 6, 7.

If an additional failure is detected at input 5.1, or in inverter 1.1, a group of n variable inverters relative to Table 3 The following settings are required - Tab. 8, 9.

Evaluation of technical and economic efficiency

The technical means of the prototype in the general case provide testing by checking the implementation of a single logical function in T ₂ = 2 ⁿ steps (cycles) with fixing at the output 7 of one of 2 ⁿ values of the logical function. This corresponds to the exponential complexity of testing.

In the proposed device, two clock cycles are required to check the passage of the logic 0, logic 1 signals for the diagnostic outputs 13 across all transistors of groups 2 of the signal.

To check the absence of failure, the “constant unit” on the gates of the transistors of groups 2, an additional test “running zero” at the inputs of n variables 5 is possible - complexity n.

To check the group of n variable inverters in the usual testing mode, an additional “running zero” guest test is also possible on the inputs of n variables 5 - complexity n.

In the usual test mode, the status of a group of 2 ⁿ tuning inverters by the diagnostic outputs 13 can also be checked.

Thus, we get a test of linear complexity:

Thus, the decrease in the time complexity of the health check (diagnosis) is determined by the expression:

So, for n = 4 we get:

For n = 5 we get:

For n = 6 we get:

For n = 7 we get:

However, the hardware cost in the proposed device is higher than in the prototype.

We show that the positive effect of reducing the time complexity of diagnosis exceeds the negative consequences of a slight increase in hardware costs.

Hardware costs of the prototype in the number of transistors are described by the expression:

where 2 ^{n + 1} -2 transistors in n groups of transmitting transistors 2 (n is the number of input variables) but 2 ⁱ , i = 1, n transistors in a group, 2 · 2 ⁿ transistors in a group of 2 ⁿ tuning inverters 3 (two transistors on inverter), 2 · n + 2 transistors in the group of n variable inverters and in the output inverter.

In the proposed device in addition to (7) introduced:

transistors, where 2 ⁿ transistors in a group of 2 ⁿ transistors disable settings 9,2 · n transistors in a group of 2n variable transistors plus an inverter controlling a group of variable transistors (2 transistors) plus a test control transistor.

Total we get in the proposed device the following number of transistors:

Then the relative hardware costs in the transistors for the modification of the prototype for the purpose of "quick" diagnosis for various n are the expression:

In FIG. Figure 2 shows a graph of the changes in the relative hardware costs in transistors for "fast" diagnosis for various n.

We see that the relative hardware costs decrease with increasing n and for very large n become less than 10%.

Let us evaluate the reliability indicator — the availability coefficient using the Markov model of a programmable logic device with “quick” diagnosis.

Consider the Markov model of a programmable logic device with "quick" diagnosis (Fig. 3).

Peak 1 is the state of operability (probability of P1), peak 2 is the state of failure (probability P2), λ ₁₂ is the failure rate, μ ₂₁ is the recovery rate, peak 3 is the state of testing and diagnosis (probability P3), to which intensity

, $${\mathrm{<figure-callout\; id="13"\; label="\lambda "\; filenames="00000038.png"\; state="\{\{state\}\}">\lambda </figure-callout>}}_{13}=\frac{\mathrm{one}}{T_d}$$

,

 where Td is the frequency of diagnosis,

, $${\mu }_{31}=\frac{\mathrm{one}}{{\mathrm{<figure-callout\; id="3"\; label="T"\; filenames="00000038.png"\; state="\{\{state\}\}">T</figure-callout>}}_3}$$

,

where T3 is the test time, λ ₃₂ is the failure rate during testing.

Let µ ₂₁ be the recovery intensity determined, for example, by the speed of the procedure for replacing the backup device. We assume that λ ₁₂ = λ ₃₂ .

We obtain a solution to the corresponding system of Kolmogorov algebraic equations for the steady state:

. Какой ценой? Ценой увеличения λ₁₂=λ₃₂.What is expressed by "speed"? In reducing T3 - the time taken to pass the test, that is, in increasing $${\mu }_{31}=\frac{\mathrm{one}}{{\mathrm{<figure-callout\; id="3"\; label="T"\; filenames="00000038.png"\; state="\{\{state\}\}">T</figure-callout>}}_3}$$

. At what price? At the cost of increasing λ ₁₂ = λ ₃₂ .

It is necessary to establish whether this approach will lead to an increase in the availability factor K _G = P ₁ ? We obtain the availability factor K _G = P ₁ (λ, µ).

Express K _G = P ₁ from the second equation in terms of P ₂ , P ₃ :

Next, from the third equation:

From the fourth we get:

I.e:

Express K _G = P ₁ (λ, µ):

,

,

.

.

Thus, we obtain:

Given λ ₁₂ = λ ₃₂ = λ, μ ₂₁ = μ we obtain the availability factor:

Consider the increase in testing time T3 of the prototype k times:

Consider a slight increase in the failure rate with the introduction of additional equipment from the proposed device:

In FIG. Figure 4 shows graphs for some values of λ, µ, ξ, T _d , T ₃ depending on k.

We see that a 70% diagnostic acceleration (ξ = 1.7) provides a higher availability factor even with a 70% increase in failure rate (k).

The achievement of the technical result of the invention is confirmed by the above estimates.

Claims (1)

A programmable logic device containing a group of n variable inverters, n groups of transmitting transistors (n is the number of input variables) 2 eachⁱ, i = 1, n transistors in a group, group 2ⁿ inverters settings, output inverter, inputs of n variables, 2ⁿ setting inputs, device output, and the gate of each even transistor of the i-th group of n groups of transmitting transistors is connected to the i-th input of the inputs of n variables, the drains of the even and odd transistors of the n-th group are combined and connected to the sources of the corresponding 2^n-1 transistors of the n-1st group, the drains of which are combined and connected to the sources of the corresponding 2^n-2 transistors of the n-2nd group, transistors in the groups n-3, n-4 ... 2 are connected in the same way, the drains of the last two transistors of the 1st group are combined and connected to the input of the output inverter, the output of which is the output of the device, the inputs of n variables are connected to the inputs of the corresponding inverters from the group of n inverters, characterized in that the group 2n transistors of variables is additionally introduced into it, group 2ⁿ tuning off transistors, a variable transistor group control inverter, a test control transistor, a signal reference input, diagnostic outputs, a test control input, and sources 2ⁿ group 2 transistorsⁿ are diagnostic outputs of the device and are connected to drains corresponding of 2ⁿ group 2 transistorsⁿ setting off transistors, the sources of which are connected to the outputs of the corresponding inverters of group 2ⁿ inverters settings, the inputs of which are group 2ⁿ tuning inputs, gates of transistors of group 2ⁿ disconnection transistors are connected to the gates of odd transistors of a group of 2n variable transistors and to the output of a transistor group control inverter, and the gates of even transistors of a group of 2n variable transistors are connected to a test control input, a variable transistor group control inverter input, a signal reference input is connected to the source of a test control transistor , the drain of which is connected to the input of the output inverter, and the gate of the test control transistor is connected to the test control input.

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