RU2547229C1 - Programmable logic device - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: device comprises a group of n inverters for variables, n groups of transmitting transistors, n is number of input variables, up to 2ⁱ, i=1, n transistors in a group, group of 2ⁿ adjustment inverters, output inverter, inputs of n variables, 2ⁿ of adjustment inputs, group of 2ⁿ for switching adjustment off, auxiliary inverters, transistors for switching alternative circuit on, a group of six auxiliary transmitting transistors, supply voltage input, "Zero Volt" input, error output, output of the device.

EFFECT: improved reliability of functioning due to control of correct computation of the preset logic function in process of operation.

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Description

The invention relates to computer technology and can be used to calculate systems of logical functions in programmable logic integrated circuits (FPGA).

A programmable logic device is known that contains the first, second, and third groups of D-flip-flops of m · 2 ^{n each} (n is the number of input variables, m is the number of output functions), the third group of D-flip-flops of 2 (n-1) m, group m (n-1) AND elements, counter, a group of m · 2 ⁿ AND elements with three output states, a decoder, a group of m (n-1) OR elements, a second group of m · 2 ⁿ AND elements with three output states and m blocks calculation functions, each function calculating unit comprises a group 4 · 2 ⁿ elements and a tri-state output, two D-flip-flop, T rigger, RS-trigger pulse fixation five elements or three elements and four inverter, n groups of elements 2 x 2 NAND-OR (in each i-th group includes 2 ^n-1 elements, i = 1, n) , delay element, an additional group of AND elements with three states at the output (RF patent No. 2146840 dated 03.20.2000, class G11C 17/00, G06F 7/00).

A disadvantage of the known device is the high hardware costs, expressed in the number of transistors, for the implementation of a logical function in programmable logic integrated circuits (FPGAs).

The closest device of the same purpose to the claimed invention in terms of features is a programmable logic device containing a group of n inverters, n groups of transmitting transistors (n is the number of input variables), 2 ⁱ , i = 1, n transistors in a group, a group of 2 ⁿ inverters setting output inverter, the inputs n variables, the group setting 2 ⁿ inputs, the output device, wherein the gate of each transistor odd i-th group of transmission transistors i = 1, n is connected to the output of i-th inverter group of inverters n, each gate etnogo transistor i-th group transmitting transistors connected to i-th entry of inputs n variables sources 2 ⁿ transistors n-th group are connected to the outputs of inverters group 2 ⁿ configuration inverters, inputs of which are a group of 2 ⁿ input control, drains the odd and even transistors of the nth group are combined and connected to the sources of the corresponding 2 ^n-1 transistors of the n-1st group, the drains of which are combined and connected to the sources of the corresponding 2 ^n-2 transistors of the n-2nd group and so on, the drains of the last two transistors 1 groups united and connected s to an input of an output inverter whose output is the output of the apparatus, the variables n inputs are connected to the inputs of respective inverters of group n inverters setting 2 ⁿ inputs are connected to the inputs of respective inverters of a group setting 2 ⁿ inverters (Stroganov, S. Programmable switching Tsybin in FPGAs: an inside look // Components and Technologies. - 2010. - No. 11. S.56-62. Fig. 9, 12 [Electronic resource].

- URL: http://www.kit-e.ru/articles/plis/2010_11_56.php 11/12/12 g).

Signs of the prototype, which coincides with the essential features of the claimed invention: contains a group of n variable inverters, n groups of transmitting transistors (n is the number of input variables) of 2 ⁱ , i = 1, n transistors in a group, a group of 2 ⁿ tuning inverters, an output inverter, inputs n variables, 2 ⁿ settings inputs, device output; the gate of each even transistor of the i-th group of n groups of transmitting transistors is connected to the i-th input of the inputs of n variables; the gate of each odd transistor of the i-th group of n groups of transmitting transistors is connected to the output of the i-th inverter from the group of n variable inverters; the drains of the even and odd transistors of the nth group are combined and connected to the sources of the corresponding 2 ^n-1 transistors of the n-1st group, the drains of which are combined and connected to the sources of the corresponding 2 ^n-2 transistors of the n-2nd group and so on; the drains of the last two transistors of the first group are combined and connected to the input of the output inverter, the output of which is the output of the device; the inputs of n variables are connected to the inputs of the corresponding inverters from the group of n inverters, 2 ⁿ settings inputs are connected to the inputs of the corresponding inverters from the group of 2 ⁿ settings inverters.

A disadvantage of the known device adopted for the prototype is the low reliability.

This is due to the following circumstances. The technical means of the prototype are oriented towards implementation, depending on the configuration of one particular logical function of n variables in perfect disjunctive normal form (SDNF). The verification of the correctness of the calculation of a logical function can be carried out only if the device is not used for its intended purpose. This is the so-called test control. Then, in order to check the operability, in the general case, it is required to check the activation of all 2 ⁿ chains of transmitting transistors, that is, 2 ⁿ steps (cycles) are necessary. All 2 ⁿ sets of variable values to carry out such a check must be fixed on the corresponding n inputs of the device and the output reaction, the implemented logical function, must be evaluated. In addition, it is necessary to check the implementation of all functions - this requires 2 ²ⁿ clock cycles. Thus, essentially complete enumeration of the values at the inputs of the device is required. The device does not provide any control during the operation of the device (that is, it does not provide for “working” control, control during the intended operation). In this regard, the reliability of the functioning of the prototype is equal to the probability of uptime.

The objective of the invention is to increase the reliability of functioning by checking the correctness of the calculation of a given logical function in the process, the functioning of the device as intended (by working control, functional control).

The problem was solved due to the fact that in the inventive device containing a group of n variable inverters, n groups of transmitting transistors (n is the number of input variables) 2 ⁱ , i = 1, n transistors in the group, a group of 2 ⁿ tuning inverters, output inverter, inputs of n variables, 2 ⁿ configuration inputs, device output, and the gate of each even transistor of the i-th group of n groups of transmitting transistors is connected to the i-th input of inputs of n variables, the gate of each odd transistor of the i-group transistors connected to the output of the i-th inverter from the group of n variable inverters, the drains of the even and odd transistors of the n-th group are combined and connected to the sources of the corresponding 2 ^n-1 transistors of the n-1 group, the drains of which are combined and connected to the sources of the corresponding 2 ^n-2 transistors of the n-2nd group, transistors in the groups n-3, n-4 ... 2 are connected in a similar way, the drains of the last two transistors of the first group are combined and connected to the input of the output inverter, the output of which is the output of the device, the inputs of n variables are connected to the inputs of the corresponding inverters and of the group of n inverters, 2 ⁿ tuning inputs are connected to the inputs of the corresponding inverters from the group of 2 ⁿ tuning inverters, according to the invention, it additionally includes a group of 2 ⁿ tuning shutdown transistors, the first, second, third, fourth additional inverters, the first and second alternative transistors chains, a group of six additional transmitting transistors, the input of the supply voltage, the input "Zero volts", the output of the error, and the sources of the transistors of the group 2 ⁿ transistors off settings are connected to the outputs of the corresponding inverters from group 2 ⁿ tuning inverters, and the drains of transistors of group 2 ⁿ switching transistors are connected to the sources of transistors of the n-th group of transmitting transistors, the gates of the first half of transistors from group 2 ⁿ switching transistors are connected to the first input of n variable inputs, which is also connected to the gate of the second transistor connecting alternate chains, gates of transistors of the second half of the group 2 ⁿ setting the sleep transistors are connected to the outputs of the first of the inverter from the group of n variable inverters, which is also connected to the gate of the first transistor for connecting an alternative circuit, the source of the first transistor for connecting an alternative circuit is connected to the combined drains of the last - even and penultimate - odd transistors of the second group of n groups of transmitting transistors, the source of the second transistor for connecting an alternative the circuit is connected to the combined drains of the first - odd and second - even transistors of the second group of n groups of transmitting transistors , the drains of the first and second transistors connecting an alternative circuit are combined and connected to the input of the second additional inverter, the output of which is connected to the input of the third additional inverter, the output of which is connected to the gates of the third and fifth transistors from the group of six additional transmitting transistors, the sources of which are connected to the input "Zero volt ", the output of the second additional inverter is connected to the gates of the fourth and sixth transistors from the group of six additional transmitting transistors, the sources of which are connected to the input of the supply voltage, the combined drains of the fifth and sixth transistors from the group of six additional transmitting transistors are connected to the source of the second transistor from the group of six additional transmitting transistors, the gate of which is connected to the output of the device and the input of the first additional inverter, the combined drains of the third and fourth transistors from a group of six additional transmitting transistors connected to the source of the first transistor from a group of six additional transmitting their transistors, the gate of which is connected to the output of the additional inverter, the drains of the first and second transistors from the group of six additional transmitting transistors are combined and connected to the input of the fourth inverter, the output of which is the output of the device error, the drains of each i-th transistor of the first half of the transistors from group 2 ⁿ disconnection transistors settings are connected to the drains of the corresponding i + 2 ^n-1 transistors from the second half of transistors from the group of adjustment transistors.

Signs of the proposed technical solution, distinctive from the prototype: contains a group of 2 ⁿ turn-off transistors, the first, second, third, fourth additional inverters, the first and second transistors connecting an alternative circuit, a group of six additional transmitting transistors, the input voltage, the input is zero volt ", Error output; the sources of the transistors of group 2 ⁿ tuning off transistors are connected to the outputs of the corresponding inverters from the group of 2 ⁿ tuning inverters, and the drains of the transistors of 2 ⁿ tuning tuning transistors are connected to the sources of transistors of the n-th group of transmitting transistors; the gates of the first half of the transistors from the group of 2 ⁿ tuning off transistors are connected to the first input of the n variable inputs, which is also connected to the gate of the second transistor connecting the alternative circuit; the gates of the second half of the transistors from the group of 2 ⁿ tuning off transistors are connected to the output of the first inverter from the group of n variable inverters, which is also connected to the gate of the first transistor connecting the alternative circuit; the source of the first alternate connection transistor is connected to the combined drains of the last — even and penultimate — odd transistors of the second group of n groups of transmitting transistors; the source of the second alternate connection transistor is connected to the combined drains of the first - odd and second - even transistors of the second group of n groups of transmitting transistors; the drains of the first and second alternate connection transistor are combined and connected to the input of the second additional inverter, the output of which is connected to the input of the third additional inverter, the output of which is connected to the gates of the third and fifth transistors from the group of six additional transmitting transistors, the sources of which are connected to the input "Zero volts "; the output of the second additional inverter is connected to the gates of the fourth and sixth transistors from the group of six additional transmitting transistors, the sources of which are connected to the input of the supply voltage, the combined drains of the fifth and sixth transistors from the group of six additional transmitting transistors are connected to the source of the second transistor from the group of six additional transmitting transistors, the shutter of which is connected to the output of the device and the input of the first additional inverter; the combined drains of the third and fourth transistors from the group of six additional transmitting transistors are connected to the source of the first transistor from the group of six additional transmitting transistors, the gate of which is connected to the output of the additional inverter; the drains of the first and second transistors from the group of six additional transmitting transistors are combined and connected to the input of the fourth inverter, the output of which is the error output of the device; the drains of each i-th transistor of the first half of transistors from a group of 2 ⁿ tuning off transistors are connected to the drains of the corresponding i + 2 ^n-1 transistors from the second half of transistors from a group of tuning off transistors.

Distinctive features in combination with the known ones allow to increase the reliability of functioning by checking the correctness of the calculation of a given logical function during operation by using the second half of the transistors that are not used on this set of input variables.

The introduction of a group of 2 ⁿ tuning off transistors allows transmitting training signals with the half of the n transmitting transistors currently used for calculations to the unused half for the purpose of monitoring calculations.

The introduction of the first additional inverter allows the inversion of the value of the calculated logical function for subsequent comparison with the control value calculated on the unused half of n groups of transmitting transistors.

The introduction of the second additional inverter allows you to get the control value calculated on the unused half of n groups of transmitting transistors of the logical function.

The introduction of the third additional inverter allows the inversion of the control value calculated on the unused half of n groups of transmitting transistors of a logical function.

The introduction of the fourth additional inverter allows you to get the value of the error signal using a group of six additional transmitting transistors.

The introduction of a group of six additional transmitting transistors allows us to calculate the value of the error signal when not comparing the calculated value of the logical function with the control value calculated on the half-currently unused logical transistor groups of the logical function by implementing modulo-two addition (exclusive OR).

The introduction of the first alternate connection transistor allows you to connect at a zero logic level on the first, highest input of n variables, the control value of the logical function, calculated on the unused half of the n groups of transmitting transistors of the logical function.

The introduction of the second alternate connection transistor allows you to connect at a logical level at the first, highest input of n variables, the control value of the logical function, calculated on the unused half of the n groups of transmitting transistors of the logical function.

The introduction of the supply voltage input allows you to configure a group of six additional transmitting transistors to implement the function of adding modulo two (exclusive OR) - with the same calculated values - the control and the main input of the fourth additional inverter is supplied with a unit, and therefore an error signal is sent to the corresponding output of the device not served.

The introduction of the “Zero volt” input allows you to configure a group of six additional transmitting transistors to implement the addition function modulo two (exclusive OR) - for different calculated values - the control and the main input of the fourth additional inverter is supplied with a logical zero, in connection with which an error signal is generated on the corresponding output of the device.

The introduction of an error output allows the error signal to be transmitted to equipment external to the device.

In FIG. 1 depicts an electrical schematic diagram of a programmable logic device.

In FIG. 2 shows graphs of changes in the probability of failure of the prototype (P1) and the proposed device (P2) taking into account the exponential model of failures (failures) and the failure rate of a single transistor λ = 10 ^-7 at n = 4.

In FIG. 3 shows graphs of changes in the probability of failure of the prototype (P1) and the proposed device (P2) taking into account the exponential model of failures (failures) and the failure rate of a single transistor λ = 10 ^-7 at n = 5.

In FIG. 4 shows graphs of changes in the probability of failure of the prototype (P1) and the proposed device (P2) taking into account the exponential model of failures (failures) and the failure rate of a single transistor λ = 10 ^-7 at n = 6.

In FIG. 5 shows graphs of changes in the probability of failure of the prototype (P1) and the proposed device (P2) taking into account the exponential model of failures (failures) and the failure rate of a single transistor λ = 10 ^-7 at n = 7.

The programmable logic device (Fig. 1) contains a group of n inverters of variables 1, n groups of transmitting transistors 2.i (n is the number of input variables) of 2 ⁱ , i = 1, n transistors in a group, a group of 2 ⁿ inverters 3, output inverter 4, n variable inputs 5, 2 ⁿ tuning inputs 6, device output 7, group 2 ⁿ switching off transistors 8, first 9, second 10, third 11, fourth 12 additional inverters, first 13 and second 14 transistors connecting an alternative circuit, a group of six additional transmitting transistors 15.1, 15.2, 15.3, 15.4, 15.5, 15.6, input voltage supply 16, input "Zero volts" 17, error output 18.

The gate of each even transistor of the i-th group 2.i of n groups of transmitting transistors is connected to the i-th input of 5 l of inputs of n variables, the gate of each odd transistor of the i-th group 2.i of n groups of transmitting transistors is connected to the output of the i-th inverters 1.i from the group of n inverters of variables 1, the drains of even and odd transistors of the n-th group 2.n are combined and connected to the sources of the corresponding 2 ^n-1 transistors of the n-1st group, the drains of which are combined and connected to the sources of the corresponding 2 ^n-2 transistors n-2 of the second group and so on, the last two drains transit tors group 1 are combined and connected to the input of the inverter output 4 whose output is an output device 7.

The inputs of n variables 5 are connected to the inputs of the corresponding inverters from the group of n inverters 1, 2 ⁿ tuning inputs inputs 6 are connected to the inputs of the corresponding inverters from the group of 2 ⁿ tuning inverters 3.

The sources of the transistors of group 2 ⁿ tuning transistors are connected to the outputs of the corresponding inverters from the group of 2 ⁿ tuning inverters, and the drains of the transistors of group 2 ⁿ tuning transistors are connected to the sources of the transistors of the n-th group of transmitting transistors 2.n.

The gates of the first half of transistors 8.1-8.2 ^n-1 from the group of 2 ⁿ off-switch transistors 8 are connected to the first input 5.1 of the inputs of n variables 5, which is also connected to the gate of the second transistor 14 connecting an alternative circuit.

The gates of the second half of the transistors 8.2 ^n-1 -8.2 ⁿ from group 2 ^{n of the} off-switch transistors 8 are connected to the output of the first inverter 1.1 from the group n of variable inverters 1, which is also connected to the gate of the first 13 transistor connecting an alternative circuit.

The source of the first 13 transistor connecting an alternative circuit is connected to the combined drains of the last - even 2.2.4 and the penultimate - odd transistors 2.2.3 of the second group 2.2 of n groups of transmitting transistors 2.i.

The source of the second 14 transistor connecting an alternative circuit is connected to the combined drains of the first - odd 2.2.1 and second - even transistors 2.2.2 of the second group 2.2 of n groups of transmitting transistors 2.i.

The drains of the first 13 and second 14 transistors connecting an alternative circuit are combined and connected to the input of the second 10 additional inverter, the output of which is connected to the input of the third 11 additional inverters, the output of which is connected to the gates of the third 15.3 and fifth 15.5 transistors from the group of six additional transmitting transistors 15, the sources which are connected to the input "Zero volts" 17.

The output of the second 10 additional inverter is connected to the gates of the fourth 15.4 and sixth 15.6 transistors from the group of six additional transmitting transistors 15, the sources of which are connected to the input of the supply voltage 16, the combined drains of the fifth 15.5 and sixth 15.6 transistors from the group of six additional transmitting transistors 15 are connected to the source of the second 15.2 transistors from the group of six additional transmitting transistors 15, the gate of which is connected to the output 7 of the device and the input of the first additional inverter 9.

The combined drains of the third 15.3 and fourth 15.4 transistors from the group of six additional transmitting transistors 15 are connected to the source of the first 15.1 transistor from the group of six additional transmitting transistors 15, the gate of which is connected to the output of the additional inverter 9.

The drains of the first 15.1 and second 15.2 transistors from the group of six additional transmitting transistors 15 are combined and connected to the input of the fourth inverter 12, the output of which is the device error output 18.

The drains of each i-th transistor of the first half of the transistors 8.1-8.2 ^n-1 from the group of 2 ⁿ tuning off transistors 8 are connected to the drains of the corresponding i + 2 ^n-1 transistors from the second half of the transistors 8.2 ^n-1 -8.2 ⁿ from the tuning transistor group 8.

A programmable logic device operates in the following modes: 1) programming; 2) calculations with the control of the correctness of the result.

1. Programming mode.

In this mode, the device works similarly to the prototype.

In this case, using technical means external to the device, at 2 ⁿ inputs of setting 6, logical levels are set that correspond to the logical function of n variables, which must be calculated (the truth table of the given logical function of n variables containing 2 ⁿ rows).

So, to implement the addition function modulo two (exclusive OR) four variables (n = 4) × 4⊕ × 3⊕ × 2⊕ × 1, where xi is the signal at the inputs of variables 5.1,5.2,5.3.5.4 - at the tuning inputs 6 (6.1 ... 6.16) the following logical levels are established (A. Stroganov, S. Tsybin. Programmable switching in FPGAs: an inside view // Components and Technologies. - 2010. - No. 11. P.56-62 Fig. 9 [Electronic resource] . - URL: http://www.kit-e.ru/articles/plis/2010_11_56.php Date of treatment 01/12/13 g) - Table 1

At the outputs of inverters of group 2 ⁿ inverters of setup 3, values are set that are inverse to the logic levels set at 2 ⁿ inputs of setup 6.

2. The calculation mode with the control of the correctness of the result.

When n variables 5 are received at the inputs using some of the 2 ⁿ sets external to the device (table 1-5.4 ... 5.1), one of the 2 ⁿ chains in n groups of 2 transmitting transistors (even transistors directly from the corresponding input n variables 5, if it is equal to a logical unit, odd - through the corresponding inverter of the group of n variable inverters, through the output inverter 4 to the output of the device 7).

So, when n variables 5 of set 0101 (set No. 5) are received at the inputs, the chain “even transistor” - “odd transistor” 2.4.6-2.3.3-2.2.2.2.2.1.1 from input 6.6, on which a logical zero is set, through the inverter 3.6, through the corresponding tuning off transistor in the lower half of the tuning transistors activated by their gates with a signal from the output of the inverter 1.1, a logical zero is generated through the inverter 4 and at the output 7: 0⊕1⊕0⊕1 = 0 .

At the same time, the chain of transistors 2 corresponding to set 1101 (set No. 13) 2.4.14-2.3.7-2.2.4-2.1.2 from input 6.14 is “almost” activated, except for the “senior” transistor 2.1.2.

Since the input 5.1 is not activated, the second, upper half of the setting off transistors is not activated (disabled) by its gates, therefore, the setting for transistor 2.4.6 is fed to the source of transistor 2.4.14, the logic level of which (zero) goes to the source of closed transistor 2.1 .2, but since the gate of the first transistor 13 connecting an alternative circuit is activated by the signal from the output of inverter 1.1, the output of the second additional inverter 10 is activated.

Thus, the first input of an addition element modulo two (exclusive OR), implemented on a group of six additional transmitting transistors 15, the first 9 and third 11 additional inverters by adjusting the input voltage 16 and 17 "Zero volts", receives the control value of a logical function.

The second input - the input of the first additional inverter 9 receives the calculated value of the logical function from the output of the inverter 4 (output 7 of the device).

At the same time, the gate of the second transistor 14 connecting an alternative circuit is not activated by the signal from input 5.1 (there is a logical zero - set - high-order bit set 0101.) and disabled.

If the logical levels obtained from the output 7 of the device and obtained at the output of the second additional inverter 10 coincide — in our case, these are two logical zeros — a logical zero is generated at the output of the error 18 through the fourth additional inverter 12.

Moreover, in the above example, logic zeroes are installed at the outputs of additional inverters 11 and 12, therefore, from the input of the supply voltage 16, the logical unit passes through the activated additional transmitting transistor 15.3, then through the activated additional transmitting transistor 15.1 to the input of the fourth additional inverter 12, at the output which is formed by a logical zero.

That is, there is no error. Calculations with control performed.

If logical units are installed at the outputs of additional inverters 11 and 12, from the input of the supply voltage 16, the logical unit passes through the activated additional transmitting transistor 15.6, then through the activated additional transmitting transistor 15.2 to the input of the fourth additional inverter 12, at the output of which a logical zero is generated.

If different logic levels are set at the outputs of additional inverters 11 and 12, from the input “Zero volts” 17 a logical zero passes, for example, through an activated additional transmitting transistor 15.5, then through an activated additional transmitting transistor 15.2 (or through an activated additional transmitting transistor 15.4, then through an activated additional transmitting transistor 15.1) to the input of the fourth additional inverter 12, at the output of which a logical unit is formed, which means a subtraction error selenium formed at the exit 18.

Assessment of technical and economic efficiency.

The probability of failure-free operation of the known programmable logic device PLU on n variables with an exponential model of transistor failures is described by the expression:

where λ is the failure rate of the transistor;

t is the time;

n is the number of digits of the PLU.

In the case of controlling the PLD by using the second half of the transmitting transistor tree, the probability P _{pp of the} situation when the PLU-K object is operational and is recognized as operational is equal to:

Expression (1) takes into account the 16 transistor addition circuit modulo two.

The probability P _{nn of the} situation when the PLU-K facility is not operational and is recognized as not functional (the output signal is not compared), which occurs in case of failures in two halves at once, is equal to:

- вероятность безотказной работы половины дерева транзисторов, схема сложения по модулю два, инверторы входных переменных и инверторы настройки учитываются выражением:Where $$e-\left(\frac{2^{n+\mathrm{one}}+2^n}{2}\right)\lambda \cdot t$$

- the probability of faultless operation of half of the transistor tree, the addition scheme modulo two, input variable inverters and tuning inverters are taken into account by the expression:

Thus, the reliability of control by using the second half of the tree of transmitting transistors is equal to the sum (1), (2):

Graphs of changes in the reliability of the functioning of the known PLU (R.1) and the proposed PLU-K with control (P2) are presented in FIG. 2-5.

So (Fig. 5), taking into account the exponential model of failures (failures) and the failure rate of a single transistor λ = 10 ^-7 at n = 7, t-1000 hours, we get more than 40% of the gain from the maximum possible value.

The achievement of the technical result of the invention is confirmed by the above estimates.

Claims (1)

A programmable logic device containing a group of n variable inverters, n groups of transmitting transistors, n is the number of input variables, 2 ⁱ , i = 1, n transistors in a group, a group of 2 ⁿ tuning inverters, an output inverter, inputs of n variables, 2 ⁿ inputs settings, the output of the device, and the gate of each even transistor of the i-th group of n groups of transmitting transistors is connected to the i-th input of the inputs of n variables, the gate of each odd transistor of the i-th group of n groups of transmitting transistors is connected to the output of the i-th inverter from groups n inv Variable drivers, the drains of even and odd transistors of the n-th group are combined and connected to the sources of the corresponding 2 ^n-1 transistors of the n-1 group, the drains of which are combined and connected to the sources of the corresponding 2 ^n-2 transistors of the n-2nd group, transistors in groups n-3, n-4 ... 2 are connected in a similar way, the drains of the last two transistors of the first group are combined and connected to the input of the output inverter, the output of which is the output of the device, the inputs of n variables are connected to the inputs of the corresponding inverters from the group of n inverters, 2 ⁿ the entrances of us triples are connected to the inputs of the corresponding inverters from the group of 2 ⁿ tuning inverters, characterized in that they additionally include a group of 2 ⁿ tuning shutdown transistors, first, second, third, fourth additional inverters, first and second alternate connection transistors, a group of six additional transmitting transistors, the supply voltage input, a "zero volts" error output, the sources of the transistors of group 2 ⁿ setting the sleep transistors are connected to the outputs of the respective inverter for moat from group 2 ⁿ inverters settings, and drains of transistors in Group 2 ⁿ transistors off configuration connected to the sources of transistors n-th group of transmission transistors, the gates of the first half of the transistors of group 2 ⁿ setting the sleep transistors are connected to a first input of inputs n variables, which is also connected to the gate of the second transistor connecting an alternative circuit, the gates of the second half of the transistors from group 2 ⁿ disconnection transistors are connected to the output of the first inverter from group n inverters in variables, which is also connected to the gate of the first alternative circuit connection transistor, the source of the first alternative circuit connection transistor is connected to the combined drains of the last - even and penultimate - odd transistors of the second group of n groups of transmitting transistors, the source of the second alternative circuit connection transistor is connected to the combined drains first - odd and second - even transistors of the second group of n groups of transmitting transistors, drains of the first and second transistor Alternators of the alternative circuit are combined and connected to the input of the second additional inverter, the output of which is connected to the input of the third additional inverter, the output of which is connected to the gates of the third and fifth transistors from the group of six additional transmitting transistors, the sources of which are connected to the input "Zero volts", the output of the second an additional inverter is connected to the gates of the fourth and sixth transistors from the group of six additional transmitting transistors, the sources of which are connected to the input at the supply voltage, the combined drains of the fifth and sixth transistors from the group of six additional transmitting transistors are connected to the source of the second transistor from the group of six additional transmitting transistors, the gate of which is connected to the output of the device and the input of the first additional inverter, the combined drains of the third and fourth transistors from the group of six additional transmitting transistors are connected to the source of the first transistor from the group of six additional transmitting transistors, the gate of which It is connected to the output of the additional inverter, the drains of the first and second transistors from the group of six additional transmitting transistors are combined and connected to the input of the fourth inverter, the output of which is the output of the device error, the drains of each i-th transistor of the first half of the transistors from the group of 2 ⁿ disconnection transistors are connected to the drains of the corresponding i + 2 ^n-1 transistors from the second half of the transistors from the group of transistors disable settings.

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