RU2542920C2 - Logic module - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: invention is intended to execute any of three simple symmetric Boolean functions, which depend on three arguments - input binary signals, and can be used in digital computer systems as code conversion means. The device has four majority elements.

EFFECT: easy setup of the logic module.

1 dwg

Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logical modules are known (see, for example, RF patent 2249844, class G06F 7/38, 2005), which, using a constant setting, implement any of three simple symmetric Boolean functions depending on three arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using known logical modules is the heterogeneity of the hardware, due to the fact that, in particular, the analogue consists of three types of logical elements (AND, OR, majority elements).

The closest device of the same purpose to the claimed invention in terms of features is the logic module adopted for the prototype (RF patent 2262733, class G06F 7/00, 2005), which contains major elements and can be configured to implement any of three simple symmetrical Boolean functions depending on three arguments - input binary signals x ₁ , x ₂ , x ₃ ∈ {0, 1}.

The reason that impedes the achievement of the technical result indicated below when using the prototype is a complicated setting due to the fact that it requires a four-element training set {0, 1, x ₁ , x ₂ }.

The technical result of the invention is to simplify the configuration for the implementation of any of the three simple symmetric Boolean functions, depending on three arguments - input binary signals, by reducing the power of the training set while maintaining the elemental basis of the prototype.

The specified technical result in the implementation of the invention is achieved by the fact that a logical module containing two majority elements, the first, second, third inputs and the output of the first majority element are connected respectively to the first tuning, first, second information inputs of the logical module and the second input of the second majority element connected the third input and output, respectively, to the third information input and output of the logical module, the peculiarity is that a third and a the fourth majority elements, the first inputs of which are connected respectively to the first and second tuning inputs of the logic module connected to the first, third and second information inputs, respectively, to the second, third inputs of the third majority element and the third input of the fourth majority element, the second input and output of which are connected respectively to the output of the third and first input of the second majority elements.

The drawing shows a diagram of the proposed logical module.

The logic module contains the majority elements l ₁ , l ₂ , l ₃ , l ₄ , and the first, second, third inputs and output of the element l _{1 are} connected respectively to the first tuning, first, second information inputs of the logical module and the second input of the element l ₂ connected third input and output respectively to the third data input and output of the logic module, the first inputs of the elements _3, l ₄ and l are respectively connected to first and second tuning logic module inputs connected first, second and third information in odes respectively to the second, the third input element l ₃ and l third input element _4, a second input and whose output is connected respectively to the output of the element and l ₃ l first input element _2.

имеем Maj(a _k1, a _k2, a _k3)=a _k1·a _k2∨a _k1·a _k3∨a _k2·a _k3, где a _k1, a _k2, a _k3 и ∨, · есть соответственно сигналы на его первом, втором, третьем входах и символы операций ИЛИ, И. Следовательно, сигнал на выходе мажоритарного элемента l₂ определяется выражениемThe work of the proposed logical module is as follows. The binary signals x ₁ , x ₂ , x ₃ ∈ {0, 1} and y ₁ , y ₂ ∈ {0, 1} are respectively supplied to its first, second, third information and first, second tuning inputs. At the output of the majority element $$l_k\left(k=\overline{\mathrm{one},\mathrm{four}}\right)$$

we have M a j ( a _k1 , a _k2 , a _k3 ) = a _k1 · a _k2 ∨ a _k1 · a _k3 ∨ a _k2 · a _k3 , where a _k1 , a _k2 , a _k3 and ∨, · there are signals its first, second, third inputs and operation symbols OR, I. Therefore, the signal at the output of the majority element l ₂ is determined by the expression

Z = (y ₂ (y ₁ x ₁ ∨y ₁ x ₃ ∨x ₁ x ₃ ) ∨y ₂ x ₂ ∨ (y ₁ x ₁ ∨y ₁ x ₃ ∨x ₁ x ₃ ) x ₂ ) (y ₁ x ₁ ∨y ₁ x ₂ ∨x ₁ x ₂ ) ∨

∨ (y ₂ (y ₁ x ₁ ∨y ₁ x ₃ ∨x ₁ x ₃ ) ∨y ₂ x ₂ ∨ (y ₁ x ₁ ∨y ₁ x ₃ ∨x ₁ x ₃ ) x ₂ ) x ₃ ∨ (y ₁ x ₁ ∨y ₁ x ₂ ∨x ₁ x ₂ ) x ₃ .

Thus, at the output of the proposed logical module, we obtain

$$Z=\{\begin{array}{l}{x}_{\mathrm{one}}{x}_2{x}_3={\tau }_{3}PR\mathrm{and}{y}_{\mathrm{one}}=y_2=0\\ x_{\mathrm{one}}{x}_{2}v{x}_2{x}_{3}v{x}_{\mathrm{one}}{x}_3={\tau }_{2}PR\mathrm{and}{y}_{\mathrm{one}}=\mathrm{one},y_2=0,\\ x_{\mathrm{one}}v{x}_{2}v{x}_3={\tau }_{\mathrm{one}}PR\mathrm{and}{y}_{\mathrm{one}}=y_2=\mathrm{one}\end{array}$$

where 0, 1 - elements of the training set; τ ₁ , τ ₂ , τ ₃ are simple symmetric Boolean functions of the three arguments x ₁ , x ₂ , x ₃ .

The above information allows us to conclude that the proposed logic module has a uniform hardware composition and a simpler setup compared to the prototype to implement any of the three simple symmetric Boolean functions, depending on three arguments — input binary signals, since a smaller Compared to the power prototype.

Claims (1)

A logic module designed to implement any of three simple symmetric Boolean functions, depending on three arguments - input binary signals, containing two majority elements, the first, second, third inputs and output of the first majority element being connected respectively to the first tuning, first, second information the inputs of the logical module and the second input of the second majority element connected to the third input and output, respectively, to the third information input and output of the logical mode alu, characterized in that the third and fourth majority elements are introduced into it, the first inputs of which are connected respectively to the first and second tuning inputs of the logic module connected to the second, third and second information inputs, respectively, to the second, third inputs of the third majority element and the third input of the fourth majority element, the second input and output of which are connected respectively to the output of the third and first input of the second majority elements.