RU2559708C1 - Logic converter - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: invention is intended to implement any of five simple symmetric Boolean functions, which depend on five arguments - input binary signals, and can be used in digital computer systems as a code conversion tool. The device comprises eleven majority elements, five information and three configuring inputs.

EFFECT: reduced hardware costs.

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Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logic converters are known (see, for example, RF patent 2281545, class G06F 7/57, 2006), which, using a constant setting, implement any of four simple symmetric Boolean functions that depend on four arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using known logic converters is limited functionality, due to the fact that the implementation of any of the five simple symmetric Boolean functions does not work, depending on five arguments - input binary signals.

The closest device of the same purpose to the claimed invention in terms of features is the logic converter adopted for the prototype (RF patent 2440601, class G06F 7/57, 2012), which contains major elements and implements any of five using three constant tuning signals simple symmetric Boolean functions depending on five arguments - input binary signals. Moreover, the maximum propagation delay time of the signal in the prototype is 5 × Δt _M , where Δt _M is the delay time of the majority element.

The reason that impedes the achievement of the technical result indicated below when using the prototype includes high hardware costs due to the fact that the prototype contains seventeen major elements.

The technical result of the invention is to reduce hardware costs while maintaining the functionality and speed of the prototype.

и j-го $$\left(j=\overline{\mathrm{6,}7}\right)$$

мажоритарных элементов соединены соответственно с вторыми входами (i+1)-го и (j+2)-го мажоритарных элементов, выходы одиннадцатого и k-го $$\left(k=\overline{\mathrm{8,}10}\right)$$

мажоритарных элементов подключены соответственно к третьим входам восьмого и (13-k)-го мажоритарных элементов, объединенные вторые, объединенные третьи входы первого, седьмого, одиннадцатого мажоритарных элементов, объединенные первый вход одиннадцатого, третьи входы второго, девятого мажоритарных элементов, объединенные вторые, объединенные третьи входы шестого, десятого мажоритарных элементов соединены соответственно с первым, вторым, третьим, четвертым, пятым информационными входами логического преобразователя, объединенные первые входы третьего, шестого, седьмого, девятого мажоритарных элементов и объединенные первые входы первого, второго, четвертого, восьмого, десятого мажоритарных элементов подключены соответственно к первому и второму настроечным входам логического преобразователя, третий настроечный вход и выход которого соединены соответственно с первым входом и выходом пятого мажоритарного элемента.The specified technical result in the implementation of the invention is achieved by the fact that in a logical converter containing eleven majority elements that have three inputs, the feature is that the outputs of the i-th $$\left(i=\overline{\mathrm{one,}\mathrm{four}}\right)$$

and j $$\left(j=\overline{\mathrm{6,}7}\right)$$

majority elements are connected respectively to the second inputs of the (i + 1) -th and (j + 2) -th majority elements, the outputs of the eleventh and k-th $$\left(k=\overline{\mathrm{8,}10}\right)$$

majority elements are connected respectively to the third inputs of the eighth and (13-k) -th majority elements, the combined second, combined third inputs of the first, seventh, eleventh majority elements, the combined first input of the eleventh, third inputs of the second, ninth majority elements, the combined second, combined the third inputs of the sixth, tenth majority elements are connected respectively to the first, second, third, fourth, fifth information inputs of the logic converter, the combined first e inputs of the third, sixth, seventh, ninth majority elements and the combined first inputs of the first, second, fourth, eighth, tenth majority elements are connected respectively to the first and second tuning inputs of the logic converter, the third tuning input and output of which are connected respectively to the first input and output the fifth majority element.

The drawing shows a diagram of the proposed logical Converter.

и 1_j $$\left(j=\overline{\mathrm{6,}7}\right)$$

соединены соответственно с вторыми входами элементов 1_i+1 и 1_j+2, выходы элементов 1₁₁ и 1_k $$\left(k=\overline{\mathrm{8,}10}\right)$$

подключены соответственно к третьим входам элементов 1₈ и 1_13-k, объединенные вторые, объединенные третьи входы элементов 1₁, 1₇, 1₁₁, объединенные первый вход элемента 1₁₁, третьи входы элементов 1₂, 1₉, объединенные вторые, объединенные третьи входы элементов 1₆, 1₁₀ соединены соответственно с первым, вторым, третьим, четвертым, пятым информационными входами логического преобразователя, а объединенные первые входы элементов 1₃, 1₆, 1₇, 1₉ и объединенные первые входы элементов 1₁, 1₂, 1₄, 1₈, 1₁₀ подключены соответственно к первому и второму настроечным входам логического преобразователя, третий настроечный вход и выход которого соединены соответственно с первым входом и выходом элемента The logical converter contains the majority elements 1 ₁ , ..., 1 ₁₁ , which have three inputs, and the outputs of the elements 1 _i $$\left(i=\overline{\mathrm{one,}\mathrm{four}}\right)$$

and 1 _j $$\left(j=\overline{\mathrm{6,}7}\right)$$

connected respectively to the second inputs of the elements 1 _{i + 1} and 1 _{j + 2} , the outputs of the elements 1 ₁₁ and 1 _k $$\left(k=\overline{\mathrm{8,}10}\right)$$

connected respectively to the third inputs of the elements 1 ₈ and 1 _13-k , the combined second, combined third inputs of the elements 1 ₁ , 1 ₇ , 1 ₁₁ , the combined first input of the element 1 ₁₁ , the third inputs of the elements 1 ₂ , 1 ₉ , the combined second, combined the third inputs of the elements 1 ₆ , 1 _{10 are} connected respectively with the first, second, third, fourth, fifth information inputs of the logic converter, and the combined first inputs of the elements 1 ₃ , 1 ₆ , 1 ₇ , 1 ₉ and the combined first inputs of the elements 1 ₁ , 1 ₂ , 1 ₄ , 1 ₈ , 1 _{10 are} connected respectively to the first and second settings rack inputs of the logical converter, the third tuning input and output of which are connected respectively to the first input and output of the element

1 ₅ .

имеем maj(a _h1, a _h2, a _h3)=a _h1 a _h2∨a _h1 a _h3∨a _h2 a _h3, где a _h1, a _h2, a _h3 и ∨, есть соответственно сигналы на его первом, втором, третьем входах и символы операций ИЛИ, И. Следовательно, сигнал на выходе элемента 1₅ определяется выражениемThe work of the proposed logical Converter is as follows. At its first, second, third tuning inputs, the necessary signals of constant tuning f ₁ , f ₂ , f ₃ ∈ {0, 1} are fixed respectively. Binary signals x ₁ , ..., x ₅ ∈ {0, 1} are respectively supplied to its first, ..., fifth information inputs. At the output of the majority element 1 _h $$\left(h=\overline{\mathrm{one,}\mathrm{eleven}}\right)$$

we have maj ( a _h1 , a _h2 , a _h3 ) = a _h1 a _h2 ∨ a _h1 a _h3 ∨ a _h2 a _h3 , where a _h1 , a _h2 , a _h3 and ∨, there are signals on its first, second, third inputs and operation symbols OR, I. Therefore, the signal at the output of element 1 ₅ is determined by the expression

. Таким образом, на выходе предлагаемого логического преобразователя получимwherein

. Thus, at the output of the proposed logical Converter we get

where τ ₁ , ..., τ ₅ are simple symmetric Boolean functions of the five arguments x ₁ , ..., x ₅ (see page 126 in the book Pospelov D.A. Logical methods of analysis and synthesis of circuits. M: Energy, 1974 ) Moreover, the specified converter contains eleven majority elements, and the maximum signal propagation delay time in it is 5 × Δt _M , where Δt _M is the delay time of the majority element.

The above information allows us to conclude that the proposed logical converter with the help of three constant tuning signals implements any of five simple symmetric Boolean functions depending on five arguments - input binary signals, has a prototype speed and has lower hardware costs compared to it.

Claims (1)

A logic converter designed to implement any of five simple symmetric Boolean functions depending on five arguments - input binary signals, containing eleven major elements that have three inputs, characterized in that the outputs of the ith $$\left(i=\overline{\mathrm{one,}\mathrm{four}}\right)$$

and j $$\left(j=\overline{\mathrm{6,}7}\right)$$

majority elements are connected respectively to the second inputs of the (i + 1) -th and (j + 2) -th majority elements, the outputs of the eleventh and k-th $$\left(k=\overline{\mathrm{8,}10}\right)$$

majority elements are connected respectively to the third inputs of the eighth and (13-k) -th majority elements, the combined second, combined third inputs of the first, seventh, eleventh majority elements, the combined first input of the eleventh, third inputs of the second, ninth majority elements, the combined second, combined the third inputs of the sixth, tenth majority elements are connected respectively to the first, second, third, fourth, fifth information inputs of the logic converter, and the combined the third, sixth, seventh, ninth majority element inputs and the combined first inputs of the first, second, fourth, eighth, tenth majority elements are connected respectively to the first and second tuning inputs of the logic converter, the third tuning input and output of which are connected respectively to the first input and output the fifth majority element.