RU2549151C1 - Logic converter - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: device comprises eleven majority elements and four tuning inputs.

EFFECT: reduced hardware costs and faster operation.

1 dwg

Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logical converters are known (see, for example, RF patent 2281545, class G06F 7/57, 2006), which implement any of four simple symmetric Boolean functions depending on four arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using known logic converters is limited functionality, due to the fact that the implementation of any of the five simple symmetric Boolean functions does not work, depending on five arguments - input binary signals.

The closest device of the same purpose to the claimed invention in terms of features is the logic converter adopted for the prototype (RF patent 2294007, class G06F 7/57, 2007), which contains major elements and implements any of five using four constant tuning signals simple symmetric Boolean functions depending on five arguments - input binary signals.

The reasons that impede the achievement of the technical result indicated below when using the prototype include high hardware costs and low speed, due to the fact that the prototype contains nineteen major elements and the maximum signal propagation delay time in it is determined by the expression Δt = 6Δt _M , where Δt _M is delay time of the majority element.

The technical result of the invention is to reduce hardware costs and increase speed while maintaining the functionality of the prototype.

и j-го $$(j=\overline{\mathrm{9,10}})$$

мажоритарных элементов соединены соответственно с вторыми входами (i+1)-го и (j-2)-го мажоритарных элементов, выходы k-го $$(k=\overline{\mathrm{6,8}})$$

и одиннадцатого мажоритарных элементов подключены соответственно к третьим входам (k-3)-го и восьмого мажоритарных элементов, а выход пятого мажоритарного элемента является выходом логического преобразователя, первый, второй, третий и четвертый настроечные входы которого соединены соответственно с первым входом десятого мажоритарного элемента, объединенными первыми входами шестого, восьмого мажоритарных элементов, объединенными первыми входами первого, второго, четвертого, пятого мажоритарных элементов и объединенными первыми входами третьего, седьмого, девятого мажоритарных элементов.The specified technical result in the implementation of the invention is achieved by the fact that in a logical converter containing eleven majority elements that have three inputs, the feature is that the outputs of the i-th $$(i=\overline{1.4})$$

and j $$(j=\overline{9.10})$$

majority elements are connected respectively to the second inputs of the (i + 1) -th and (j-2) -th majority elements, the outputs of the k-th $$(k=\overline{6.8})$$

and the eleventh majority elements are connected respectively to the third inputs of the (k-3) th and eighth majority elements, and the output of the fifth majority element is the output of a logic converter, the first, second, third and fourth tuning inputs of which are connected respectively to the first input of the tenth majority element, the combined first inputs of the sixth, eighth majority elements, the combined first inputs of the first, second, fourth, fifth majority elements and the combined first inputs mi of the third, seventh, ninth majority elements.

The drawing shows a diagram of the proposed logical Converter.

и 1_j $$(j=\overline{\mathrm{9,10}})$$

соединены соответственно с вторыми входами элементов 1_i+1 и 1_j-2, выходы элементов 1_k $$(k=\overline{\mathrm{6,8}})$$

и 1₁₁ подключены соответственно к третьим входам элементов 1_k-3 и 1₈, а выход элемента 1₅ является выходом логического преобразователя, первый, второй, третий и четвертый настроечные входы которого соединены соответственно с первым входом элемента 1₁₀, объединенными первыми входами элементов 1₆, 1₈, объединенными первыми входами элементов 1₁, 1₂, 1₄, 1₅ и объединенными первыми входами элементов 1₃, 1₇, 1₉.The logical converter contains the majority elements 1 ₁ , ..., 1 ₁₁ , which have three inputs, and the outputs of the elements 1 _i $$(i=\overline{1.4})$$

and 1 _j $$(j=\overline{9.10})$$

connected respectively to the second inputs of the elements 1 _{i + 1} and 1 _j-2 , the outputs of the elements 1 _k $$(k=\overline{6.8})$$

and 1 _{11 are} connected respectively to the third inputs of elements 1 _k-3 and 1 ₈ , and the output of element 1 ₅ is the output of a logic converter, the first, second, third and fourth tuning inputs of which are connected respectively to the first input of element 1 ₁₀ , combined by the first inputs of elements 1 ₆ , 1 ₈ , combined by the first inputs of the elements 1 ₁ , 1 ₂ , 1 ₄ , 1 ₅ and the combined first inputs of the elements 1 ₃ , 1 ₇ , 1 ₉ .

имеем maj(am₁, am₂, am₃)=am₁am₂∨am₁am₃∨am₂am₃, где am₁, am₂, am₃ и ∨, · есть соответственно сигналы на его первом, втором, третьем входах и символы операций ИЛИ, И. Следовательно, сигнал на выходе элемента 1₅ определяется выражениемThe work of the proposed logical Converter is as follows. At its first, ..., fourth tuning inputs, the necessary signals f ₁ , ..., f ₄ ∈ {0,1} of the constant setting are respectively fixed. To the second inputs of the elements 1 ₁ , 1 ₉ , the first input of the element 1 ₁₁ ; the third inputs of the elements 1 ₁ 1 ₉ , the second input of the element 1 ₁₁ ; the third inputs of the elements 1 ₂ , 1 ₇ , 1 ₁₁ ; the second and third inputs of the elements 1 ₆ , ₁₀ are binary signals x ₁ , respectively; x ₂ ; x ₃ ; x ₄ and x ₅ (x ₁ , ..., x ₅ ∈ {0,1}). At the output of the majority element 1 _m $$(m=\overline{\mathrm{1,11}})$$

we have maj (am ₁ , am ₂ , am ₃ ) = am ₁ am ₂ ∨am ₁ am ₃ ∨am ₂ am ₃ , where am ₁ , am ₂ , am ₃ and ∨, · there are signals on its first, second, respectively, the third inputs and operation symbols OR, I. Therefore, the signal at the output of element 1 ₅ is determined by the expression

,

,

wherein

Thus, at the output of the proposed Converter get

where τ ₁ , ..., τ ₅ are simple symmetric Boolean functions of the five arguments x ₁ , ..., x ₅ (see p. 126 in the book Pospelov DA Logical methods of analysis and synthesis of circuits. -M .: Energy, 1974) . Moreover, this converter contains eleven majority elements, and the maximum delay time of the signal propagation in it is determined by the expression Δt = 5Δt _M (Δt _M is the delay time of the majority element).

The above information allows us to conclude that the proposed logical converter using four constant tuning signals implements any of five simple symmetric Boolean functions depending on five arguments - input binary signals, and has lower hardware costs and higher speed compared to the prototype.

Claims (1)

A logic converter designed to implement any of five simple symmetric Boolean functions depending on five arguments - input binary signals, containing eleven major elements that have three inputs, characterized in that the outputs of the ith

and j

majority elements are connected respectively to the second inputs of the (i + 1) -th and (j-2) -th majority elements, the outputs of the k-th

and the eleventh majority elements are connected respectively to the third inputs of the (k-3) th and eighth majority elements, and the output of the fifth majority element is the output of a logic converter, the first, second, third and fourth tuning inputs of which are connected respectively to the first input of the tenth majority element, the combined first inputs of the sixth, eighth majority elements, the combined first inputs of the first, second, fourth, fifth majority elements and the combined first inputs mi of the third, seventh, ninth majority elements.