RU2393527C2 - Logical converter - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: logical converter is intended to realise any of five simple symmetrical Boolean functions, which depend on five arguments - input binary signals, and may be used in systems of digital computer equipment as facility for conversion of codes. Device comprises eight majority elements, four information and three adjustment inputs.

EFFECT: reduced instrument costs and improved efficiency.

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Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logical converters are known (see, for example, RF patent 2281545, class G06F 7/57, 2006), which implement any of four simple symmetric Boolean functions depending on four arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using known logic converters is limited functionality, due to the fact that the implementation of any of the five simple symmetric Boolean functions does not work, depending on five arguments - input binary signals.

The closest device of the same purpose to the claimed invention in terms of features is the logic converter adopted for the prototype (RF patent 2294007, class G06F 7/57, 2007), which contains majority elements and implements any of five simple symmetric Boolean functions that depend from five arguments - input binary signals.

The reasons that impede the achievement of the technical result indicated below when using the prototype include high hardware costs and low speed, due to the fact that the prototype contains nineteen major elements and the maximum signal propagation delay time in it is determined by the expression Δt = 6Δt _M , where Δt _M is delay time of the majority element.

The technical result of the invention is to reduce hardware costs and increase speed while maintaining the functionality of the prototype.

мажоритарного элемента подключен к второму входу (i+3)-го мажоритарного элемента, а выходы четвертого, пятого и шестого мажоритарных элементов соединены соответственно с вторым, третьим входами седьмого и третьим входом восьмого мажоритарных элементов, подключенных выходами соответственно к второму входу восьмого мажоритарного элемента и выходу логического преобразователя, третий, первый и второй настроечные входы которого образованы соответственно третьим входом третьего мажоритарного элемента, объединенными первыми входами первого - третьего, седьмого, восьмого и объединенными первыми входами четвертого - шестого мажоритарных элементов.The specified technical result in the implementation of the invention is achieved by the fact that in a logical converter containing eight major elements, the feature is that the combined second inputs of the first to third, the combined third inputs of the first, sixth and the combined third inputs of the second, fourth major elements are connected respectively to the first, second and third information inputs of the logical converter, the fourth information input of which is formed by the third input of the fifth major Foot element, i-th output

the majority element is connected to the second input of the (i + 3) -th majority element, and the outputs of the fourth, fifth and sixth majority elements are connected respectively to the second, third inputs of the seventh and third input of the eighth majority elements, connected by the outputs respectively to the second input of the eighth majority element and the output of the logical converter, the third, first and second tuning inputs of which are formed respectively by the third input of the third majority element, combined by the first inputs of the first of - the third, seventh, eighth, and combining the first input of the fourth - sixth of majority elements.

The drawing shows a diagram of the proposed logical Converter.

подключен к второму входу элемента 1_i+3, а выходы элементов 1₄, 1₅ и 1₆ соединены соответственно с вторым, третьим входами элемента 1₇ и третьим входом элемента 1₈, подключенного вторым входом и выходом соответственно к выходу элемента 1₇ и выходу логического преобразователя, третий, первый и второй настроечные входы которого образованы соответственно третьим входом элемента 1₃, объединенными первыми входами элементов 1₁, 1₂, 1₃, 1₇, 1₈ и объединенными первыми входами элементов 1₄, 1₅, 1₆.The logical converter contains the majority elements 1 ₁ , ..., 1 ₈ , and the combined second inputs of the elements 1 ₁ , 1 ₂ , 1 ₃ , the combined third inputs of the elements 1 ₁ , 1 ₆ and the combined third inputs of the elements 1 ₂ , 1 ₄ , the second and third information inputs of the logical converter, the fourth information input of which is formed by the third input of element 1 ₅ , the output of element 1 _i

connected to the second input of the element 1 _{i + 3} , and the outputs of the elements 1 ₄ , 1 ₅ and 1 _{6 are} connected respectively to the second, third inputs of the element 1 ₇ and the third input of the element 1 ₈ connected by the second input and output, respectively, to the output of the element 1 ₇ and the output of the logical converter, the third, first and second tuning inputs of which are formed respectively by the third input of the element 1 ₃ , combined by the first inputs of the elements 1 ₁ , 1 ₂ , 1 ₃ , 1 ₇ , 1 ₈ and the combined first inputs of the elements 1 ₄ , 1 ₅ , 1 ₆ .

имеем a_k1#a_k2#a_k3=a_k1a_k2∨a_k1a_k3∨a_k2a_k3, где a_k1,a_k2,a_k3 и #, ∨, • есть соответственно сигналы на его первом, втором, третьем входах и символы операций Maj, ИЛИ, И. Следовательно, сигнал на выходе предлагаемого логического преобразователя определяется выражениемThe work of the proposed logical Converter is as follows. Binary signals x ₁ , ..., x ₄ ∈ {0,1} and f ₁ , ..., f ₃ ∈ {0,1} are given respectively to its first, ..., fourth information and first, ..., third tuning inputs. At the output of the majority element 1 _k

we have a _k1 #a _k2 #a _k3 = a _k1 a _k2 ∨a _k1 a _k3 ∨a _k2 a _k3 , where a _k1 , a _k2 , a _k3 and #, ∨, • there are signals on its first, second, third, respectively inputs and symbols of operations Maj, OR, I. Therefore, the signal at the output of the proposed logical converter is determined by the expression

Z = f ₁ (f ₁ y ₁ ∨f ₁ y ₂ ∨y ₁ y ₂ ) ∨f ₁ y ₃ ∨ (f ₁ y ₁ ∨f ₁ y ₂ ∨y ₁ y ₂ ) y ₃ ,

Where

y ₁ = f ₂ (f ₁ x ₁ ∨f ₁ x ₂ ∨x ₁ x ₂ ) ∨f ₂ x ₃ ∨ (f ₁ x ₁ ∨f ₁ x ₂ ∨x ₁ x ₂ ) x ₃ ;

y ₂ = f ₂ (f ₁ x ₁ ∨f ₁ x ₃ ∨x ₁ x ₃ ) ∨f ₂ x ₄ ∨ (f ₁ x ₁ ∨f ₁ x ₃ ∨x ₁ x ₃ ) x ₄ ;

y ₃ = f ₂ (f ₁ x ₁ ∨f ₁ x ₃ ∨x ₁ x ₃ ) ∨f ₂ x ₂ ∨ (f ₁ x ₁ ∨f ₁ x ₃ ∨x ₁ x ₃ ) x ₂ ;

Thus, at the output of the proposed logical Converter we get

where τ ₁ , ..., τ ₅ are simple symmetric Boolean functions of the five arguments x ₁ , ..., x ₅ (see page 126 in the book Pospelov D. A. Logical methods of analysis and synthesis of circuits. M .: Energy, 1974). Moreover, this converter contains eight majority elements, and the maximum delay time of the signal propagation in it is determined by the expression Δt = 4Δt _M , where Δt _M is the delay time of the majority element.

The above information allows us to conclude that the proposed logic converter implements any of five simple symmetric Boolean functions, depending on five arguments - input binary signals, and has lower hardware costs and faster performance compared to the prototype.

Claims (1)

A logic converter for implementing any of five simple symmetric Boolean functions, depending on five arguments - input binary signals, containing eight majority elements, characterized in that the combined second inputs of the first and third, the combined third inputs of the first, sixth and the combined third inputs of the second, fourth majority elements are connected respectively to the first, second and third information inputs of the logic converter, the fourth information input of which is formed by third m input of the fifth majority element, the output of the i-th

the majority element is connected to the second input of the (i + 3) -th majority element, and the outputs of the fourth, fifth and sixth majority elements are connected respectively to the second, third inputs of the seventh and third input of the eighth majority elements, connected by the outputs respectively to the second input of the eighth majority element and the output of the logical converter, the third, first and second tuning inputs of which are formed respectively by the third input of the third majority element, combined by the first inputs of the first of - the third, seventh, eighth, and combining the first input of the fourth - sixth of majority elements.