RU2417404C1 - Logic converter - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: logic converter has six majority elements, four data inputs and two adjustment units.

EFFECT: reduced hardware expenses.

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Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logic converters are known (see, for example, RF patent 2248034, class G06F 7/38, 2005), which contain majority elements and implement any of the four simple symmetric Boolean functions τ ₁ = x ₁ ∨x ₂ ∨x ₃ ∨ x ₄ , τ ₂ = x ₁ x ₂ ∨x ₁ x ₃ ∨x ₁ x ₄ ∨x ₂ x ₃ ∨x ₂ x ₄ ∨x ₃ x ₄ , τ ₃ = x ₁ x ₂ x ₃ ∨x ₁ x ₂ x ₄ ∨x ₁ x ₃ x ₄ ∨x ₂ x ₃ x ₄ , τ ₄ = x ₁ x ₂ x ₃ x ₄ , depending on four arguments - input binary signals x ₁ , x ₂ , x ₃ , x ₄ ∈ { 0,1}.

The reason that impedes the achievement of the technical result indicated below when using well-known logic converters includes high hardware costs.

The closest device of the same purpose to the claimed invention in terms of features is a logic converter adopted for the prototype (RF patent 2281545, class G06F 7/57, 2006), which contains majority elements and implements any of four simple symmetric Boolean functions τ ₁ = x ₁ ∨x ₂ ∨x ₃ ∨x ₄ , τ ₂ = x ₁ x ₂ ∨x ₁ x ₃ ∨x ₁ x ₄ ∨x ₂ x ₃ ∨x ₂ x ₄ ∨x ₃ x ₄ , τ ₃ = x ₁ x ₂ x ₃ ∨x ₁ x ₂ x ₄ ∨x ₁ x ₃ x ₄ ∨x ₂ x ₃ x ₄ , τ ₄ = x ₁ x ₂ x ₃ x ₄ , depending on four arguments - input binary signals x ₁ , x ₂ , x ₃ , x ₄ ∈ {0,1}.

The reason that impedes the achievement of the technical result indicated below when using the prototype includes high hardware costs due to the fact that the prototype contains seven major elements.

The technical result of the invention is to reduce hardware costs while maintaining the functionality of the prototype.

The specified technical result in the implementation of the invention is achieved by the fact that in a logic converter containing six majority elements and connected by the first, second, fourth information and first tuning inputs, respectively, to the second, third inputs of the first, third input of the fifth and first input of the third majority elements, the feature is in that the second, third inputs and the output of the second majority element are connected respectively with the third, fourth information inputs about the converter and the third input of the third majority element, the second input and output of which are connected respectively to the output of the first majority element and the third input of the sixth majority element, connected by the first, second inputs and output, respectively, to the outputs of the fourth, fifth majority elements and the output of the logical converter, the first, the second and third information inputs of which are connected respectively with the second, third inputs of the fourth and second input of the fifth majority elements, the first inputs to the first tuning input of the logic converter, the second tuning input of which is formed by the combined first inputs of the first, second majority elements.

The drawing shows a diagram of the proposed logical Converter.

The logical converter contains the majority elements 1 ₁ -1 ₆ , and the combined second and combined third inputs of the elements 1 ₁ , 1 ₄ , the combined second and combined third inputs of the elements 1 ₂ , 1 ₅ form respectively the first and second, third and fourth information inputs of the logical converter connected to the output of the output element 1 to _6, the first, second and third inputs connected respectively to the outputs of the elements 1 _4, 1 ₅ and 1 ₃ are connected to first inputs of a first adjustment logic input transducer , The second input of which is formed by adjusting the combined first inputs of the elements 1 _1, 1 ₂ outputs connected respectively to the second, the third input element ₁ March.

имеем a_k1#a_k2#a_k3=a_k1a_k2∨a_k1a_k3, где a_k1,a_k2,a_k3 и #, ∨, · есть соответственно сигналы на его первом, втором, третьем входах и символы операций Maj, ИЛИ, И. Следовательно, если на первом входе элемента 1_k присутствует «1» либо «0», то этот элемент будет выполнять операцию a_k2∨a_k3 либо a_k2a_k3. Таким образом, на выходе предлагаемого преобразователя получимThe work of the proposed logical Converter is as follows. Binary signals x ₁ -x ₄ ∈ {0,1} and f ₁ , f ₂ ∈ {0,1} are supplied to its first - fourth information and first, second training inputs. At the output of the majority element

we have a _k1 #a _k2 #a _k3 = a _k1 a _k2 ∨a _k1 a _k3 , where a _k1 , a _k2 , a _k3 and #, ∨, · there are signals on its first, second, third inputs and symbols of Maj operations, respectively , OR, I. Therefore, if at the first input of element 1 _k there is “1” or “0”, then this element will perform the operation a _k2 ∨a _k3 or a _k2 a _k3 . Thus, at the output of the proposed Converter get

The above information allows us to conclude that the proposed logic converter implements any of the four simple symmetric Boolean functions τ ₁ = x ₁ ∨x ₂ ∨x ₃ ∨x ₄ , τ ₂ = x ₁ x ₂ ∨x ₁ x ₃ ∨x ₁ x ₄ ∨x ₂ x ₃ ∨x ₂ x ₄ ∨x ₃ x ₄ , τ ₃ = x ₁ x ₂ x ₃ ∨x ₁ x ₂ x ₄ ∨x ₁ x ₃ x ₄ ∨x ₂ x ₃ x ₄ , τ ₄ = x ₁ x ₂ x ₃ x ₄ , depending on four arguments - input binary signals x ₁ , x ₂ , x ₃ , x ₄ ∈ {0,1}, and has less hardware costs compared to the prototype, since it contains one majority the element is smaller than in the hardware composition of the prototype.

Claims (1)

A logic converter for implementing any of four simple symmetric Boolean functions depending on four arguments - input binary signals, containing six majority elements and connected by the first, second, fourth information and first tuning inputs, respectively, to the second, third inputs of the first, third inputs of the fifth and first the input of the third majority elements, characterized in that the second, third inputs and the output of the second majority element are connected respectively to the third, fourth inf the logic inputs of the logic converter and the third input of the third majority element, the second input and output of which are connected respectively to the output of the first majority element and the third input of the sixth majority element, connected by the first, second inputs and output, respectively, to the outputs of the fourth, fifth majority elements and the output of the logical converter, the first, second and third information inputs of which are connected respectively to the second, third inputs of the fourth and second input of the fifth m zhoritarnyh elements, first inputs connected to the first tuning input of logic inverter, the second input of which is formed by adjusting the combined first inputs of the first, second majority elements.