RU2443009C1 - Logic converter - Google Patents

Abstract

FIELD: computational engineering.

SUBSTANCE: device contains four information inputs and three setup inputs, the vote-taking elements (1₁…1₇) and is performed with an option of implementation of any of five symmetrical Boolean functions depending on five arguments - input binary waveforms.

EFFECT: decrease in hardware costs and increasing the processing speed reached due to a decrease in the number of vote-taking elements and a decrease in the maximum signal delay time.

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Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logical converters are known (see, for example, RF patent 2294007, class G06F 7/57, 2007), which implement any of five simple symmetric Boolean functions depending on five arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using well-known logic converters includes high hardware costs and low speed, due respectively to the hardware composition of nineteen major elements and the maximum signal propagation delay time defined by the expression Δt = 6Δt _M , where Δt _M is the time delays of the majority element.

The closest device of the same purpose to the claimed invention in terms of features is the logic converter adopted for the prototype (RF patent 2393527, class G06F 7/57, 2010), which contains majority elements and implements any of five simple symmetric Boolean functions that depend from five arguments - input binary signals.

The reasons that impede the achievement of the technical result indicated below when using the prototype include high hardware costs and low speed, due to the fact that the prototype contains eight majority elements and the maximum signal propagation delay time in it is determined by the expression Δt = 4Δt _M , where Δt _M is delay time of the majority element.

The technical result of the invention is to reduce hardware costs and increase speed while maintaining the functionality of the prototype.

The specified technical result in the implementation of the invention is achieved by the fact that in a logical converter containing seven majority elements, among which the first majority element is connected by the second and third inputs, respectively, to the first and second information inputs of the logical converter, connected to the second and first tuning inputs, respectively, to the first input of the fourth , and the combined first inputs of the first, third majority elements, the peculiarity is that the combined WTO the first inputs of the second, fifth, the combined first inputs of the fifth, sixth and the combined first inputs of the second, seventh majority elements are connected respectively to the third information, first and second tuning inputs of the logic converter, the first, second, fourth information and third tuning inputs of which are connected respectively to the second , the third inputs of the fourth, third input of the second and third input of the fifth majority element, the second and third inputs of the i-th (i∈ {3,6}) majority element are connected with respectively with the output (i-2) th and output (i-1) -th elements of the majority, and the second, the third input and an output of the seventh majority element are respectively connected to the output of the third, sixth output of majority logic elements and output transducer.

The drawing shows a diagram of the proposed logical Converter.

The logical converter contains the majority elements 1 ₁ , ..., 1 ₇ , and the combined second inputs of the elements 1 ₁ , 1 ₄ , the combined third inputs of the elements 1 ₁ , 1 ₄ and the combined second inputs of the elements 1 ₂ , 1 ₅ connected respectively to the first, second and the third information inputs of the logical converter, the fourth information input of which is formed by the third input of element 1 ₂ , the second and third inputs of element 1 _i (i∈ {3,6}) are connected respectively to the outputs of elements 1 _i-2 and 1 _i-1 , and the second a third input and an output element connected with January ₇ tvetstvenno to the outputs of the elements 1 _3, 1 ₆ and the output logic inverter, the third, the first and second tuning inputs of which are respectively formed the third input element 1 to ₅ combined first inputs of the elements 1 _1, 1 _3, 1 _5, 1 ₆ and the combined first inputs of elements 1 ₂ , 1 ₄ , 1 ₇ .

имеем a _k1#a _k2#a _k3=a _k1 a _k2∨a _k1 a _k3∨a _k2 a _k3, где a _k1, a _k2, a _k3 и #, ∨, · есть соответственно сигналы на его первом, втором, третьем входах и символы операций Maj, ИЛИ, И. Следовательно, сигнал на выходе предлагаемого логического преобразователя определяется выражениемThe work of the proposed logical Converter is as follows. Binary signals x ₁ , ..., x ₄ ∈ {0,1} and f ₁ , ..., f ₃ ∈ {0,1} are given respectively to its first, ..., fourth information and first, ..., third tuning inputs. At the output of the majority element

we have a _k1 # a _k2 # a _k3 = a _k1 a _k2 ∨ a _k1 a _k3 ∨ a _k2 a _k3 , where a _k1 , a _k2 , a _k3 and #, ∨, · there are signals on its first, second, third, respectively inputs and symbols of operations Maj, OR, I. Therefore, the signal at the output of the proposed logical converter is determined by the expression

Z = f ₂ y ₁ ∨ f ₂ y ₂ ∨y ₁ y ₂ ,

Where

y ₁ = f ₁ (f ₁ x ₁ ∨f ₁ x ₂ ∨x ₁ x ₂ ) ∨f ₁ (f ₂ x ₃ ∨f ₂ x ₄ ∨x ₃ x ₄ ) ∨

∨ (f ₁ x ₁ ∨f ₁ x ₂ ∨x ₁ x ₂ ) (f ₂ x ₃ ∨f ₂ x ₄ ∨x ₃ x ₄ );

y ₂ = f ₁ (f ₂ x ₁ ∨f ₂ x ₂ ∨x ₁ x ₂ ) ∨f ₁ (f ₁ x ₃ ∨f ₁ f ₃ ∨x ₃ f ₃ ) ∨

∨ (f ₂ x ₁ ∨f ₂ x ₂ ∨x ₁ x ₂ ) (f ₁ x ₃ ∨f ₁ f ₃ ∨x ₃ f ₃ ).

Thus, at the output of the proposed logical Converter we get

where τ ₁ , ..., τ ₅ are simple symmetric Boolean functions of the five arguments x ₁ , ..., x ₅ (see page 126 in the book Pospelov D. A. Logical methods of analysis and synthesis of circuits. M .: Energy, 1974). Moreover, the specified Converter contains seven majority elements, and the maximum delay time of the signal propagation in it is determined by the expression Δt = 3Δt _M , where Δt _M is the delay time of the majority element.

The above information allows us to conclude that the proposed logic converter implements any of five simple symmetric Boolean functions, depending on five arguments - input binary signals, and has lower hardware costs and faster performance compared to the prototype.

Claims (1)

A logic converter designed to implement any of five simple symmetric Boolean functions depending on five arguments - input binary signals, containing seven majority elements, among which the first majority element is connected by the second and third inputs, respectively, to the first and second information inputs of the logical converter connected to the second and the first tuning inputs, respectively, to the first input of the fourth and the combined first inputs of the first, third majority element s, characterized in that the combined second inputs of the second, fifth, the combined first inputs of the fifth, sixth and the combined first inputs of the second, seventh majority elements are connected respectively to the third information, first and second tuning inputs of the logic converter, the first, second, fourth information and third the tuning inputs of which are connected respectively to the second, third inputs of the fourth, third input of the second and third input of the fifth majority elements, the second and third inputs of the i-th (i∈ {3,6}) of the majority element are connected respectively to the output of the (i-2) -th and output of the (i-1) -th majority elements, and the second, third inputs and the output of the seventh majority element are connected respectively to the output of the third, the output of the sixth majority elements and the output of the logical converter.

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