RU2634229C1 - Logical converter - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: logical converter is designed to perform simple symmetric Boolean functions and can be used in the digital computer engineering systems like the code conversion means. The logical converter contains fourteen majority elements (1₁, …1₁₄).

EFFECT: ensuring the implementation of any of the six simple symmetric Boolean functions depending on six arguments - binary input signals.

1 dwg

Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logic converters are known (see, for example, RF patent 2440601, class G06F 7/57, 2012), which, using a constant setting, implement any of five simple symmetric Boolean functions that depend on five arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using known logic converters is limited functionality, due to the fact that the implementation of any of the six simple symmetric Boolean functions does not work, depending on six arguments - input binary signals.

The closest device of the same purpose to the claimed invention in terms of features is the logic converter adopted as a prototype (RF patent 2517720, class G06F 7/57, 2014), which contains twelve major elements and implements any of five simple settings symmetric Boolean functions depending on five arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using the prototype is limited functionality, due to the fact that the implementation of any of the six simple symmetric Boolean functions does not work, depending on six arguments - input binary signals.

The technical result of the invention is the expansion of functionality by providing the implementation using a constant configuration of any of six simple symmetric Boolean functions, depending on six arguments - input binary signals.

мажоритарного элемента соединены соответственно с выходами (2×i-17)-го, (2×i-16)-го и (i-10)-м входом четырнадцатого мажоритарных элементов, а выходы j-го

и четырнадцатого мажоритарных элементов подключены соответственно к второму входу (j+4)-го мажоритарного элемента и выходу логического преобразователя, третий, первый и второй настроечные входы которого соединены соответственно с первым входом одиннадцатого мажоритарного элемента, объединенными первыми входами второго, пятого, двенадцатого мажоритарных элементов и объединенными первыми входами третьего, четвертого, седьмого, восьмого, тринадцатого мажоритарных элементов.The specified technical result during the implementation of the invention is achieved by the fact that in a logical converter containing twelve major elements, which have three inputs, the first inputs of the first, sixth majority elements are connected to the first tuning input of the logical converter, the peculiarity is that it is additionally introduced two majority elements that have three inputs, the second, third inputs and the i-th output

the majority element are connected respectively to the outputs of the (2 × i-17) -th, (2 × i-16) -th and (i-10) -th inputs of the fourteenth majority elements, and the outputs of the j-th

and the fourteenth majority elements are connected respectively to the second input of the (j + 4) -th majority element and the output of the logic converter, the third, first and second tuning inputs of which are connected respectively to the first input of the eleventh majority element, combined by the first inputs of the second, fifth, twelfth majority elements and the combined first inputs of the third, fourth, seventh, eighth, thirteenth major elements.

The drawing shows a diagram of the proposed logical Converter.

соединены соответственно с выходами элементов 1_2×i-17, 1_2×i-16 и (i-10)-м входом элемента 1₁₄, а выходы элементов 1_j

и 1₁₄ подключены соответственно к второму входу элемента 1_j+4 и выходу логического преобразователя, третий, первый и второй настроечные входы которого образованы соответственно первым входом элемента 1₁₁, объединенными первыми входами элементов 1₁, 1₂, 1₅, 1₆, 1₁₂ и объединенными первыми входами элементов 1₃, 1₄, 1₇, 1₈, 1₁₃.The logical converter contains the majority elements 1 ₁ , ..., 1 ₁₄ , which have three inputs, and the second, third inputs and the output of the element 1 _i

connected respectively to the outputs of the elements 1 _{2 × i-17} , 1 _{2 × i-16} and the (i-10) -th input of the element 1 ₁₄ , and the outputs of the elements 1 _j

and 1 _{14 are} connected respectively to the second input of element 1 _{j + 4} and the output of the logic converter, the third, first and second tuning inputs of which are formed respectively by the first input of element 1 ₁₁ , combined by the first inputs of elements 1 ₁ , 1 ₂ , 1 ₅ , 1 ₆ , 1 ₁₂ and the combined first inputs of the elements 1 ₃ , 1 ₄ , 1 ₇ , 1 ₈ , 1 ₁₃ .

константной настройки. На вторые входы элементов 1₁, 1₃, первый вход элемента 1₉; третьи входы элементов 1₃, 1₃, второй вход элемента 1₉; третьи входы элементов 1₅, 1₇, 1₉; вторые входы элементов 1₂, 1₄, первый вход элемента 1₁₀; третьи входы элементов 1₂, 1₄, второй вход элемента 1₁₀; третьи входы элементов 1₆, 1₈, 1₁₀ подаются соответственно двоичные сигналы x₁; x₂; x₃; х₄; х₅; x₆ (x₁, …, x₆∈{0,1}). На выходе мажоритарного элемента 1_m,

имеем a_m1#a_m2#a_m3=a_m1a_m2∨a_m1a_m3∨a_m2a_m3, и a_m1, a_m2, a_m3 и #, ∨, ⋅ есть соответственно сигналы на его первом, втором, третьем входах и символы операций maj, ИЛИ, И. Следовательно, сигнал на выходе элемента 1₁₄ определяется выражениемThe work of the proposed logical Converter is as follows. On its first, second, third tuning inputs, the necessary signals are fixed accordingly

constant settings. To the second inputs of the elements 1 ₁ , 1 ₃ , the first input of the element 1 ₉ ; third inputs of elements 1 ₃ , 1 ₃ , second input of element 1 ₉ ; third inputs of elements 1 ₅ , 1 ₇ , 1 ₉ ; the second inputs of the elements 1 ₂ , 1 ₄ , the first input of the element 1 ₁₀ ; the third inputs of the elements 1 ₂ , 1 ₄ , the second input of the element 1 ₁₀ ; the third inputs of the elements 1 ₆ , 1 ₈ , 1 ₁₀ give binary signals x ₁ , respectively; x ₂ ; x ₃ ; x ₄ ; x ₅ ; x ₆ (x ₁ , ..., x ₆ ∈ {0,1}). At the output of the majority element 1 _m ,

we have a _m1 #a _m2 #a _m3 = a _m1 a _m2 ∨a _m1 a _m3 ∨a _m2 a _m3 , and a _m1 , a _m2 , a _m3 and #, ∨, ⋅ are respectively signals on its first, second, third inputs and symbols of operations maj, OR, I. Therefore, the signal at the output of element 1 ₁₄ is determined by the expression

Таким образом, на выходе предлагаемого преобразователя получимwherein

Thus, at the output of the proposed Converter get

where τ ₁ , ..., τ ₆ are simple symmetric Boolean functions of six arguments x ₁ , ..., x ₆ (see p. 126 in the book Pospelov D.A. Logical methods of analysis and synthesis of circuits. M: Energy, 1974 )

The above information allows us to conclude that the proposed logic converter has wider functionality compared to the prototype, because it uses a constant configuration to implement any of six simple symmetric Boolean functions that depend on six arguments - input binary signals.

Claims (1)

A logic converter designed to implement any of six simple symmetric Boolean functions depending on six arguments - input binary signals, containing twelve majority elements that have three inputs, the first inputs of the first and sixth majority elements connected to the first tuning input of the logical converter, characterized in that two major elements are additionally introduced into it, which have three inputs, a second, a third input and an i-th output

the majority element are connected respectively to the outputs of the (2 × i-17) -th, (2 × i-16) -th and (i-10) -th inputs of the fourteenth majority elements, and the outputs of the j-th

and the fourteenth majority elements are connected respectively to the second input of the (j + 4) -th majority element and the output of the logic converter, the third, first and second tuning inputs of which are connected respectively to the first input of the eleventh majority element, combined by the first inputs of the second, fifth, twelfth majority elements and the combined first inputs of the third, fourth, seventh, eighth, thirteenth major elements.

Images