RU2621281C1 - Logic converter - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: logic converter is designed to perform any of the simple symmetrical Boolean functions τ₁, τ₂, τ_n-1, τ_n depending on the n-arguments - the binary input signals at n=5, and can be used in the digital computer engineering systems like the code conversion means. The logic converter comprises eight majority elements (1₁, …, 1₈₎, and the maximum propagation delay time therein is equal to 5×Δt_m, where Δt_m - the majority element delay time.

EFFECT: increasing performance while maintaining hardware composition and functional capabilities of the prototype.

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Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logic converters are known (see, for example, RF patent 2281545, class G06F 7/57, 2006), which, using a constant setting, implement any of the simple symmetric Boolean functions τ ₁ , τ ₂ , τ _n-1 , τ _n depending on n arguments - input binary signals, for n = 4.

The reason that impedes the achievement of the technical result indicated below when using known logic converters is limited functionality due to the fact that processing of five input signals is not allowed.

The closest device of the same purpose to the claimed invention in terms of features is the logic converter adopted for the prototype (RF patent 2542895, class G06F 7/57, 2015), which contains eight major elements and implements any of the simple symmetric using a constant setting Boolean functions τ ₁ , τ ₂ , τ _n-1 , τ _n , depending on n arguments - input binary signals, for n = 5.

The reason that impedes the achievement of the technical result indicated below when using the prototype is the low speed due to the fact that the maximum propagation delay time of the signal in the prototype is determined by the expression 6 × ΔT _M , where Δt _M is the delay time of the majority element.

The technical result of the invention is to improve performance while maintaining the hardware composition and functionality of the prototype.

) информационные и первый настроечный входы которого подключены соответственно к второму входу первого, третьему входу (j-1)-го мажоритарных элементов и первым входам первого, второго, третьего, шестого мажоритарных элементов, особенность заключается в том, что второй, третий входы k-го (

), первый вход и выход восьмого мажоритарных элементов соединены соответственно с выходами (k-1)-го, (2×k-12)-го мажоритарных элементов, первым настроечным входом и выходом логического преобразователя, первый, второй, третий и четвертый информационные входы которого подключены соответственно к первому, второму, третьему входам пятого и третьему входу шестого мажоритарных элементов.The specified technical result in the implementation of the invention is achieved by the fact that in a logic converter containing eight majority elements, the output of the i-th (i∈ {1,2,3,5}) majority element and the first inputs of the fourth, seventh majority elements are connected respectively to the second the input of the (i + 1) -th majority element and the second tuning input of the logical converter, the first, j-th

) the information and first tuning inputs of which are connected respectively to the second input of the first, third input of the (j-1) -th majority elements and the first inputs of the first, second, third, sixth majority elements, the feature is that the second, third inputs k- go (

), the first input and output of the eighth majority elements are connected respectively to the outputs of the (k-1) -th, (2 × k-12) -th majority elements, the first tuning input and the output of the logic converter, the first, second, third and fourth information inputs which are connected respectively to the first, second, third inputs of the fifth and third inputs of the sixth majority elements.

The drawing shows a diagram of the proposed logical Converter.

), первый вход и выход элемента 1₈ соединены соответственно с выходами элементов 1_k-1 и 1_2×k-12, первым настроечным входом и выходом логического преобразователя, первый, второй, третий и четвертый информационные входы которого подключены соответственно к первому, второму, третьему входам элемента 1₅ и третьему входу элемента 1₆.The logical converter contains the majority elements 1 ₁ , ..., 1 ₈ , and the output of the element 1 _i (i∈ {1, 2, 3, 5}) and the first inputs of the elements 1 ₄ , 1 _{7 are} connected respectively to the second input of the element 1 _{i + 1} and the second training input of the logic converter, the first, j-th (J = 2.5) information and first tuning inputs of which are connected respectively to the second input of element 1 ₁ , the third input of element 1 _j-1 and the first inputs of elements 1 ₁ , 1 ₂ , 1 ₃ , 1 ₆ , second, third inputs of element 1 _k (

), the first input and output of element 1 _{8 are} connected respectively to the outputs of elements 1 _k-1 and 1 _{2 × k-12} , the first tuning input and output of the logic converter, the first, second, third and fourth information inputs of which are connected respectively to the first, second , the third inputs of element 1 ₅ and the third input of element 1 ₆ .

) имеем

, где a_m1, a_m2, a_m3 и

,

есть соответственно сигналы на его первом, втором, третьем входах и символы операций ИЛИ, И. Следовательно, сигнал на выходе элемента 1₈ определяется выражениемThe work of the proposed logical Converter is as follows. At its first and second tuning inputs, the necessary signals of constant tuning ƒ ₁ , ƒ ₂ ∈ {0,1} are fixed respectively. At its first, ..., fifth information inputs, binary signals x ₁ , ..., x ₅ ∈ {0,1} are supplied, respectively. At the output of the majority element 1 _m (

) we have

, where a _m1 , a _m2, a _m3 and

,

there are, respectively, signals at its first, second, third inputs and symbols of operations OR, I. Therefore, the signal at the output of element 1 ₈ is determined by the expression

,

,

. Таким образом, на выходе предлагаемого логического преобразователя получимwherein

. Thus, at the output of the proposed logical Converter we get

where τ ₁ , τ ₂ , τ ₄ , τ ₅ are simple symmetric Boolean functions of the five arguments x ₁ , ..., x ₅ (see page 126 in the book Pospelov DA Logical methods of analysis and synthesis of circuits. -M .: Energy, 1974). Moreover, this converter contains eight majority elements, and the maximum delay time of the signal propagation in it is 5 × Δt _M , where Δt _M is the delay time of the majority element.

The above information allows us to conclude that the proposed logical converter using the tuning constant implements any of the simple symmetric Boolean functions τ ₁ , τ ₂ , τ _n-1 , τ _n , depending on n arguments - input binary signals, for n = 5, it has the hardware composition of the prototype and has a higher speed compared to it.

Claims (1)

A logic converter designed to implement simple symmetric Boolean functions containing eight majority elements, the output of the i-th (i∈ {1, 2, 3, 5}) majority element and the first inputs of the fourth, seventh majority elements respectively connected to the second input ( i + 1) -th majority element and the second tuning input of the logical converter, the first, j-th

the information and first tuning inputs of which are connected respectively to the second input of the first, third input of the (j-1) -th majority elements and the first inputs of the first, second, third, sixth majority elements, characterized in that the second, third inputs of the k-th

the first input and output of the eighth majority elements are connected respectively to the outputs of the (k-1) -th, (2 × k-12) -th majority elements, the first tuning input and the output of the logical converter, the first, second, third and fourth information inputs of which are connected respectively, to the first, second, third inputs of the fifth and third inputs of the sixth majority elements.

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