RU2472209C1 - Logic module - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: logic module is designed to reproduce simple symmetric boolean functions and can be used in digital computing systems as a means of converting codes. The logic module realises any of five simple symmetric boolean functions which depend on five arguments - input binary signals and contains five AND elements, five OR elements and four majority decision elements.

EFFECT: broader functional capabilities owing to use of additional logic elements.

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Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logical modules are known (see, for example, RF patent 2281545, class G06F 7/57, 2006), which implement any of four simple symmetric Boolean functions depending on four arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using well-known logic modules is limited functionality, due to the fact that the implementation of any of the five simple symmetric Boolean functions does not work, depending on five arguments - input binary signals.

The closest device of the same purpose to the claimed invention in terms of features is the logic module adopted for the prototype (RF patent 2286594, class G06F 7/57, 2006), which contains two AND elements, two OR elements, three major elements and implements any of four simple symmetric Boolean functions depending on four arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using the prototype is limited functionality, due to the fact that the implementation of any of the five simple symmetric Boolean functions that depend on five arguments, the input binary signals, is not performed.

The technical result of the invention is the expansion of functionality by providing the implementation of any of five simple symmetric Boolean functions that depend on five arguments, the input binary signals.

элемента И подключены соответственно к первому и второму входам j-го элемента ИЛИ, а первый, второй входы первого и первый, второй входы второго элементов ИЛИ являются соответственно первым, вторым и третьим, четвертым информационными входами логического модуля, особенность заключается в том, что в него дополнительно введены три элемента И, три элемента ИЛИ и мажоритарный элемент, причем первый и второй входы k-го

элемента И подключены соответственно к первому и второму входам k-го элемента ИЛИ, j-й вход и выход третьего элемента ИЛИ соединены соответственно с выходом j-го элемента ИЛИ и третьим входом первого мажоритарного элемента, j-й вход и выход четвертого элемента И подключены соответственно к выходу j-го элемента И и третьему входу четвертого мажоритарного элемента, а первый, второй входы и выход пятого элемента ИЛИ соединены соответственно с выходом третьего элемента И, выходом четвертого элемента ИЛИ и третьим входом второго мажоритарного элемента, подключенного выходом к второму входу третьего мажоритарного элемента, первый, третий входы и выход которого соединены соответственно с третьим настроечным входом логического модуля, выходом пятого элемента И и вторым входом четвертого мажоритарного элемента, подключенного первым входом и выходом соответственно к четвертому настроечному входу и выходу логического модуля, пятый информационный вход которого соединен с вторым входом первого мажоритарного элемента.The specified technical result in the implementation of the invention is achieved by the fact that in a logical module containing two AND elements, two OR elements and three majority elements, in which the first input of the first, first and second inputs of the second majority elements are connected respectively to the first, second tuning inputs of the logical module and the output of the first majority element, the first and second inputs of the j-th

AND elements are connected respectively to the first and second inputs of the jth OR element, and the first, second inputs of the first and first, second inputs of the second OR elements are respectively the first, second and third, fourth information inputs of the logical module, the peculiarity is that in it additionally introduced three AND elements, three OR elements and a majority element, the first and second inputs of the kth

AND elements are connected respectively to the first and second inputs of the kth OR element, the jth input and output of the third OR element are connected respectively to the output of the jth OR element and the third input of the first majority element, the jth input and output of the fourth AND element are connected respectively, to the output of the jth AND element and the third input of the fourth majority element, and the first, second inputs and the output of the fifth OR element are connected respectively to the output of the third AND element, the output of the fourth OR element and the third input of the second majoritarian electronic an element connected by an output to the second input of the third majority element, the first, third inputs and output of which are connected respectively to the third tuning input of the logic module, the output of the fifth AND element and the second input of the fourth majority element connected to the fourth tuning input and output, respectively, of the fourth input and output logic module, the fifth information input of which is connected to the second input of the first majority element.

The drawing shows a diagram of the proposed logical module.

соединен с i-м настроечным входом логического модуля, первый и второй входы элемента 1_m

подключены соответственно к первому и второму входам элемента 2_m, j-й

вход и выход элемента 2₃ соединены соответственно с выходом элемента 2_j и третьим входом элемента 3₁, j-й вход и выход элемента 1₄ подключены соответственно к выходу элемента 1_j и третьему входу элемента 3₄, первый, второй входы и выход элемента 2₅ соединены соответственно с выходами элементов 1₃, 2₄ и третьим входом элемента 3₂, выход элемента 1₅ подключен к третьему входу элемента 3₃, выход предыдущего мажоритарного элемента соединен с вторым входом последующего мажоритарного элемента, а выход элемента 3₄ и второй вход элемента 3₁ образуют соответственно выход и пятый информационный вход логического модуля, первый, второй и третий, четвертый информационные входы которого соединены соответственно с первым, вторым входами элемента 2₁ и первым, вторым входами элемента 2₂.The logic module contains the elements AND 1 ₁ , ..., 1 ₅ , the elements OR 2 ₁ , ..., 2 ₅ and the majority elements 3 ₁ , ..., 3 ₄ , and the first input of the element 3 _i

connected to the i-th training input of the logic module, the first and second inputs of the element 1 _m

connected respectively to the first and second inputs of the element 2 _m , j-th

the input and output of element 2 _{3 are} connected respectively to the output of element 2 _j and the third input of element 3 ₁ , the jth input and output of element 1 _{4 are} connected respectively to the output of element 1 _j and the third input of element 3 ₄ , the first, second inputs and output of the element 2 _{5 are} connected respectively to the outputs of elements 1 ₃ , 2 ₄ and the third input of element 3 ₂ , the output of element 1 _{5 is} connected to the third input of element 3 ₃ , the output of the previous majority element is connected to the second input of the subsequent majority element, and the output of element 3 ₄ and the second input element 3 ₁ form with responsible is the output and the fifth information input of the logic module, the first, second, third, fourth information inputs of which are connected respectively to the first, second inputs of element 2 ₁ and the first, second inputs of element 2 ₂ .

The work of the proposed logical module is as follows.

The binary signals x ₁ , ..., x ₅ ∈ {0,1} and y ₁ , _... , y ₄ ∈ {0,1} are given respectively to its first, ..., fifth information and first, ..., fourth tuning inputs. The signal at the output of the majority element 3 _i (i∈ {1,2,3,4}) is equal to "1"("0") only when signals equal to "1"(" 0 "). Therefore, if at the first input of element 3 _i there is “1” (“0”), then this element will perform an OR (AND) operation on signals acting on its second and third inputs. Thus, at the output of the module, we have

, · есть символы операций ИЛИ, И; τ₁,…,τ₅ есть простые симметричные булевы функции пяти аргументов х₁,…,х₅ (см. стр.126 в книге Поспелов Д.А. Логические методы анализа и синтеза схем. М.: Энергия, 1974).Where

, · There are symbols of operations OR, AND; τ ₁ , ..., τ ₅ are simple symmetric Boolean functions of five arguments x ₁ , ..., x ₅ (see page 126 in the book Pospelov DA Logical methods of analysis and synthesis of circuits. M .: Energy, 1974).

The above information allows us to conclude that the proposed logic module has wider functionality compared to the prototype, as it provides the implementation of any of five simple symmetric Boolean functions that depend on five arguments - input binary signals.

Claims (1)

A logic module designed to implement any of five simple symmetric Boolean functions, depending on five arguments - input binary signals, containing two AND elements, two OR elements and three majority elements, in which the first input of the first, first and second inputs of the second majority elements are connected respectively, with the first, second tuning inputs of the logic module and the output of the first majority element, the first and second inputs of the j-th

AND elements are connected respectively to the first and second inputs of the j-th OR element, and the first, second inputs of the first and first, second inputs of the second OR element are respectively the first, second and third, fourth information inputs of the logic module, characterized in that it additionally introduced three AND elements, three OR elements and a majority element, the first and second inputs of the kth

AND elements are connected respectively to the first and second inputs of the kth OR element, the jth input and output of the third OR element are connected respectively to the output of the jth OR element and the third input of the first majority element, the jth input and output of the fourth AND element are connected respectively, to the output of the jth AND element and the third input of the fourth majority element, and the first, second inputs and the output of the fifth OR element are connected respectively to the output of the third AND element, the output of the fourth OR element and the third input of the second majoritarian electronic an element connected by an output to the second input of the third majority element, the first, third inputs and output of which are connected respectively to the third tuning input of the logic module, the output of the fifth AND element and the second input of the fourth majority element connected to the fourth tuning input and output, respectively, of the fourth input and output logic module, the fifth information input of which is connected to the second input of the first majority element.