RU2286594C1 - Logic module - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: logic module contains two majority elements, AND element and OR element, first and second inputs of which are connected respectively to first, second inputs of AND element, while second, first inputs and output of second majority element are connected respectively to output of first majority element, second adjustment input and output of logic module. Introduced additionally are additional element AND, element OR and third majority element, output and second, third inputs of which are connected to respectively to third input of second majority element and output of element OR, output of additional element AND, connected by its first, second inputs respectively to first, second inputs of additional element OR, output of which is connected to second input of first majority element, connected by third input to output of element AND, first and second inputs of which are connected respectively to first and second information inputs of logic module, connected by third, fourth information and first adjustment inputs respectively to first, second inputs of additional element OR and to combined first inputs of first, third majority elements.

EFFECT: expanded functional capabilities due to provision of realization of any one of four simple symmetric Boolean functions, depending on four arguments - input binary signals.

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Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logical modules are known (see, for example, Fig. 18.2a on page 315 in the book by A. Kayatskas, Fundamentals of Radio Electronics. M.: Higher School, 1988), which implement a simple symmetric Boolean function τ ₂ = x ₁ x ₂ ∨x ₁ x ₃ ∨x ₂ x ₃ , depending on three arguments - input binary signals x ₁ , x ₂ , x ₃ ∈ {0, 1}.

The reason that impedes the achievement of the technical result indicated below when using well-known logic modules is limited functionality, due to the fact that the implementation of any of the four simple symmetric Boolean functions does not work, depending on four arguments - input binary signals.

The closest device of the same purpose to the claimed invention in terms of features is the logical module adopted for the prototype (RF patent 2249844, CL G 06 F 7/38, 2005), which contains two major elements, the element "And", element "OR" and implements any of the three simple symmetric Boolean functions τ ₁ = x ₁ ∨ x ₂ ∨ x ₃ , τ ₂ = x ₁ x ₂ ∨ x ₁ x ₃ ∨ x ₂ x ₃ , τ ₃ = x ₁ x ₂ x ₃ depending on three arguments - input binary signals x ₁ , x ₂ , x ₃ ∈ {0, 1}.

The reason that impedes the achievement of the technical result indicated below when using the prototype is limited functionality, due to the fact that the implementation of any of the four simple symmetric Boolean functions does not work, depending on four arguments - input binary signals.

The technical result of the invention is the expansion of functionality by providing the implementation of any of four simple symmetric Boolean functions, depending on four arguments - input binary signals.

The specified technical result during the implementation of the invention is achieved by the fact that in a logical module containing two majority elements, an AND element and an OR element, the first, second inputs of which are connected respectively to the first, second inputs of the AND element, and the second, first the inputs and output of the second majority element are connected respectively to the output of the first majority element, the second tuning input and output of the logic module, additional elements "AND", the element "OR" and the third majority element, the output and the second are introduced , the third inputs of which are connected respectively with the third input of the second majority element and the output of the element "OR", the output of the additional element "AND" connected by the first, second inputs, respectively, to the first, second inputs of the additional element "OR", the output of which is connected to the second input of the first majority element connected by the third input to the output of the element "And", the first and second inputs of which are connected respectively to the first and second information inputs of the logic module connected to the third, fourth fifth information and the first tuning input respectively to the first and second inputs of the additional element "OR" and the combined first inputs of the first, third majority elements.

The drawing shows a diagram of the proposed logical module.

The logic module contains an AND element and an additional AND element 1 ₁ and 1 ₂ , an OR element and an additional OR element 2 ₁ and 2 ₂ , the first, second and third major elements 3 ₁ , 3 ₂ and 3 ₃ moreover, the first, second inputs and output of the element 1 _{1 are} connected respectively to the first, second inputs of the element 2 ₁ and the third input of the element 3 ₁ connected by the second input to the output of the element 2 ₂ , and the first, second inputs and output of the element 1 _{2 are} connected respectively with the first, second inputs of element 2 ₂ and the third input of element 3 ₃ connected to the second input and output of co respectively, to the output of element 2 ₁ and the third input of element 3 ₂ , the second, first inputs and output of which are connected respectively to the output of element 3 ₁ , the second training input and the output of the logic module connected to the first, second, third, fourth information and first training inputs, respectively to the first, second inputs of the element 2 ₁ , the first, second inputs of the element 2 ₂ and the combined first inputs of the elements 3 ₁ , 3 ₃ .

The work of the proposed logical module is as follows. Binary signals x ₁ , ..., x ₄ ∈ {0, 1} and y ₁ , y ₂ ∈ {0, 1} are supplied to its first, ..., fourth information and first, second tuning inputs, respectively. The signal at the output of the majority element 3 _i (i∈ {1, 2, 3}) is equal to "1"("0") only when signals equal to "1"("0" act on two or all inputs of this element ) Therefore, if "1"("0") is present at the first input of element 3 _i , then this element will perform the operation "OR"("AND") on the signals acting on its second and third inputs. Thus, at the output of the module, we have

where the symbols ∨ and · denote the operations "OR" and "AND", respectively.

The above information allows us to conclude that the proposed logic module has wider functionality compared to the prototype, as it provides the implementation of any of four simple symmetric Boolean functions

τ ₁ = x ₁ ∨x ₂ ∨x ₃ ∨x ₄ , τ ₂ = x ₁ x ₂ ∨x ₁ x ₃ ∨x ₁ x ₄ 4x ₂ x ₃ ∨x ₂ x ₄ ∨x ₃ x ₄ , τ ₃ = x ₁ x ₂ x ₃ ∨x ₁ x ₂ x ₄ ∨x ₁ x ₃ x ₄ ∨x ₂ x ₃ x ₄ , τ ₄ = x ₁ x ₂ x ₃ x ₄ ,

depending on four arguments - input binary signals.

Claims (1)

A logic module designed to implement any of four simple symmetric Boolean functions, depending on four arguments - input binary signals, containing two majority elements, an AND element and an OR element, the first and second inputs of which are connected respectively to the first, second inputs of the element And, and the second, first inputs and output of the second majority element are connected respectively to the output of the first majority element, the second tuning input and output of the logic module, characterized in that it is introduced s additional AND element, OR element and the third majority element, the output and the second, third inputs of which are connected respectively to the third input of the second majority element and the output of the OR element, the output of the additional element AND, connected by the first, second inputs, respectively, to the first, second inputs of the additional element OR, the output of which is connected to the second input of the first majority element connected by the third input to the output of the AND element, the first and second inputs of which are connected respectively to the first and the second information inputs of the logic module connected to the third, fourth information and first tuning inputs respectively to the first, second inputs of the additional OR element and the combined first inputs of the first, third major elements.