RU2700550C1 - Logic module - Google Patents

Abstract

FIELD: computer equipment.

SUBSTANCE: invention relates to the computer equipment. Logic module comprises four majority elements, which have three inputs, wherein first input of third majority element and first input of first majority element, connected by output to second input of second majority element, the first input of the fourth majority element is connected to the second and the first tuning inputs of the logic module, additionally there are six analogues of said majority elements, the second and third inputs of the j-th, second and third inputs of the k-th majority elements are connected to outputs (j-1)-th and (j+2)-th, (k+2)-th and (k+4)-th majority elements, and the output of the fourth and second inputs of the ninth majority elements are connected to the output and the third tuning input of the logic module, respectively, the first tuning input of which is connected to the first inputs of the second, fifth, sixth, seventh and ninth majority elements.

EFFECT: broader functional capabilities of the logic module by providing implementation of any of simple symmetric Boolean functions τ₁, τ₂, τ_n-1, τ_n, depending on n arguments – input binary signals, at n=7.

1 cl, 1 dwg

Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logical modules are known (RF patent 2248034, CL G06F 7/38, 2005; RF patent 2281545, CL G06F 7/57, 2006) that implement any of the simple symmetric Boolean functions τ ₁ , τ ₂ , τ _n-1 , τ _n , depending on n arguments - input binary signals, for n = 4.

The reason that impedes the achievement of the technical result indicated below when using well-known logical modules includes limited functionality, due to the fact that the implementation of any of the functions τ ₁ , τ ₂ , τ _n-1 , τ _n with n = 7 is not provided.

The closest device of the same purpose to the claimed invention in terms of features is the logic module adopted for the prototype (RF patent 2393528, class G06F 7/57, 2010), which contains four majority elements and implements any of the simple symmetric Boolean functions τ ₁ , τ ₂ , τ _n-1 , τ _n , depending on n arguments - input binary signals, for n = 4.

The reason that impedes the achievement of the technical result indicated below when using the prototype is limited functionality due to the fact that the implementation of any of the functions τ ₁ , τ ₂ , τ _n-1 , τ _n with n = 7 is not provided.

The technical result of the invention is the expansion of functionality by providing the implementation of any of the simple symmetric Boolean functions τ ₁ , τ ₂ , τ _n-1 , τ _n , depending on n arguments - input binary signals, with n = 7.

второй и третий входы k-го

мажоритарных элементов соединены соответственно с выходами (j-1)-го и (j+2)-го, (k+2)-го и (k+4)-го мажоритарных элементов, а выход четвертого и второй вход девятого мажоритарных элементов подключены соответственно к выходу и третьему настроечному входу логического модуля, первый настроечный вход которого соединен с первыми входами второго, пятого, шестого, седьмого и девятого мажоритарных элементов.The specified technical result in the implementation of the invention is achieved by the fact that in a logic module containing four majority elements that have three inputs, the first input of the third majority element and the first input of the first majority element connected by the output to the second input of the second majority element, the first input of the fourth majority elements are connected respectively with the second and first tuning inputs of the logic module, the peculiarity is that six more ogichnyh majority said elements, second and third inputs j-th

second and third inputs of the k-th

majority elements are connected respectively to the outputs of the (j-1) -th and (j + 2) -th, (k + 2) -th and (k + 4) -th major elements, and the output of the fourth and second input of the ninth majority elements are connected respectively, to the output and the third tuning input of the logic module, the first tuning input of which is connected to the first inputs of the second, fifth, sixth, seventh and ninth major elements.

The drawing shows a diagram of the proposed logical module.

второй и третий входы элемента 1_k

соединены соответственно с выходами элементов 1₁, 1_j-1 и 1_j+2, 1_k+2 и 1_k+4, а выход элемента 1₄ и первый вход элемента 1₃, второй вход элемента 1₉ подключены соответственно к выходу и второму, третьему настроечным входам логического модуля, первый настроечный вход которого соединен с первыми входами элементов 1₁, 1₂, 1₄, 1₅, 1₆, 1₇, 1₉.The logic module contains the majority elements 1 ₁ , ..., 1 ₁₀ , which have three inputs, the second input of the element 1 ₂ , the second and third inputs of the element 1 _j

second and third inputs of element 1 _k

connected respectively to the outputs of elements 1 ₁ , 1 _j-1 and 1 _{j + 2} , 1 _{k + 2} and 1 _{k + 4} , and the output of element 1 ₄ and the first input of element 1 ₃ , the second input of element 1 _{9 are} connected respectively to the output and the second, third tuning inputs of the logic module, the first tuning input of which is connected to the first inputs of the elements 1 ₁ , 1 ₂ , 1 ₄ , 1 ₅ , 1 ₆ , 1 ₇ , 1 ₉ .

имеем

где

есть соответственно сигналы на его первом, втором, третьем входах и символы операций ИЛИ, И. Следовательно, сигнал на выходе элемента 1₄ определяется выражением Z=ƒ₁(ƒ₂y₁∨ƒ₂y₂∨y₁y₂)∨ƒ₁y₃∨(ƒ₂y₁∨ƒ₂y₂∨y₁y₂)y₃, в которомThe work of the proposed logical module is as follows. The necessary binary signals ƒ ₁ , ƒ ₂ , ƒ ₃ ∈ {0,1} are respectively supplied to its first, second, third tuning inputs. At the second input of element 1 ₁ , the first input of element 1 ₈ ; the third input of the element 1 ₁ , the second input of the element 1 ₈ ; the third inputs of the elements 1 ₂ , 1 ₈ ; the second input of element 1 ₇ , the first input of element 1 ₁₀ ; the third input of element 1 ₇ , the second input of element 1 ₁₀ ; the third inputs of the elements 1 ₉ , 1 ₁₀ are supplied, respectively, binary signals x ₁ ; x ₂ ; x ₃ ; x ₄ ; x ₅ ; x ₆ (x ₁ , ..., x ₆ ∈ {0,1}). At the output of element 1 _i

we have

Where

there are, respectively, signals at its first, second, third inputs and operation symbols OR, I. Therefore, the signal at the output of element 1 ₄ is determined by the expression Z = ƒ ₁ (ƒ ₂ y ₁ ∨ƒ ₂ y ₂ ∨y ₁ y ₂ ) ∨ƒ ₁ y ₃ ∨ (ƒ ₂ y ₁ ∨ƒ ₂ y ₂ ∨y ₁ y ₂ ) y ₃ , in which

y ₁ = ƒ ₁ (ƒ ₁ x ₁ ∨ƒ ₁ x ₂ ∨x ₁ x ₂ ) ∨ƒ ₁ x ₃ ∨ (ƒ ₁ x ₁ ∨ƒ ₁ x ₂ ∨x ₁ x ₂ ) x ₃ ;

y ₂ = ƒ ₁ (ƒ ₁ x ₄ ∨ƒ ₁ x ₅ ∨x ₄ x ₅ ) ∨ƒ ₁ (ƒ ₁ ƒ ₃ ∨ƒ ₁ x ₆ ∨ƒ ₃ x ₆ ) ∨

∨ (ƒ ₁ x ₄ ∨ƒ ₁ x ₅ ∨x ₄ x ₅ ) (ƒ ₁ ƒ ₃ ∨ƒ ₁ x ₆ ∨ƒ ₃ x ₆ );

y ₃ = ƒ ₁ (x ₁ x ₂ ∨x ₁ x ₃ ∨x ₂ x ₃ ) ∨ƒ ₁ (x ₄ x ₅ ∨x ₄ x ₆ ∨x ₅ x ₆ ) ∨

∨ (x ₁ x ₂ ∨x ₁ x ₃ ∨x ₂ x ₃ ) (x ₄ x ₅ ∨x ₄ x ₆ ∨x ₅ x ₆ ).

Thus, at the output of the proposed logical module, we obtain

where τ ₁ , τ ₂ , τ ₆ , τ ₇ are simple symmetric Boolean functions of seven arguments x ₁ , ..., x ₇ (see page 126 in the book Pospelov DA Logical methods of analysis and synthesis of circuits. M .: Energy , 1974).

The above information allows us to conclude that the proposed logic module has wider functionality compared to the prototype, since it implements any of the simple symmetric Boolean functions τ ₁ , τ ₂ , τ _n-1 , τ _n , depending on n arguments - input binary signals, with n = 7.

Claims (1)

A logic module designed to implement simple symmetric Boolean functions, containing four majority elements that have three inputs, the first input of the third majority element and the first input of the first majority element connected to the second input of the second majority element, the first input of the fourth majority element connected respectively, with the second and first tuning inputs of the logic module, characterized in that it additionally introduces six similar to the mentioned m zhoritarnyh elements, second and third inputs j-th

second and third inputs k

majority elements are connected respectively to the outputs of the (j-1) -th and (j + 2) -th, (k + 2) -th and (k + 4) -th major elements, and the output of the fourth and second input of the ninth majority elements are connected respectively, to the output and the third tuning input of the logic module, the first tuning input of which is connected to the first inputs of the second, fifth, sixth, seventh and ninth major elements.

Images