RU2281545C1 - Logical transformer - Google Patents

Abstract

FIELD: computer engineering, possible use for construction of automatic devices, functional assemblies of control systems.

SUBSTANCE: device contains seven majority elements, four information inputs, two adjustment inputs.

EFFECT: increased speed of operation.

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Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logic converters are known (see, for example, Fig. 18.2a on page 315 in the book by A. Kayatskas, Fundamentals of Radio Electronics. M .: Higher School, 1988), which implement a simple symmetric Boolean function τ ₂ = x ₁ x ₂ ∨ x ₁ x ₃ ∨ x ₂ x ₃ , depending on three arguments - input binary signals x ₁ , x ₂ , x ₃ , x ₃ ∈ {0,1}.

The reason that impedes the achievement of the technical result indicated below when using known logic converters is limited functionality, due to the fact that the implementation of any of the four simple symmetric Boolean functions does not work, depending on four arguments - input binary signals.

The closest device of the same purpose to the claimed invention in terms of features is the logic converter adopted for the prototype (RF patent 2248034, class G 06 F 7/38, 2005), which contains seven major elements and implements any of four simple symmetric Boolean functions τ ₁ = x _{1 2} ∨h ∨h ₃ ∨h _4, τ ₂ = x ₁ x ₂ x _{3 1} ∨h ∨h ₄ ∨h ₁ x ₂ x ₃ x _{4 2} ∨h ∨h ₃ x _4, τ ₃ = x ₁ x ₂ x ₃ ∨ x ₁ x ₂ x ₄ ∨ x ₁ x ₃ x ₄ ∨ x ₂ x ₃ x ₄ , τ ₄ = x ₁ x ₂ x ₃ x ₄ , depending on four arguments - binary input signals x ₁ , x ₂ , x ₃ , x ₄ ∈ {0,1}.

The reason that impedes the achievement of the technical result indicated below when using the prototype is the low speed due to the fact that the maximum signal propagation delay time in the prototype is determined by the expression Δt = 6Δt _M , where Δt _M is the delay time of the majority element.

The technical result of the invention is to increase performance while maintaining the functionality of the prototype.

мажоритарного элемента соединен с вторым входом (i+3)-го мажоритарного элемента, а i-ый вход и выход седьмого мажоритарного элемента подключены соответственно к выходу (i+3)-го мажоритарного элемента и выходу логического преобразователя, первый и второй настроечные входы которого образованы соответственно объединенными первыми входами первого - третьего и объединенными первыми входами четвертого - шестого мажоритарных элементов.The specified technical result in the implementation of the invention is achieved by the fact that in a logical converter containing seven majority elements and connected by the first information input to the combined second inputs of the first to third majority elements, the feature is that the combined third inputs of the first, sixth and combined third inputs of the second , the fourth majority elements form respectively the second and third information inputs of the logical converter, the fourth information od which is formed by the combined third inputs of the third, fifth majority element out i-th

the majority element is connected to the second input of the (i + 3) -th majority element, and the i-th input and output of the seventh majority element are connected respectively to the output of the (i + 3) -th majority element and the output of the logic converter, whose first and second tuning inputs are formed respectively by the combined first inputs of the first - third and the combined first inputs of the fourth - sixth majority elements.

The drawing shows a diagram of the proposed logical Converter.

соединен с вторым входом элемента 1_i+3, а i-ый вход и выход элемента 1₇ подключены соответственно к выходу элемента 1_i+3 и выходу логического преобразователя, первый и второй настроечные входы которого образованы соответственно объединенными первыми входами элементов 1₁-1₃ и объединенными первыми входами элементов 1₄-1₆.The logical converter contains the majority elements 1 ₁ -1 ₇ , and the combined second inputs of the elements 1 ₁ -1 ₃ and the combined third inputs of the elements 1 ₁ , 1 _{6 are} connected respectively to the first and second information inputs of the logical converter connected to the third and fourth information inputs, respectively combined third inputs of elements 1 ₂ , 1 ₄ and combined third inputs of elements 1 ₃ , 1 ₅ , output of element 1 _i

connected to the second input of the element 1 _{i + 3} , and the i-th input and output of the element 1 _{7 are} connected respectively to the output of the element 1 _{i + 3} and the output of the logic converter, the first and second tuning inputs of which are formed respectively by the combined first inputs of the elements 1 ₁ -1 ₃ and the combined first inputs of the elements 1 ₄ -1 ₆ .

имеем а_k1#а_k2#а_k3=а_k1а_k2∨a_k1a_k3∨a_k2a_k3, где а_k1, а_k2, а_k3 и #, ∨, · есть соответственно сигналы на его первом, втором, третьем входах и символы операций Maj, ИЛИ, И. Следовательно, если на первом входе элемента 1_k присутствует "1" либо "0", то этот элемент будет выполнять операцию а_k2∨a_k3 либо а_k2а_k3. Таким образом, на выходе предлагаемого преобразователя получимThe work of the proposed logical Converter is as follows. Binary signals x ₁ -x ₄ ∈ {0,1} and f ₁ , f ₂ ∈ {0,1} are supplied to its first - fourth information and first, second training inputs. At the output of the majority element 1 _k

we have a _k1 # a _k2 # a _k3 = a _k1 a _k2 ∨a _k1 a _k3 ∨a _k2 a _k3 , where a _k1 , a _k2 , and _k3 and #, ∨, · there are signals on its first, second, third inputs and symbols of operations Maj, OR, I. Therefore, if the first input of element 1 _k contains "1" or "0", then this element will perform the operation a _k2 ∨a _k3 or a _k2 a _k3 . Thus, at the output of the proposed Converter get

The above information allows us to conclude that the proposed logic converter implements any of the four simple symmetric Boolean functions τ ₁ = x ₁ ∨x ₂ ∨x ₃ ∨x ₄ , τ ₂ = x ₁ x ₂ ∨x ₁ x ₃ ∨x ₁ x ₄ ∨x ₂ x ₃ ∨x ₂ x ₄ ∨x ₃ x ₄ , τ ₃ = x ₁ x ₂ x ₃ ∨x ₁ x ₂ x ₄ ∨x ₁ x ₃ x ₄ ∨x ₂ x ₃ x ₄ , τ ₄ = x ₁ x ₂ x ₃ x ₄ , depending on four arguments - input binary signals x ₁ , x ₂ , x ₃ , x ₄ ∈ {0,1}, and has a higher speed compared to the prototype, since the maximum delay time the signal propagation in the specified Converter is determined by the expression Δt = 3Δt _M , where Δt _M ec The delay time of the majority element. An additional advantage of the proposed logical converter is four major elements smaller in comparison with the prototype hardware.

Claims (1)

A logic converter for implementing any of the four simple symmetric Boolean functions, containing seven majority elements and connected by the first information input to the combined second inputs of the first or third majority elements, characterized in that the combined third inputs of the first, sixth and combined third inputs of the second, fourth majority elements form respectively the second and third information inputs of the logical converter, the fourth information input of which is formed by the third inputs of the third, fifth majority elements, the output of the i-th

the majority element is connected to the second input of the (i + 3) -th majority element, and the i-th input and output of the seventh majority element are connected respectively to the output of the (i + 3) -th majority element and the output of the logic converter, whose first and second tuning inputs are formed respectively by the combined first inputs of the first to third and the combined first inputs of the fourth to sixth majority elements.