RU2580801C1 - Majority module - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in digital computer systems as an information preprocessing means. Majority module comprises two AND elements (11, 12), two OR elements (21, 22) and nine majority elements (31, … , 39). Due to the above elements and new circuits of their connection, the depth of which is equal to four, five processing input binary signals. As a result is achieved broadening of functional capabilities of majority module and reduced relative value of circuit depth.

EFFECT: technical result consists in expansion of functional capabilities, particularly, to implement a majority function of several arguments - input binary signals or disjunction (conjunction) of the same arguments.

1 cl, 1 dwg

Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

, где n=3, h=3 и $$\tilde{h}$$

есть соответственно количество аргументов реализуемых функций, глубина схемы и относительный показатель схемной глубины.Majority modules are known (see, for example, RF patent 2398265, class G06F 7/57, 2010), which, using constant settings, implement the majority function Maj (x ₁ , x ₂ , x ₃ ) = x ₁ x ₂ ∨ x ₁ x ₃ ∨ x ₂ x _{3 of} three arguments - input binary signals x ₁ , x ₂ , x ₃ ∈ {0,1} or a disjunction (conjunction) of the same three arguments. Wherein

where n = 3, h = 3 and $$\tilde{h}$$

there are, accordingly, the number of arguments of the implemented functions, the depth of the circuit, and a relative indicator of the circuit depth.

The reason that impedes the achievement of the technical result indicated below when using known majority modules includes limited functionality, due to the fact that processing of five input signals is not allowed, and a large value of the relative indicator of the circuit depth.

.The closest device of the same purpose to the claimed invention in terms of features is the majority module adopted for the prototype (RF patent 2249844, class G06F7 / 38, 2005), which contains the AND element, the OR element, two majority elements and implements the Maj majority function (x ₁ , x ₂ , x ₃ ) = x ₁ x ₂ ∨ x ₁ x ₃ ∨ x ₂ x ₃ three arguments - input binary signals x ₁ , x ₂ , x ₃ ∈ {0,1} or a disjunction (conjunction) the same three arguments. Moreover, n = 3, h = 3 and

.

The reason that impedes the achievement of the technical result indicated below when using the prototype is limited functionality due to the fact that processing of five input signals is not allowed, and a large value of the relative indicator of the circuit depth.

The technical result of the invention is the expansion of functionality by ensuring the implementation of the majority function of the five arguments - input binary signals or disjunction (conjunction) of the same five arguments and a decrease in the relative index of the circuit depth.

The specified technical result during the implementation of the invention is achieved by the fact that in the majority module containing the element AND, the OR element and two majority elements, the first input of the first, first and second inputs of the second majority elements are connected respectively to the first, second tuning inputs of the majority module and the output of the first majority element, the peculiarity lies in the fact that the element AND, the OR element and seven majority elements are combined into it, the combined third input of the second, second input of the fifth majority elements, the combined first input of the first OR element, the second input of the fourth, third input of the sixth majority elements, the combined second input of the first OR element, the second input of the first, third input of the fifth majority elements, the combined second input of the first AND element, the third input of the first, second input of the eighth majority elements and the combined second input of the second element And, the third inputs of the fourth, eighth majority elements form respectively the first, second, third, fourth and fifth information the inputs of the majority module, the outputs of the first OR element and the fifth majority element are connected respectively to the first input of the first AND element and combined by the first input of the second AND element, the second input of the sixth majority element, the second, third inputs of the i-th (i∈ {3,7} ) of the majority element and the first, second inputs of the second OR element are connected respectively to the outputs of the (i-1) -th, (i + 1) -th majority elements and the outputs of the first, second elements And, and the first, second, third inputs and output of the ninth majority element connected respectively, with the outputs of the third, seventh majority elements, the second OR element and the output of the majority module, the first and second tuning inputs of which are connected respectively to the combined first inputs of the third, fifth, seventh and combined first inputs of the fourth, sixth, eighth majority elements.

In the drawing. The scheme of the proposed majority module is presented.

The majority module contains the elements AND 1 ₁ , 1 ₂ , the elements OR 2 ₁ , 2 ₂ and the majority elements 3 ₁ , ..., 3 ₉ , the combined third input of the element 3 ₂ , the second input of the element 3 ₅ , the combined first input of the element 2 ₁ , second input of element 3 ₄ , third input of element 3 ₆ , combined third input of element 3 ₅ , second inputs of elements 2 ₁ , 3 ₁ , combined third input of element 3 ₁ , second inputs of elements 1 ₁ , 3 ₈ and combined second input of element 1 ₂ , third inputs members 3 _4, 3 ₈ form, respectively, first, second, third, fourth and fifth information WMOs s majority module outputs elements 2 _1, 3 ₁ and 3 ₅ are connected respectively to the first input element 1 _1, the second input element 3 is ₂ and the combined first input element 1, ₂ second input member 3 _6, a second, a third input element 3 _i ( i∈ {3,7}) and the first, second inputs of element 2 _{2 are} connected respectively to the outputs of elements 3 _i-1 , 3 _{i + 1} and 1 ₁ , 1 ₂ , and the first, second, third inputs and output of element 3 _{9 are} connected respectively, with the outputs of the elements 3 ₃ , 3 ₇ , 2 ₂ and the output of the majority module, the first and second tuning inputs of which are connected respectively to the combined first inputs of the elements 3 ₁ , 3 ₃ , 3 ₅ , 3 ₇ and the combined first inputs of the elements 3 ₂ , 3 ₄ , 3 ₆ , 3 ₈ .

The work of the proposed majority module is as follows.

имеем a_j1#a_j2#a_j3=a_j1a_j2∨а_j3∨a_j2a_j3, где а_j1,а_j2,а_j3 и #,∨, • есть соответственно сигналы на его первом, втором, третьем входах и символы операций Maj, ИЛИ, И. Следовательно, сигнал на выходе элемента 3₉ определяется выражениемThe binary signals x ₁ , ..., x ₅ ∈ {0,1} and ₁ , y ₂ ∈ {0,1}, respectively, are fed to its first, ..., fifth information and first, second tuning inputs. At the output of the majority element

have _{a j1 #a j2 #a j3 = a} j1 a j2 _j3 ∨a ∨a _{j2 j3} a, where a is _j1, and _j2, and _j3 and #, ∨, • have respectively the signals at its first, second, and third inputs symbols of operations Maj, OR, I. Therefore, the signal at the output of element 3 ₉ is determined by the expression

Таким образом, на выходе предлагаемого модуля получимWhere

Thus, at the output of the proposed module, we obtain

схемной глубины составляют h=4 и

.The above information allows us to conclude that the proposed majority module has a wider functionality compared to the prototype, as it implements the majority function n = 5 arguments - input binary signals or disjunction (conjunction) of the same five arguments. Moreover, the depth h of the scheme of the proposed majority module and the relative indicator $$\tilde{h}$$

the design depths are h = 4 and

.

Claims (1)

A majority module containing an AND element, an OR element, and two majority elements, the first input of the first, first and second inputs of the second majority elements being connected respectively to the first, second tuning inputs of the majority module and the output of the first majority element, characterized in that they are additionally introduced AND element, OR element, and seven majority elements, combined third input of the second, second input of the fifth majority elements, combined first input of the first OR element, second fourth input go, the third input of the sixth majority elements, the combined second input of the first OR element, the second input of the first, the third input of the fifth majority elements, the combined second input of the first AND element, the third input of the first, second input of the eighth majority elements and the combined second input of the second AND element, third the inputs of the fourth, eighth majority elements form, respectively, the first, second, third, fourth and fifth information inputs of the majority module, the outputs of the first OR element and the fifth majority element a are connected respectively to the first input of the first AND element and combined by the first input of the second AND element, the second input of the sixth majority element, the second, third inputs of the i-th (i∈ {3,7}) majority element and the first, second inputs of the second OR element are connected respectively, to the outputs of the (i-1) -th, (i + 1) -th major elements and the outputs of the first, second elements And, and the first, second, third inputs and output of the ninth major element are connected respectively to the outputs of the third, seventh major elements, second element OR yield majority module, the first and second tuning inputs are connected respectively to the combined first inputs of the third, fifth, seventh, and the combined first inputs of the fourth, sixth, eighth majority elements.

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