RU2747107C1 - Majority module - Google Patents

Abstract

FIELD: math.SUBSTANCE: invention relates to a majority module. The majority module contains four majority elements, and the second input of the fourth majority element is connected to the output of the second majority element, and two EXCLUSIVE OR elements are additionally introduced into it, the i-thinput of the j-thand the first, third inputs of the fourth majority elements are connected respectively with the i-th input of the j-th EXCLUSIVE OR element and the outputs of the third, first majority elements, the second input and output of the second EXCLUSIVE OR element are connected respectively to the output of the first EXCLUSIVE OR element and the second input of the third majority element, and the i-th input of the first, the first and the third inputs of the second EXCLUSIVE OR elements and the first, third inputs of the third majority element are connected respectively to the i-th, fourth, fifth and sixth, seventh inputs of the majority module, the output of which is the output of the fourth majority element.EFFECT: simplified the scheme of the majority module.1 cl, 2 tbl, 1 dwg

Description

The invention relates to computer technology and can be used to build automation tools, functional units of control systems, etc.

Majority modules are known (RF patent 2294007, class G06F 7/57, 2007; RF patent 2393527, class G06F 7/57, 2010), which contain logic elements and implement the majority function

five arguments - input binary signals х1, ..., х ₅ ∈ {0, l}.

The reason that prevents the achievement of the technical result indicated below when using the known majority modules is limited functionality and circuit complexity, due, respectively, to the fact that the implementation of the majority function of seven arguments is not provided and the lowest of the Quine prices of the schemes of the mentioned analogs is 24.

The closest device for the same purpose to the claimed invention in terms of a set of features is the majority module adopted as a prototype (RF patent 2700554, class G06F 7/57, 2019), which contains logic elements and implements the majority function of seven arguments - input binary signals.

The reason that prevents the achievement of the technical result indicated below when using the prototype is the circuit complexity due to the fact that the Quine price of the prototype circuit is 26 and the hardware composition of this circuit is formed from logical elements of four types (NOT element, AND elements, OR elements, majority elements).

The technical result of the invention is to simplify the scheme of the majority module by reducing its price according to Quine and reducing the number of types of logical elements of the hardware composition while maintaining the functionality of the prototype.

вход

и первый, третий входы четвертого мажоритарных элементов соединены соответственно с i-ым входом j-го элемента ИСКЛЮЧАЮЩЕЕ ИЛИ и выходами третьего, первого мажоритарных элементов, второй вход и выход второго элемента ИСКЛЮЧАЮЩЕЕ ИЛИ соединены соответственно с выходом первого элемента ИСКЛЮЧАЮЩЕЕ ИЛИ и вторым входом третьего мажоритарного элемента, а i-й вход первого, первый, третий входы второго элементов ИСКЛЮЧАЮЩЕЕ ИЛИ и первый, третий входы третьего мажоритарного элемента соединены соответственно с i-ым, четвертым, пятым и шестым, седьмым входами мажоритарного модуля, выходом которого является выход четвертого мажоритарного элемента.The specified technical result in the implementation of the invention is achieved by the fact that in the majority module containing four majority elements, the second input of the fourth majority element is connected to the output of the second majority element, the peculiarity is that two EXCLUSIVE OR elements are additionally introduced into it, the i-th

entrance

and the first, third inputs of the fourth majority elements are connected, respectively, with the i-th input of the j-th element EXCLUSIVE OR and the outputs of the third, first majority elements, the second input and output of the second EXCLUSIVE OR element are connected, respectively, with the output of the first EXCLUSIVE OR element and the second input of the third majority element element, and the i-th input of the first, first, third inputs of the second EXCLUSIVE OR elements and the first, third inputs of the third majority element are connected respectively to the i-th, fourth, fifth and sixth, seventh inputs of the majority module, the output of which is the output of the fourth majority element ...

The drawing shows a diagram of the proposed majority module.

вход элемента 2_j

и i-й вход элемента 2₄ соединены соответственно с i-ым входом элемента 1_j и выходом элемента 2_4-i, второй вход и выход элемента 1₂ соединены соответственно с выходом элемента 1₁ и вторым входом элемента 2₃, а i-й вход элемента 1₁, первый, третий входы элемента 1₂ и первый, третий входы элемента 2₃ соединены соответственно с i-ым, четвертым, пятым и шестым, седьмым входами мажоритарного модуля, выходом которого является выход элемента 2₄.The majority module contains the EXCLUSIVE OR elements 1 ₁ , 1 ₂ and the majority elements 2 ₁ , 2 ₂ , 2 ₃ , 2 ₄ , and the i-th

input of element 2 _j

and the i-th input of element 2 _{4 are} connected, respectively, with the i-th input of element 1 _j and the output of element 2 _4-i , the second input and output of element 1 _{2 are} connected, respectively, with the output of element 1 ₁ and the second input of element 2 ₃ , and i- the i-th input of element 1 ₁ , the first, third inputs of element 1 ₂ and the first, third inputs of element 2 _{3 are} connected respectively to the i-th, fourth, fifth and sixth, seventh inputs of the majority module, the output of which is the output of element 2 ₄ .

2_k

имеемThe proposed majority module operates as follows. On its first, ..., seventh inputs, respectively, binary signals x ₁ , ..., x ₇ ∈ {01} are supplied. At the outputs of elements 1j

2 _k

we have

- сигналы на их i-ых входах. В представленных ниже табл. 1 и табл. 2 приведены соответственно значения внутренних сигналов z₁,z₂,z₃ предлагаемого мажоритарного модуля, полученные с учетом (1), (2) для всех возможных наборов значений сигналов х₁,…,х₅, и значения его выходногоWhere

- signals at their i-th inputs. In the tables below. 1 and tab. 2 shows, respectively, the values of the internal signals z ₁ , z ₂ , z _{3 of the} proposed majority module, obtained taking into account (1), (2) for all possible sets of signal values x ₁ , ..., x ₅ , and the values of its output

signal Z obtained taking into account (2) for all possible sets of signal values z ₁ , z ₂ , z ₃ , x ₆ , x ₇ .

According to the data given in table. 1, tab. 2, we have

where Maj (x ₁ ,…, x ₇ ) is the majority function of seven arguments x ₁ ,…, x ₇ .

The above information allows us to conclude that the proposed majority module implements the majority function of seven arguments - input binary signals, while the scheme of the proposed majority module is simpler than that of the prototype, since its Quine price is 18 and the hardware composition is formed from logical elements of two types.

Claims (1)

Majority module containing four majority elements, and the second input of the fourth majority element is connected to the output of the second majority element, characterized in that it additionally contains two EXCLUSIVE OR elements, the i-th

j-th input

and the first, third inputs of the fourth majority elements are connected, respectively, with the i-th input of the j-th element EXCLUSIVE OR and the outputs of the third, first majority elements, the second input and output of the second EXCLUSIVE OR element are connected, respectively, with the output of the first EXCLUSIVE OR element and the second input of the third majority element element, and the i-th input of the first, first, third inputs of the second EXCLUSIVE OR elements and the first, third inputs of the third majority element are connected respectively to the i-th, fourth, fifth and sixth, seventh inputs of the majority module, the output of which is the output of the fourth majority element ...

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