RU2538949C1 - Pulse counting method and device - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: each decimal digit of the device contains four binary digits, each of them containing one RS-trigger, three logic AND elements, two logic OR elements, three logic NOT elements. Each decimal digit contains as well four logic AND elements, one logic OR element, input for common trigger setting of tetrads to zero, input of counting pulses from the lowest tetrad, output of counting pulses to the most significant tetrad.

EFFECT: increased operational speed of pulse counting operation.

2 cl, 2 dwg

Description

The invention relates to the field of computer technology and can be used in processor computer devices and automation devices.

Known methods and devices for counting pulses (see, for example, I.N. Bukreev, B.M. Mansurov and V.I. Goryachev. Microelectronic means of digital devices. 1973, Sov. Radio, p. 143, Fig. 5.7). The coding of information in the specified counter is performed in the code 8 4 2 1, each bit of the counter contains two RS-flip-flops and logic elements (LE) AND, NOT. The disadvantage of this counter is the presence of two RS-triggers (Tr) in the discharge and the sequential propagation of the transfer signal (SP), the maximum value of which, ceteris paribus, depends on the number of binary bits of the counter. Counters are known that contain one RS-flip-flop in each category and perform a wide list of EOs, for example, pulse counters made according to the patents RU 2284653 C2, RU 2284654 C2, but the speed of these counters also depends on the number of binary bits. The closest prototype of the proposed device is a counter made according to patent RU 2308801 C. The prototype contains one RS-flip-flop in each category and slightly reduces the maximum propagation time of the SP, but this is achieved due to the additional costs of equipment for constructing the transfer circuit.

по приходу счетного импульса (СИ) в триггер первого разряда заносят код „1", по следующему СИ сдвигают код принятой единицы в Tr второго разряда, а Tr 1 первого разряда устанавливается в „0". Аналогично выполняют сдвиг „1" на один разряд влево по C2-C4. При A4=1 значение триггера сохраняют до прихода СИ 10. По СИ 5 заносят „1" в Tr первого разряда согласно соотношению (1). Счетные импульсы СИ 6 и СИ 7 сдвигают код „1" в Tr третьего разряда, при A3=1 значение триггера сохраняют до прихода СИ 10. Десятым СИ устанавливают все Tr тетрады в „0" и вырабатывают СП в старшую тетраду. Это позволяет исключить время распространения СП в пределах тетрады, что повышает быстродействие выполнения счета импульсов. Также предложено устройство счета импульсов, отличающееся тем, что каждый двоичный разряд счетчика импульсов построен на основе одного RS-триггера, трех элементов И, двух элементов ИЛИ и трех элементов НЕ. Кроме того, каждая тетрада содержит схему формирования СП, выполненную на двух элементах И, схему управления приемом „1" в Tr первого разряда, выполненную на двух элементах И и одном элементе ИЛИ, вход общей установки триггеров тетрад в „0", вход СИ из младшей тетрады, выход СИ из i-й тетрады в старшую тетраду. Предложенное построение счетчика обеспечивает снижение затрат оборудования и повышает быстродействие счета импульсов.The aim of the invention is to increase the speed of the counter by eliminating the time delay during the formation of the joint venture when counting pulses in tetrads of the binary decimal counter and reducing hardware costs. For this, a pulse counting method is proposed, characterized in that the decoding of decimal digits from zero to nine is represented by the codes of four triggers 0000, 0001, 0010, 0100, 1000, 1001, 1010, 1100, 1101 and 1110, while in the case of $$\overline{A\mathrm{one}}\cdot \overline{\mathrm{<figure-callout\; id="2"\; label="A"\; filenames="00000011.png"\; state="\{\{state\}\}">A</figure-callout>}2}\cdot \overline{\mathrm{<figure-callout\; id="3"\; label="A"\; filenames="00000011.png"\; state="\{\{state\}\}">A</figure-callout>}3}=\mathrm{one..}...(\mathrm{one})$$

upon the arrival of the counting pulse (SI), the code “1” is entered into the trigger of the first discharge, the code of the received unit is shifted to Tr of the second discharge at the next SI, and Tr 1 of the first discharge is set to “0”. Similarly, shift “1” by one bit to the left along C2-C4. At A4 = 1, the trigger value is stored until the arrival of SI 10. According to SI 5, “1” is entered into Tr of the first discharge according to relation (1). The counting pulses of SI 6 and SI 7 shift the code “1” to Tr of the third category, with A3 = 1, the trigger value is stored until the arrival of SI 10. For tenth SI, set all Tr tetrads to “0” and generate a joint venture in the senior notebook. This makes it possible to exclude the propagation time of the SP within the tetrad, which increases the speed of pulse counting. A pulse counting device is also proposed, characterized in that each binary bit of the pulse counter is built on the basis of one RS-trigger, three AND elements, two OR elements, and three NOT elements. In addition, each tetrad contains a joint venture formation circuit executed on two AND elements, a reception control circuit “1” in Tr of the first discharge, executed on two AND elements and one OR element, the input of the general setting of the notebook triggers to “0”, the SI input from lower notebook, SI output from the i-th notebook to the senior notebook. The proposed construction of the counter provides a reduction in equipment costs and increases the speed of the pulse count.

To explain the operation of the proposed device, Fig. 1 shows a functional diagram of one tetrad of a pulse counter. The following notation is used in the diagram: elements AND 1-7, elements OR 8-10, elements NOT 11-13; RS-flip-flop (Tr) 14, input of the general setting “0” of triggers of tetrads 15, input of counting pulses from the lowest notebook 17, output of counting pulses to the senior notebook 16. Figure 2 shows the timing diagram of the operation of two counter notebooks.

. (Здесь $$\overline{A3}$$

, $$\overline{A2}$$

и $$\overline{A1}$$

- инверсные значения Tr 14.), второй СИ установит Tr 14 второго разряда в „1". Сигнал проходит по цепи элементов И 2, НЕ 13 и поступит на единичный вход Tr 14. При этом нулевое значение сигнала с выхода НЕ 13 запрещает работу И 3 второго разряда, чем обеспечивает задержку сигнала с И 3 на время длительности СИ 2. Одновременно сигнал с выхода И 2 через ИЛИ 9, И 1, НЕ 12 поступит на нулевой вход Tr 14 первого разряда и установит упомянутый триггер в „0". Таким образом код „1", хранящийся в Tr 14 первого разряда, будет сдвинут на один разряд влево, т.е. в тетраде будет храниться код 0010, что соответствует числу 2. Третий СИ сдвинет код „1" из второго разряда в третий разряд. Четвертый СИ сдвинет код „1" из третьего разряда в четвертый разряд. Код „1" в четвертом разряде будет сохраняться до конца счета первых десяти СИ в рассматриваемой тетраде. После окончания четвертого СИ снова будет выработан управляющий потенциал по условию (1). Пятый СИ занесет в Tr 14 первого разряда код „1", шестой СИ сдвинет код „1" в Tr 14 второго разряда, седьмой СИ сдвигает код „1" в Tr 14 третьего разряда. Код „1" в третьем разряде будет храниться до конца счета первых десяти СИ. После окончания седьмого СИ будет сформирован управляющий потенциал $$A4\cdot A3\cdot \overline{A2}\cdot \overline{A1}=1\dots \dots (2)$$

. Упомянутый потенциал будет сформирован на выходы И 5, 6, ИЛИ 10, который разрешит прохождение восьмого СИ по цепи элементов И 2, НЕ 13 на единичный вход Tr 14 первого разряда. Девятый СИ сдвинет код „1" из первого разряда во второй. После окончания девятого СИ в тетраде будет сформирован код 1110, что соответствует числу 9. Десятый СИ выработает СП в старшую тетраду счетчика, при этом $$СП=A4\cdot A3\cdot A2\cdot СИ10=1\dots \dots (3)$$

. Сигнал переноса в старшую тетраду вырабатывается на выход И 4 и по выходу 16 поступает в старшую тетраду на вход 17 и на вход ИЛИ 9 четвертого разряда рассматриваемой тетрады. Сигнал с выхода элемента ИЛИ 9 по цепи элементов И 1, НЕ 12 поступит на первый вход Tr 14 четвертого разряда и одновременно через элементы ИЛИ 9, И 1, НЕ 12 на нулевые входы Tr 14 триггеров третьего-первого разрядов. Таким образом устройство выполняет счет импульсов в двоично-десятичном коде, каждый разряд которого построен на основе одного RS-триггера, ЛЭ И, ИЛИ, НЕ, при этом исключена схема сквозного переноса в разрядах каждой тетрады, что позволяет повысить быстродействие работы и снизить аппаратурные затраты.The proposed device is as follows. In each binary bit of the counter, the outputs AND 1, 2 through HE 12, 13 are connected to the zero and single inputs Tr 14, the output AND 1 and the unit output Tr 14 through OR 8 are connected to the first input AND 3, the second input of which is connected to the output NOT 13 The output And 3 is connected to the first input to the first And 1 and to the input NOT 11 of the i-th category and to the third input And 2 i + 1-th category. The output of the PEN in the first category is connected to the first input AND 2, the second and third inputs of which are connected to the input 17 and to the output OR 10. The output OR 9 is connected to the first input AND 1. The first input OR 9 of the first or third bits is connected to the output AND 2 of the second or fourth category, the second inputs of OR 9 of the first to third category are interconnected and connected to the output of OR 9 and the input AND 1 of the fourth category. The first input OR 9 of the fourth category is connected to input 15, the second input of the said OR element is connected to output And4. In each notebook of discharges, the first and third inputs And 4 are connected to the input 17, with the output FROM the second discharge and the output And 5, respectively. The output And 4 is connected to the input of the joint venture in the senior notebook 16. The first and second inputs And 5 are connected to the outputs And 3 of the fourth and third digits. The first and second inputs And 6 are connected to the output And 5 and NOT 11 of the second category. The first and second inputs AND 7 are connected to the outputs NOT 11 of the third and second digits. The outputs And 6, 7 are connected to the input OR 10. The input SP 17 from the lower notebook is connected to the second inputs And 2 of the first or fourth digits. Consider the operation of the device during the pulse counting operation. Before the operation starts, the triggers 14 of all the notebooks are set to “0.” The zero pulse goes through the circuit: input 15, OR 9 of the fourth category, OR 9 of the first and third digits, AND 1, NOT 12 and the zero input Tr 14 of all notebooks. First counted the pulse received at input 17 sets Tr 14 in the first digit to "1" under the condition $$\overline{A\mathrm{one}}\cdot \overline{\mathrm{<figure-callout\; id="2"\; label="A"\; filenames="00000011.png"\; state="\{\{state\}\}">A</figure-callout>}2}\cdot \overline{\mathrm{<figure-callout\; id="3"\; label="A"\; filenames="00000011.png"\; state="\{\{state\}\}">A</figure-callout>}3}=\mathrm{one..}...(\mathrm{one})$$

. (Here $$\overline{A3}$$

, $$\overline{\mathrm{<figure-callout\; id="2"\; label="A"\; filenames="00000011.png"\; state="\{\{state\}\}">A</figure-callout>}2}$$

and $$\overline{A\mathrm{one}}$$

- inverse values of Tr 14.), the second SI will set Tr 14 of the second bit to “1." The signal passes through the circuit of elements AND 2, NOT 13 and goes to a single input Tr 14. In this case, the zero value of the signal from the output NOT 13 prohibits AND 3 of the second discharge, which ensures a delay of the signal from AND 3 for the duration of SI 2. At the same time, the signal from the output of AND 2 through OR 9, AND 1, NOT 12 will go to the zero input Tr 14 of the first discharge and set the mentioned trigger to “0”. Thus, the code “1” stored in Tr 14 of the first digit will be shifted one bit to the left, that is, the code 0010 will be stored in the notebook, which corresponds to number 2. The third SI will shift the code “1” from the second digit to the third digit . The fourth SI will shift the code “1” from the third category to the fourth category. The code “1” in the fourth category will be stored until the end of the first ten SI in the notebook. After the end of the fourth SI, the control potential will again be developed according to condition (1). The fifth SI will enter the code “1” in Tr 14 of the first digit, the sixth SI will shift the code “1” in Tr 14 of the second digit, the seventh SI will shift the code “1” in Tr 14 of the third digit. The code “1” in the third digit will be stored until the end accounts of the first ten SI. After the end of the seventh SI, the control potential will be formed $$A\mathrm{four}\cdot \mathrm{<figure-callout\; id="3"\; label="A"\; filenames="00000011.png"\; state="\{\{state\}\}">A</figure-callout>}3\cdot \overline{\mathrm{<figure-callout\; id="2"\; label="A"\; filenames="00000011.png"\; state="\{\{state\}\}">A</figure-callout>}2}\cdot \overline{A\mathrm{one}}=\mathrm{one}......(2)$$

. The mentioned potential will be formed at the outputs AND 5, 6, OR 10, which will allow the passage of the eighth SI through the circuit of elements AND 2, NOT 13 to a single input Tr 14 of the first category. The ninth SI will shift the code “1” from the first digit to the second. After the end of the ninth SI, the code 1110 will be generated in the notebook, which corresponds to the number 9. The tenth SI will generate a joint venture in the senior counter notebook, while $$\mathrm{FROM}P=A\mathrm{four}\cdot \mathrm{<figure-callout\; id="3"\; label="A"\; filenames="00000011.png"\; state="\{\{state\}\}">A</figure-callout>}3\cdot \mathrm{<figure-callout\; id="2"\; label="A"\; filenames="00000011.png"\; state="\{\{state\}\}">A</figure-callout>}2\cdot \mathrm{FROM}\mathrm{AND}10=\mathrm{one}......(3)$$

. The transfer signal to the senior notebook is generated at the output And 4 and output 16 is fed into the senior notebook to the input 17 and to the input OR 9 of the fourth category of the notebook under consideration. The signal from the output of the element OR 9 through the circuit of elements AND 1, NOT 12 will go to the first input Tr 14 of the fourth category and at the same time through the elements OR 9, AND 1, NOT 12 to the zero inputs Tr 14 of the triggers of the third and first digits. Thus, the device performs pulse counting in binary decimal code, each bit of which is built on the basis of one RS-flip-flop, LE AND, OR, NOT, while the scheme of end-to-end transfer in bits of each tetrad is excluded, which allows to increase the operating speed and reduce hardware costs .

Claims (2)

1. The method of counting pulses, characterized in that each decimal digit of one bit is represented by four binary digits, while decimal digits from zero to four are represented by binary codes 0000, 0001, 0010, 0100 and 1000, respectively, numbers from five to nine are represented by binary codes 1001, 1010, 1100, 1101 and 1110, respectively, the pulse counting from “0” to “9” is performed by adding “1” to the code of the number stored in the first or fourth triggers of notebook A1, A2, A3 and A4, while adding "1" to the code of the notebook is carried out by entering "1" A1 or shift of "1" by one bit towards the MSB first SI pulse counting 1 for zero values of A1, A2 and A3, i.e.,

, set A1 to "1", the second counter pulse SI 2 set A2 to "1" and A1 set to "0", the third counter pulse SI 3 set A3 to "1", and A2 to "0", the fourth counter pulse SI 4 set A4 to "1", and A3 to "0", while A4 is stored until the end of the count in the notebook under consideration, the fifth SI 5 at

take the code “1” in A1, the sixth counting pulse of SI 6 sets A2 to “1”, and A1 to the “0”, the seventh counting pulse of SI 7 set A3 to “1”, and A2 to “0", with the code A3 save until the end of the account in the notebook in question, provided

according to SI 8, it is possible to write the code “1” in A1, according to SI 9 they set A2 to “1” and A1 to “0”, according to the tenth SI 10, they form a signal to transfer the SP to the senior notebook, while SP = A4 · A3 · A2 · SI 10 = 1, and set all the triggers of the tetrad to "0", feeding the SP along the chain of the second elements OR, the first elements AND, the second elements NOT to the zero inputs of each RS trigger of the tetrad. 2. The pulse counting device, made on the logical elements of the LE AND, OR, NOT, containing in each binary bit one RS-trigger, the first-third elements AND, the first element OR, the first-third elements NOT, while the first element AND, through the second element is NOT connected to the zero input of the RS flip-flop, the second element And through the third element is NOT connected to the single input of the RS-flip-flop, the output of the first element And and the single output of the RS-flip-flop through the first element OR are connected to the first input of the third And element, the second input which is connected to the output third of the first element NOT, the output of the third AND element is connected to the first input of the first AND element and to the input of the first element NOT, the output of which is connected to the first input of the second AND element, characterized in that a second OR element is introduced into each binary bit of the notebook, the first input of which the first to third bits are connected to the output of the second AND element of the fourth and second category, respectively, the output of the said OR element is connected to the second input of the first AND element of the corresponding discharge, in addition, the output of the second OR element of the fourth row connected to the second inputs of the second elements OR third-first digits of the tetrad, the first and second inputs of the second OR element of the fourth digit are connected to the first input of the general installation of the triggers of the notebooks in "0" and to the output of the fourth element And, the outputs of the third elements And the first-third digits notebooks are connected to the third inputs of the second elements AND senior bits, respectively; the second inputs of the second And elements of the first and fourth bits of the tetrad are connected to the second input of the SI counting pulses from the younger notebook, the first, second and third inputs of the fourth And element, the output of which is a transfer signal to the senior notebook, are connected to the input of the counting pulses from the lower discharge, the output the third element AND of the second category and with the output of the fifth element And, accordingly, the inputs of the fifth element And are connected to the outputs of the third elements And of the fourth and third digits, the output of the fifth element And is connected to the first input m of the sixth element AND, the second input of which is connected to the output of the first element NOT of the second category, the inputs of the seventh element And are connected with the outputs of the first elements NOT of the second and third categories, the outputs of the sixth and seventh elements And through the third element OR are connected to the third input of the second element AND of the first discharge.

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