RU2780048C1 - Cycle synchronization method for signals with a cycle concentrated or distributed synchrogroup - Google Patents

Abstract

FIELD: communication technology.

SUBSTANCE: invention relates to the field of telecommunications. The search for a CA or the restoration of synchronism by cycles is performed by summing at each position of the cycle not the responses of the synchro signal recognizer, but summing all symbols similar to synchro group synchro symbols, using full synchro information about each synchro group synchro symbol, true and false. An increase in the accuracy of estimating the probability of an error of the POC synchro symbol is experimentally achieved by counting not the number of D distorted responses of the synchro signal recognizer during S cycles, but the number of D’ distorted synchro symbols of synchro groups during S’ cycles. Reducing the search time of the CA, if there was a failure of synchronism in cycles, and reducing the probability of false triggering of the decisive node after restoring the communication channel when the signal disappears or a relatively long exposure to powerful interference in the signal reception area is achieved by zeroing the memory block of the decisive node and the block of shift registers when any summation result is achieved at any of the N positions of the acceptable value cycle.

EFFECT: reduction in the search time of the cyclic sync signal of the CA and an increase in the accuracy of its detection.

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Description

The invention relates to telecommunications and can be used in receiving devices for synchronization in cycles of discrete message transmission systems.

In [1], based on the criterion for the maximum a posteriori probability, an analytical expression was obtained that describes the optimal algorithm for searching for the phase of the cyclic synchronization signal (CS) or the temporal position of the CS among the information symbols of a binary stream. In contrast to similar expressions obtained in [2] and [3], here we take into account the dependence of the required duration Q of the analysis interval of the received binary sequence when searching for a DS, measured in cyclic intervals (CI), on the parameters of the DS (M, N), the ratio a posteriori probabilities of alternative hypotheses (K) of correct and false detection of the CS, which determines the probability of correct detection of the CS, the probability of correct reception of the sync symbol (P _p ), as well as the probability of the appearance of a false sync symbol (P _l ) at the information position of the cycle.

The work [4] defines the minimum amount of analyzed data of the binary sequence Q _min CI for the optimal algorithm for searching for the CS, less than which a decision on the temporal position of the CS cannot be made. At the same time, the required amount of analyzed data (a segment of a binary sequence with a duration of Q CI) is determined, after which it is possible to make a decision about the temporal position of the DS - phase of the DS, with the required probability of correct detection of the DS, determined by the value of K. Thus, the optimal DS search algorithm obtained in [1] under the condition of choosing the duration of the analysis interval Q=f(K,M,N,P _p ,P _l ) CI, at the end of which a decision is made about the temporary position of the CS, and determined by the formula obtained in [4], can be abbreviated as

where the symbol ] [means rounding to the nearest whole number.

Here K=P(H ₁ /Q)/P(H ₂ /Q) is the ratio of a posteriori truth probabilities of the alternative hypotheses H ₁ and H ₂ , where the hypothesis H _i means that the analyzed i-th position of the cycle corresponds to the CS phase; n _i - the number of registered responses - binary symbols "1", the identifier of the clock signal at the i-th position of the cycle during the duration of Q cycle intervals of the analysis; N - the number of positions in the cycle or the duration of the cycle - the cyclic interval (NI), in binary symbols; M is the number of sync symbols in a sync group concentrated or distributed over a cycle, the regular repetition of which through N symbols is a CS; P _p - the probability of correct reception of the sync symbol (P _p =1-P _OS , P _OS - the probability of erroneous reception of a binary symbol or the probability of error of any symbol of the received binary signal - a sync symbol or an information symbol, in addition, it is assumed here that P _p >0, 5); R _l - the probability of a false sync symbol in a group of M information symbols analyzed by the sync signal identifier (in most cases, we can assume that R _l ≈0.5); a=(1-P ^M _l )/(1-P ^M _p ).

According to the optimal algorithm (1*) for searching for a DS obtained in [1] and [4], the received binary sequence containing the cyclic sync signal in the form of a concentrated or cyclically distributed sync group of M sync symbols, periodically repeated after N binary symbols, is fed to the input of the sync signal identifier (sync group decoder), at the output of which a binary sequence of symbols is analyzed, in which the symbol "1" is a response to a correctly received sync group or a false sync group of M information symbols of the binary sequence, the symbol "0" is a response to a distorted sync group or a false distorted sync group. At the same time, at each of the N positions of the cycle (corresponding to the response of the sync signal identifier), the symbols “1” are summed from cycle to cycle during the Q CI of the analysis, determined by the formula of the algorithm (1*). At the end of the Q DI analysis, the cycle position is determined, at which there are more responses than any other of the N-1 cycle positions, which is considered the synchronism position and which is the true synchronism position with a given probability of correct detection of the CS, determined by the value of K.

This DS phase search algorithm can be performed in various ways, implemented by the corresponding frame synchronization devices, differing from each other in the degree of compliance with the optimal DS search algorithm. For example, a variant of the circuit structure of a frame synchronization device that implements one of the methods for searching for the DS phase in accordance with the optimal DS search algorithm (1*) when operating under predictable communication conditions is given in [1], which can be stated as follows.

The method of framing, according to which a binary sequence containing a frame sync signal in the form of a sync group of M sync symbols concentrated or distributed over a cycle, periodically repeated after N binary symbols, is fed to the information input of the sync group decoder, from the output of which the response sequence is a binary sequence of symbols "1" and "0" are fed to the first inputs of N elements And, to the second inputs of which from the pulse distributor, the clock input of which is combined with the corresponding inputs of the sync group decoder and the cycle counter, the corresponding sequences of cyclic pulses delayed relative to each other by one clock interval are fed, at the same time, the sequences Q ₁ ,…,Q _N of single symbols “1” generated at the outputs of the elements AND are fed to the block N counters to count the number of single symbols “1” in each sequence, while at the end of counting Q cycles by the counter of cycles at its output, I form t pulse, with which the result of counting in binary code of each counter of the block of N counters is written to the decisive node, in which the number of the counter is selected in which the symbols "1" are accumulated more than in any other counter of the block of N counters and a control signal is generated for switch, which provides connection to its output of the corresponding sequence of cyclic pulses, which is a sequence of synchronism, after which the cycle counter and all counters of the block N counters are reset and the DS search procedure is repeated.

The disadvantages of this method of searching for a DS corresponding to the optimal algorithm (1*) for searching for a DS under predictable communication conditions are:

1. When searching for the temporal position of the DS, the responses of the sync group decoder, which is often called the sync signal identifier, are used as the primary source of synchronization information. In accordance with the optimal DS search algorithm, such responses at each cycle position (corresponding to cycle positions) are summarized from cycle to cycle for further selection of the synchronism position. However, such a sync group decoder reacts to a true or false sync group (it gives a response - the symbol "1" at its output) only when all M sync symbols of the sync group are received correctly or a false set of M information symbols similar to the sync symbols of the sync group occurs, and does not respond (at the output - symbol "0"), when at least one sync symbol of the true sync group is distorted (accepted by mistake) or when the collection of a false sync group from information symbols does not occur, i.e. the sync group decoder responds to the total sync information from all M correctly received sync symbols and does not take into account the sync information contained in each of the M sync symbols of the sync group. However, the incomplete use of the synchronization information contained in each synchronization symbol leads to an increase in the accumulation time of the required amount of synchronization information to make a decision on the choice of the synchronism position, and, accordingly, to an increase in the DS search time, especially under poor communication conditions. Therefore, in order to reduce the DS search time, it is advisable to accumulate from cycle to cycle at each position of the cycle not the number of responses of the sync group decoder to correctly received sync groups and false sync groups, but the number of symbols similar to the sync symbols of the sync group at each position of the cycle [5].

2. The disadvantage of this method is that it is designed to operate in a channel with constant parameters, when the duration of the analysis interval Q can be determined in advance, taking into account the predicted communication conditions. When operating in a channel with signal fading, this method of searching for a CS will lead to an increase in the probability of false detection of a CS under poor communication conditions and to an increase in the search time for a CS when communication conditions improve.

Of the known methods of framing, the closest in terms of the essence of the tasks to be solved in accordance with the optimal CS search algorithm (1*) and most of the matching essential features is the framing method for signals with a lumped or distributed sync group over a cycle when operating in a channel with variable parameters, in accordance with with which a binary sequence containing a cyclic sync signal in the form of a sync group concentrated or distributed over a cycle is fed to the information input of the sync signal identifier, the output signal of which from a single-bit output is simultaneously fed to the first input of the prohibition element connected in series with the counter of distorted sync symbols and the threshold selection unit, and to the input of the least significant digit of the first input of the adder, the output signal of which in a parallel n-bit binary code is fed to the signal input of the shift register block, the main and additional outputs of which are connected, respectively, to the second at the input of the adder and the signal input of the decisive node, the clock input of which is combined with the corresponding inputs of the sync signal identifier, the shift register block and the cyclic pulse shaper, while the shift register block includes n N-bit shift registers, in which the clock inputs and inputs are separately combined reset, which are respectively the clock input and reset input of the shift register block, and the input and output bits, as well as the outputs of the input bits of all n N-bit shift registers of the shift register block are, respectively, the signal input, output and additional output of the shift register block, and at upon arrival of each clock pulse at the clock input of the block of shift registers, the input bits of n N-bit shift registers of this block are rewritten from the output of the adder in a parallel n-bit binary code, the result of summing the symbols "1" at the corresponding one of the N positions of the cycle with the corresponding serial number i=1 ,2,…,N, in addition, a sequence of cyclic pulses from the output of the cyclic pulse shaper is simultaneously fed to the second input of the prohibition element and the input of the cycle counter, which is used to count S cyclic pulses, after which the pulse signal from its output is simultaneously fed to the control input of the threshold selection block and the reset input of the counter of distorted sync signals, with the help of which, for S cycles, the number D of single symbols "1" is counted from the output of the prohibition element corresponding to distorted sync groups, in the form of a binary number in parallel code, which is rewritten into the block from the output of the counter of distorted sync signals threshold selection, and the counters are reset to count the next number of distorted sync symbols during the next S cycles, while in the threshold selection block, based on the current estimate of the sync symbol error probability in the form of P _oc ≈D/S, the value of which is within the corresponding one of the Z intervals admissible values of R _os , for the corresponding threshold number G _z is stored in a parallel binary code with the corresponding serial number of the threshold number gradation z=1,2,…,Z, which is fed from the output of the threshold selection block to the control input of the decision node, the signal input of which is the first input of the subtraction block, combined with the first input of the first comparison block and the data input of the memory block, the output of which is combined with the second inputs of the subtraction block and the first comparison block, in which two numbers are compared at its inputs, if in the corresponding clock interval the number at the first input of the first comparison block exceeds number at its second input, then a pulse signal is generated at the output of the first comparison block, which is fed to the control input of the memory block, ensuring that it rewrites the largest number coming to its data input and the first inputs of the first comparison block and the subtraction block, from the output of which binary numbers following with the frequency of clock pulses and corresponding to ra the difference of numbers between the largest number from the output of the memory block and each number entering the first input of the subtraction block is fed to the first input of the second comparison block, in which the binary numbers corresponding to the difference of numbers are compared with the threshold number supplied to its second input, which is the control the input of the decisive node, while the logic level from the output of the second comparison unit is fed to the reset input of the comparison counter, the clock input of which is the clock input of the decisive node, and if at one of the N positions of the cycle the result of summing the symbols "1" exceeds the result of summing the symbols "1" at any other position of the cycle by at least a threshold number, then an enabling "zero" potential is applied to the reset input of the comparison counter, and using the comparison counter, N-1 clock pulses are counted, and at its output, which is the output of the decisive node, a pulse synchronization signal, which is applied to the reset inputs of the memory block, the shift register block and of the cyclic pulse shaper, resetting the memory block and shift registers, as well as confirming or correcting the phase of the output sequence of cyclic pulses of the cyclic pulse shaper [6].

The following disadvantages of this method should be noted: 1. The possibilities to reduce the DS search time or the time to acquire synchronism were not used due to the fact that when searching for the DS time position, the responses of the sync signal identifier are used as the primary source of synchronization information that is being processed, and not sync information from each sync symbol of each sync group [5].

When summing symbols similar to the sync symbols of the sync group, as recommended in [5], the optimal CS search algorithm (1*) requires clarification in terms of the duration Q of the analysis interval in cyclic intervals to achieve the required value of the ratio of a posteriori probabilities K=P(H ₁ /Q)/ P(H2/ _Q ). Taking into account the analytical expressions obtained in [4], the abbreviated optimal CS search algorithm in this case can be written as

where n' _i is the number of sync symbol-like symbols of the sync group at the i-th position of the cycle, each of which is registered as a sync symbol "1", during the duration of Q' analysis frame intervals, during which MQ' of sync symbols are transmitted; c=(1-P _l )/(1-P _p ).

When working in accordance with the algorithm (2*) with character-by-character processing of symbols similar to the synchro-symbols of the synchro-group, it is also necessary to bring the method of frame synchronization as close as possible to this algorithm into conformity.

2. Since, according to this method, all operations are carried out using the responses of the sync signal identifier, including estimating the probability of an error of the sync symbol Р _os , (which is required in accordance with the optimal search algorithm for the DS (1 *)), indirect experimental method - by counting the number of D distorted synchrogroups for S cycles (S is the total number of transmitted synchrogroups) and determining the probability (frequency) of an error of the synchrogroup P _osg =D/S. This method of estimating the value of Р _os ≈Р _osg is inaccurate, especially with an increase in the number M of sync symbols in the sync group, which leads to a corresponding error in choosing the duration of the analysis interval Q _z determined by the threshold number G _z ≈f(P _osg ), i.e. . Q _z ≈F(G _z )≈F[f(P _osg )] and disruption of work according to algorithm (1*).

However, when summing symbols similar to the sync symbols of the sync group and operating in accordance with the algorithm (2*), it becomes possible to more accurately determine P _OS =D'/MS', where D' is the number of distorted sync symbols with MS' of the transmitted sync symbols. In this case, the calculation of the duration Q' _z of the analysis interval should be performed using a different formula corresponding to the algorithm (2*), respectively, and the calculation of the threshold value G' _z =f(P _os ) takes a different value, which can be more accurately calculated to obtain the desired duration Q' _z =F(G' _z )=F[f(P _oc )] analysis interval.

3. Since the maximum sum of counting the responses of the sync signal identifier in a parallel binary code at each position of the cycle is limited by the capacity of n parallel cells with identical ordinal numbers of bits of the N-bit shift registers of the block of shift registers, overflows of individual n-bit numbers written to the parallel cells of the block are possible shift registers, which is equivalent to zeroing the results of counting responses in these cells. Such cases can occur, for example, when there is a signal loss or a relatively long exposure to powerful interference in the signal reception area. After the restoration of the communication channel, this can lead to an increase in the search time for the DS if there was a failure of synchronism in cycles and an increase in the probability of a false operation of the decisive node.

This disadvantage will also manifest itself when summing symbols similar to the synchro-symbols of the synchro-group when working according to the algorithm (2*).

The tasks to be solved by the present invention - a method of framing when receiving signals with a concentrated or distributed sync group over the cycle, are:

1. Reducing the search time for the DS or the recovery time of synchronism by cycles by summing at each position of the cycle not the responses of the sync signal identifier, but the summation of all symbols similar to the sync symbols of the sync group, using the full sync information about each sync symbol of the sync group, true and false. At the same time, the search for the temporary position of the CS should be carried out in a manner corresponding to the optimal algorithm (2*), in accordance with which a reduction in the search time for the CS in relation to the algorithm (1*) will be achieved without worsening the probability of false detection of the CS.

2. Increasing the accuracy of estimating the probability of error of the sync symbol P _os experimentally by counting not the number D of distorted responses of the sync signal identifier during S cycles, but the number D' of distorted sync symbols of sync groups during S' cycles. As a result, it is possible to more accurately estimate the probability of a sync symbol error by the formula Р _os =D'/MS', as required by the optimal CS search algorithm (1*) or (2*), and, accordingly, choose threshold numbers based on a more accurate calculation analysis interval for operation in a channel with variable communication parameters with the required noise immunity and elimination of false DS detections in the time intervals between adjacent synchronism failures in cycles.

3. Reduction of the DS search time if there was a failure of synchronism in cycles, and a decrease in the probability of a false operation of the decisive node after the restoration of the communication channel in the event of a signal loss or relatively long exposure to powerful interference in the signal reception area by resetting the memory block of the decisive node and the block of shift registers upon reaching any summation result at any of the N positions of the cycle of a valid value.

The solution of the tasks is achieved by the fact that in the known method of framing for signals with a lumped or sync group distributed over a cycle, according to which a binary sequence containing a cyclic sync signal in the form of a sync group concentrated or distributed over a cycle is fed to the information input of the sync signal identifier, the output signal which is fed from a single-bit output with a serial number r=1 to the input of the least significant bit with a serial number r=1 of the first input of the adder, the output signal of which in a parallel n-bit binary code is fed to the signal input of the shift register block, the main and additional outputs of which are connected respectively to the second input of the adder and the signal input of the decisive node, the clock input of which is combined with the corresponding inputs of the clock signal identifier, the shift register block and the cyclic pulse shaper, while the shift register block includes n N-bit shift registers ha, in which the clock inputs and reset inputs are separately combined, which are respectively the clock input and the reset input of the shift register block, and the input and output bits, as well as the outputs of the input bits of all n N-bit shift registers of the shift register block are, respectively, the signal input, output and additional output of the block of shift registers, and when each clock pulse arrives at the clock input of the block of shift registers, the input bits of n N-bit shift registers of this block are overwritten from the output of the adder in a parallel n-bit binary code, the result of summing the symbols "1" on corresponding to one of the N positions of the cycle with the corresponding serial number i=1, 2, ..., N, in addition, the results of the summation of symbols at each of the N positions of the cycle from the additional output of the shift register block are fed sequentially in time with the frequency of the clock pulses to the signal input decision node, the signal input of which is the first input of the subtraction unit, combined with the first input of the first comparison unit and the data input of the memory unit, the output of which is combined with the second inputs of the subtraction unit and the first comparison unit, in which two numbers are compared at its inputs, if in the corresponding clock interval the number is the first input of the first comparison block exceeds the number at its second input, then a pulse signal is generated at the output of the first comparison block, which is fed to the control input of the memory block, ensuring that it rewrites the largest number coming to its data input and the first inputs of the first comparison block and the block subtraction, from the output of which binary numbers following with the frequency of clock pulses and the corresponding difference of numbers between the largest number from the output of the memory block and each number entering the first input of the subtraction block are fed to the first input of the second comparison block, in which the binary numbers corresponding to the difference numbers are compared with a threshold number, the to its second input, which is the control input of the decisive node, from the output of the threshold selection block, while the logic level from the output of the second comparison block is fed to the reset input of the comparison counter, the clock input of which is the clock input of the decisive node, while, if on one of N positions of the cycle, the result of the summation of the symbols "1" will exceed the result of the summation of the symbols "1" at any other position of the cycle by at least a threshold number, then an enabling "zero" potential is applied to the reset input of the comparison counter, and using the comparison counter, count N- 1 clock pulses and at its output, which is the output of the decisive node, a synchronization pulse signal is generated, which is fed to the reset input of the cyclic pulse shaper block, confirming or correcting the phase of the output sequence of cyclic pulses from the output of the cyclic pulse shaper, which is fed to the input of the cycle counter and to the first entry of the prohibition element with the sequence number m=1, complement R-1 single-bit outputs of the sync signal identifier with serial numbers r=2, 3…, R, and M-1 prohibition elements with serial numbers m=2, 3,…, M, where R is the minimum required number of single-digit outputs or the number digits of the R-bit output of the sync signal identifier, which is selected from the condition R=]log ₂ M[, where][ is rounding to the nearest largest integer, M is the number of sync symbols in the binary signal sync group concentrated or distributed over the cycle at the information input of the sync signal identifier, consecutive in time with conditional serial numbers m=1, 2, ..., M, and the cycle duration or repetition period of synchrogroups among information symbols equal to Tc=N binary symbols, moreover, additional bit outputs of the sync signal identifier with serial numbers r=2, 3, ..., R are connected to the corresponding bit inputs with the same serial numbers r=2, 3, ..., R of the first input of the adder, the first inputs M-1 of the prohibition elements from to serial numbers m=2, 3, ..., M are combined and connected additionally to the first input of the prohibition element with serial number m=1, and the second inputs of M prohibition elements with serial numbers m=1, 2, ..., M are connected to the corresponding additional outputs sync signal identifier with the same serial numbers m=1, 2, ..., M, in addition, an adder of distorted sync symbols of the sync group, an accumulating adder, a second memory block, a first delay element, a second delay element, an overflow decoder and an OR element are additionally introduced.

In the cycle synchronism mode, each cyclic pulse from the output of the cyclic pulse shaper must coincide in time with the corresponding M sync symbols of each converted sync group, arriving simultaneously with M additional outputs of the sync signal identifier with serial numbers m = 1,2, ..., M, while if there are no distorted sync symbols of sync groups in the input binary signal, then during the action of each cyclic pulse at the first inputs of the M prohibition elements, the second inputs of these prohibition elements are simultaneously fed M sync symbols "1" from the corresponding M additional outputs of the sync signal identifier, and from the outputs of the M prohibition elements the corresponding one-bit inputs of the adder of distorted sync symbols of the sync group are supplied with M symbols "0", which means that there are no errors in the sync symbols of the sync group, respectively, at the output of this adder a "zero" number is formed in the binary code, in the opposite case, when all M sync symbols are in the input binary signal to each sync group is distorted, then during the action of each cyclic pulse at the first inputs of the M prohibition elements, the second inputs of these prohibition elements are simultaneously supplied with M sync symbols "0" from the corresponding M additional outputs of the sync signal identifier, and from the outputs of the M prohibition elements, they are fed to the corresponding single-bit inputs of the adder of distorted sync symbols of the sync group, the sync symbols "1", which means that all the sync symbols of the sync group are distorted, respectively, at the output of this adder, the result of summing the symbols "1" at its inputs is, in this case, in the form of the number M in a parallel binary code, which is fed synchronously with the corresponding cyclic pulse of the cyclic pulse shaper to the signal input of the accumulating adder, with the help of which the distorted sync symbols of sync groups are summed from cycle to cycle during S' cycles counted by the cycle counter, after which a pulse is formed at its output, which is fed to and the control input of the second memory block, providing rewriting and storing a new result of counting D' of distorted sync symbols from the output of the accumulating adder connected to the data input of the second memory block, in addition, a pulse from the output of the cycle counter is fed through the first delay element to the reset input of the accumulating adder, zeroing its contents, and the counting of the distorted sync symbols of the sync groups by the accumulating adder, the synchronization input of which is fed with cyclic pulses from the output of the cyclic pulse shaper through the second delay element, is repeated for the next S' cycles, while the current result of counting the distorted sync symbols in the second memory block is recorded in the second memory block. during each S' cycles, is fed to the signal input of the threshold selection block, in which, according to the measured value of the estimate of the probability of error of the sync symbol P _os =D'/MS', the value of which is within the corresponding one of the Z intervals of permissible values of the value of P _os , form the corresponding threshold number G' _z in a parallel binary code with the corresponding serial number of the threshold number gradation z=1,2,…,Z, which is fed from the output of the threshold selection block to the control input of the decision node in which, in order to avoid overflow of any bits of the N-bit registers shift registers with identical serial numbers of the block of shift registers, an overflow decoder is additionally connected to the output of the first memory block, at the output of which, when the critical binary number A=B-M is written to the first memory block, where B is the maximum possible n-bit binary number, a drop is formed voltage, which is applied to the input of the OR element, the other input of which is supplied with a synchronization pulse signal from the output of the comparison counter, while the output of the OR element is connected to the reset input of the first memory block, which is an additional output of the decisive node, and to the reset input of the shift register block, providing zeroing the first block of memory and the block of shift registers upon receipt of any signal to the corresponding input of the OR element.

In the sync signal identifier for receiving a binary signal with a concentrated sync group of M sync symbols with conditional serial numbers m=1,2, ..., M and a cycle time or a sync group repetition period equal to Tc=N binary symbols, an M-bit shift register is used, in which the number bits M with serial numbers m=1,2,…,M, corresponding to the sequence of bits from the senior (output) bit - at m=1, to the junior (input) bit - at m=M, which is the information input of the sync signal identifier, the clock input of which is the clock input of the M-bit shift register, the outputs of the bits with serial numbers m=1,2, ..., M are connected to the corresponding inputs of the sync group converter, the outputs of which with serial numbers m = 1, 2, ..., M, which are additional outputs of the sync signal identifier with the same serial numbers m = 1, 2, ..., M, are additionally connected to the corresponding single-bit inputs of the adder of symbols of similar sync symbols of the sync group, the output of which is an R-bit digital output of the sync signal identifier, consisting of R single-bit outputs with serial numbers r=1, 2, ..., R.

соответствующих порядку следования разрядов от старшего (выходного) разряда - при m=1, к младшему (входному) разряду - при m=L, который является информационным входом опознавателя синхросигнала, тактовым входом которого является тактовый вход L-разрядного регистра сдвига, выходы М разрядов которого с порядковыми номерами

при М=3 или

(М-1)K+1 при М>3 подключают к соответствующим входам преобразователя синхрогруппы, выходы которого с порядковыми номерами m=1,2,…,М, являющиеся дополнительными выходами опознавателя синхросигнала с такими же порядковыми номерами m=1, 2, …, М, дополнительно подключают к соответствующим одноразрядным входам сумматора символов подобных синхросимволам синхрогруппы, выход которого является R-разрядным цифровым выходом опознавателя синхросигнала, состоящего из R одноразрядных выходов с порядковыми номерами r=1, 2, …, R.In the sync signal identifier for receiving a binary signal with a sync group of M sync symbols uniformly distributed over the cycle with conditional serial numbers m=1, 2, ..., M and a cycle duration or a repetition period of the sync group T _c =N=MT _s of binary symbols, where T _c = The K-period of the synchronization symbols among the information symbols is equal to K binary symbols, using an L-bit shift register, in which the number of L=K(M-1)+1 bits with serial numbers

corresponding to the sequence of bits from the senior (output) bit - at m=1, to the junior (input) bit - at m=L, which is the information input of the sync signal identifier, the clock input of which is the clock input of the L-bit shift register, the outputs of M bits which with serial numbers

at M=3 or

(M-1)K+1 at M>3 is connected to the corresponding inputs of the sync group converter, the outputs of which with serial numbers m=1,2,…,M, which are additional outputs of the sync signal identifier with the same serial numbers m=1, 2, ..., M, is additionally connected to the corresponding single-bit inputs of the adder of symbols similar to the synchro-symbols of the synchro-group, the output of which is the R-bit digital output of the synchro-signal identifier, consisting of R single-bit outputs with serial numbers r=1, 2, ..., R.

A comparative analysis with the prototype shows that the introduction of significant distinctive features is novelty and allows, as will be shown below, to solve the tasks.

Let us consider the effectiveness of the proposed invention on the example of the operation of a frame synchronization device, the electrical structural diagram of which is shown in Fig. 1 with a sync signal identifier in the composition for receiving a binary signal with a lumped sync group at M=3, T _c =N=15. In FIG. 2 d shows an electrical structural diagram of the sync signal identifier for receiving a binary signal with a sync group distributed over the cycle at M=3, T _c =N=MT _c =15, T _c =K=5. In FIG. 2a,b,c shows the timing diagrams of the input signals of the device: a) - clock pulses; b) - a signal with a lumped synchrogroup; c) - a signal with a synchrogroup evenly distributed over the cycle.

The frame synchronization device for a signal with a lumped sync group contains a sync signal identifier 1, an adder 2, a shift register block 3, a decision node 4, a cyclic pulse generator 5, a counter 6 cycles, M=3 elements 7 ₁ ,7 ₂ ,7 ₃ prohibition with a serial number m=1,2,3 and a threshold selection block 8, wherein the information and clock inputs of the device are, respectively, the information and clock inputs of the identifier 1 of the clock signal, R=2 bit outputs of which with serial numbers of the bit outputs r=1,2, constituting the R-bit output connected to the corresponding bit inputs with the same serial numbers of the bit inputs of the first input of the adder 2, the output of which is connected to the signal input of the shift register unit 3, the main and additional outputs of which are connected, respectively, to the second input of the adder 2 and the signal input of the decisive node 4, clock the input of which is combined with the corresponding inputs of the identifier 1 of the clock signal, block 3 of the registers with engine, and shaper 5 cyclic pulses.

Here R=2 is the minimum required number of single-bit outputs or the number of bits of the R-bit output of the identifier 1 of the clock signal, the number of bits of which is selected from the condition R=]log ₂ M[, where][ is rounding up to the nearest largest integer, M=3 - the number of sync symbols in a lumped or cyclically distributed sync group of a binary signal at the information input of the device, following one after another in time with conditional serial numbers m=1,2,3 and a cycle duration or repetition period of sync groups among information symbols equal to Tc=N binary symbols and equal to the number N=15 bits of each shift register block 3 shift registers.

The output of the shaper 5 cyclic pulses, which is the output of the device, is combined with the input of the counter 6 cycles and the first inputs M=3 elements 7 ₁ ,7 ₂ ,7 ₃ inhibition with serial numbers m=1, 2, 3, the second inputs of which are connected to the corresponding additional the outputs of the identifier of the clock signal with the same serial numbers m=1, 2, 3, while the reset input of the shaper 5 of the cyclic pulses is connected to the output of the decisive node 4, the control input of which is connected to the output of the threshold selection block 8.

The decisive node 4 consists of the first comparison unit 9, the first memory unit 10, the subtraction unit 11, the second comparison unit 12 and the comparison counter 13, and the output of the first comparison unit 9 is connected to the control input of the first memory unit 10, the output of which is combined with the input of the decoder 19 overflow and the first inputs of the first block 9 of comparison and the first block 11 of subtraction, the output of which is connected to the first input of the second block 12 of comparison, the output of which is connected to the reset input of the counter 13 of the comparison, the output of which, which is the output of the decisive node 4, is additionally connected to the first input OR element 20, the second input of which is connected to the output of the overflow decoder 19, and the output of the OR element 20, which is an additional output of the decisive node 4, is combined with the reset inputs of the first memory block 10 and the shift register block 3, with the signal, control and clock inputs of the decisive node 4 are respectively the data input of the first memory block 10 combined with the second inputs of the first block 9 comparison, and block 11 subtraction, the second input of the second block 12 comparison and the clock input of the counter 13 comparison.

In addition, the device contains an adder 14 of distorted sync symbols of the sync group, accumulating adder 15, the second memory block 16, the first delay element 17 and the second delay element 18, while the outputs M=3 elements 7 ₁ ,7 ₂ ,7 ₃ prohibition with serial numbers m =1,2,3 are connected to the corresponding single-bit inputs of the adder 14 distorted synchro-symbols of the synchrogroup, the output of which is connected to the signal input of the accumulating adder 15, the reset input and the synchronization input of which are connected respectively to the output of the counter 6 cycles through the first delay element 17 and additionally to the output of the shaper cyclic 5 pulses through the second delay element 18, and the output of the accumulating adder 15 is connected to the data input of the second memory block 16, the output and control input of which are connected respectively to the signal input of the threshold selection block 8 and additionally to the output of the counter 6 cycles.

Identifier 1 sync signal for receiving a binary signal with a lumped sync group of M=3 sync symbols with conditional serial numbers m=1, 2, 3 and a cycle time or a repetition period of the sync group equal to Tc=N=15 binary symbols, contains an M-bit shift register 21, in which the number of digits M=3 with serial numbers m=1,2,3, corresponding to the sequence of digits from the senior (output) bit - at m=1, to the junior (input) bit - at m=3, which is an information input identifier 1 of the clock signal, the clock input of which is the clock input of the M-bit shift register, the outputs of the bits of which with serial numbers m=1, 2, 3 are connected to the corresponding inputs of the converter 22 of the clock group, the outputs of which are with serial numbers m=1, 2, 3, which are additional outputs of the identifier 1 of the clock signal with the same serial numbers m=1, 2, 3, are additionally connected to the corresponding single-bit inputs of the adder 23 characters similar to the sync symbols of the sync group, the output of which is an R-bit digital output of the identifier 1 of the sync signal, consisting of R=2 single-bit outputs with serial numbers r=1, 2.

соответствующих порядку следования разрядов от старшего (выходного) разряда - при m=1, к младшему (входному) разряду - при m=11, который является информационным входом опознавателя 1-1 синхросигнала, тактовым входом которого является тактовый вход L-разрядного регистра сдвига, выходы М=3 разрядов которого с порядковыми номерами

подключены к соответствующим входам преобразователя синхрогруппы, выходы которого с порядковыми номерами m=1, 2, 3, являющиеся дополнительными выходами опознавателя 1-1 синхросигнала с такими же порядковым номерами m=1, 2, 3, дополнительно подключены к соответствующим одноразрядным входам сумматора 23 символов подобных синхросимволам синхрогруппы, выход которого является R-разрядным цифровым выходом опознавателя синхросигнала, состоящего из R=2 одноразрядных выходов с порядковыми номерами r=1, 2.Identifier 1-1 of the sync signal for receiving a binary signal with a sync group evenly distributed over the cycle of M=3 sync symbols with conditional serial numbers m=1, 2, 3 and a cycle duration or a repetition period of the sync group T _c =N=MT _with =15 binary symbols, where T _c =K - the repetition period of the sync symbols among the information symbols is equal to K=5 binary symbols, contains an L-bit shift register 21-1, in which the number of L=K(M-1)+1=11 bits with serial numbers

corresponding to the order of bits from the senior (output) bit - at m=1, to the junior (input) bit - at m=11, which is the information input of the identifier 1-1 of the clock signal, the clock input of which is the clock input of the L-bit shift register, outputs M=3 digits of which with serial numbers

connected to the corresponding inputs of the sync group converter, the outputs of which with serial numbers m=1, 2, 3, which are additional outputs of the identifier 1-1 of the clock signal with the same serial numbers m=1, 2, 3, are additionally connected to the corresponding single-bit inputs of the adder 23 characters similar to the sync symbols of the sync group, the output of which is an R-bit digital output of the sync signal identifier, consisting of R=2 single-bit outputs with serial numbers r=1, 2.

The frame synchronization device works as follows.

If the input binary signal contains a cyclic sync signal in the form of a lumped sync group of M=3 sync symbols, periodically repeated among information symbols with a repetition period T _c =N=15 binary symbols (Fig. 2b), then the sync signal identifier must be used as part of the frame synchronization device, which is included in the device shown in Fig. 1. Here, with the identifier 1 of the sync signal, it contains an M-bit shift register 21, in which the number of bits M=3 with serial numbers m=1,2,3 corresponding to the order of the bits from the senior (output) bit - at m=1 to the least significant (input) bit - at m=3, the input of which is the information input of the identifier 1 of the clock signal and the device as a whole,

Under the influence of clock pulses (Fig. 2a) the input sequence of binary symbols (Fig. 2b) moves along the bits of the M-bit shift register 21. In this case, the concentrated sync group of M=3 sync symbols is a combination of sync symbols of the form "011". In clock intervals coinciding in time with the cyclic pulses from the output of the shaper 5 cyclic pulses, this sync group of each cycle is located in the corresponding bits of the M-bit shift register 21 with serial numbers m=1, 2, 3, the outputs of which are connected to the corresponding inputs of the converter 22 of the sync group , which converts a known combination of M=3 sync symbols "011" into a combination of M=3 "single" sync symbols "111" using the appropriate logic elements of the sync group converter 22: one logical element with the function of negation - NOT and two logical elements each with the function repetition or double negation - NOT-NOT [7].

One-bit outputs of the converter 22 synchrogroups, which are additional outputs of the identifier 1 of the synchrosignal with serial numbers m=1, 2, 3, additionally connected to the corresponding single-bit inputs of the adder 23 symbols similar to the synchrosymbols of the synchrogroup. The adder 23 counts the symbols "1" at its inputs and outputs the summation result to the digital output of the identifier 1 of the clock signal in binary code. To represent the maximum decimal number M=3 binary code requires R=2 digits or two single-bit outputs of the identifier 1 of the clock signal, selected from the ratio R=]log ₂ M[, where][ is rounded to the nearest largest integer. The adder 23 is a parallel combination adder [7], the output of which is an R-bit digital output of the identifier 1 of the clock signal, consisting of R=2 single-bit outputs with serial numbers r=1, 2.

соответствующих порядку следования разрядов от старшего (выходного) разряда - при

к младшему (входному) разряду - при

=11, вход которого является информационным входом опознавателя 1 синхросигнала и устройства в целом.If the received binary signal contains a sync group distributed over the cycle, periodically repeated among the information symbols (Fig. 2c), then as part of the device shown in Fig. 1, another version of the clock identifier 1-1 (Fig. 2d) should be used, containing an L-bit shift register 21-1, in which the number of L=K(M-1)+1=11 bits with serial numbers

corresponding to the sequence of digits from the senior (output) digit - when

to the least significant (input) digit - when

=11, the input of which is the information input of the identifier 1 of the clock signal and the device as a whole.

=1,K+1,2К+1=1, 6, 11, выходы которых подключены к входам соответствующих логических элементам, составляющих преобразователь 22 синхрогруппы, который обеспечивает преобразование известной комбинации из М=3 синхросимволов «011» в комбинацию «единичных» синхросимволов «111» с помощью соответствующих М=3 логических элементов преобразователя 22 синхрогруппы: одного логического элемента с функцией отрицания - НЕ и двух логических элементов каждый с функцией повторения или двойного отрицания - НЕ-НЕ.Under the influence of the clock pulses (Fig. 2a) the sequence of binary symbols moves through the bits of the L-bit shift register 21-1. In this case, the sync group distributed over the cycle also consists of M=3 sync symbols and is a combination of sync symbols of the form "011" with conditional serial numbers m=1, 2, 3. pulses, this sync group of each cycle is located in the corresponding bits of the L-bit shift register 21-1 with serial numbers

=1,K+1,2K+1=1, 6, 11, the outputs of which are connected to the inputs of the corresponding logic elements that make up the sync group converter 22, which converts a known combination of M=3 sync symbols "011" into a combination of "single" sync symbols "111" using the corresponding M=3 logical elements of the converter 22 of the synchrogroup: one logical element with the function of negation - NOT and two logical elements each with the function of repetition or double negation - NOT-NOT.

One-bit outputs of the converter 22 of the synchrogroup, which are additional outputs of the identifier 1-1 of the synchro signal with the corresponding serial numbers m=1, 2, 3, are additionally connected to the corresponding one-bit inputs of the adder 23 of symbols similar to the synchrosymbols of the synchrogroup. The adder 23 counts the symbols "1" at its inputs and is a combination adder of parallel action [7], the output of which is an R-bit digital output of the identifier 1 of the clock signal, consisting of R=2 single-digit outputs with serial numbers r=1, 2.

Thus, the operation of the identifiers 1 and 1-1 of the clock signals is similar and consists in counting symbols similar to the clock symbols of a concentrated or distributed sync group.

In any projected or existing communication system, only one type of frame synchronization signal selected during design can be used, therefore, in the frame synchronization device (Fig. 1), either the identifier 1 of the clock signal or the identifier 1-1 of the clock signal must be used. With this in mind, any version of the identifier 1 or 1-1 of the clock signal, built according to those shown in Fig. 1 and FIG. 2g structures for the corresponding signal - with a concentrated or distributed cycle synchrogroup with any identical parameters M, R, T _c =N=MT _s , is compatible with all interacting functional elements as part of the cycle synchronization device shown in FIG. one.

The results of the summation of symbols similar to the sync symbols of the sync group from the digital output of the identifier 1 or 1-1 of the sync signal are fed to the first input of the adder 2. To the second input of the adder 2 from the output of the shift register block 3, binary n-bit binary numbers in a parallel code are fed with a clock frequency.

The adder 2 is a parallel combinational adder [7], in which two lower bit inputs (R=2) of the first term and n bit inputs of the second term are respectively the first and second inputs of the adder 2, while the other n-2 bit inputs of the first input are connected to the source of the "zero" level.

Block 3 shift registers includes n N-bit shift registers, which are separately combined clock inputs and reset inputs. In this case, the combined clock inputs and the combined reset inputs of the shift registers in the shift register block 3 are, respectively, the clock input and the reset input of the shift register block 3, and the inputs of the first bits, the outputs of the last bits and the outputs of the first bits of all n shift registers are, respectively, the signal input, output and additional output block 3 shift registers.

Thus, the result of counting symbols similar to the sync symbols of the sync group at the output of the identifier 1 or 1-1 of the sync signal, which takes place in the i-th clock interval, is added in the adder 2 with the result of the previous count of symbols similar to the sync symbols at the i-th position of the cycle, coming from the output of the block 3 shift registers, and the new result of counting such symbols, greater by M≤3 of the previous one, is written as an n-bit binary number in the first cells (bits) of the shift registers of the block 3 of the shift registers.

In this case, the binary number previously written in the first cells of the shift register block 3, as well as all other numbers stored in subsequent cells of the same type, are shifted in parallel by one bit, and the following result is already received from the output of the shift register block 3 to the second input of the adder 2 character counts - at the (i+1)-th position of the cycle, which is overwritten in the first cells of the shift register block 3, and the remaining numbers stored in the same type cells of the shift register block 3 are shifted by one bit, etc. those. the shift register block 3 provides for storing the results of counting symbols similar to sync symbols at each position of the cycle during the duration of the cycle. In this case, the value of n determines the capacity of the memory of the results of the calculation.

At the same time, the results of counting symbols similar to sync symbols at each of the positions of the cycle from the additional output of the shift register block 3 are sequentially fed to the signal input of the decisive node 4. In the decisive node 4, for example, in the i-th clock interval, a binary number in a parallel code, representing the current the result of counting symbols similar to sync symbols at the i-th position of the cycle is simultaneously fed to the corresponding inputs of the first comparison block 9, the first memory block 10 and the first subtraction block 11. In the first comparison block 9, the input number is compared with the binary number stored in the first memory block 10 and, if it exceeds the number of the first memory block 10, then a pulse is generated at the output of the first comparison block 9, which, when fed to the control input of the first memory block 10, provides erasing the old and writing a new (input) number. After that, the inputs of the first block 9 comparison are equal binary numbers. If the input number is equal to or less than the number stored in the first memory block 10, then the contents of the latter are not changed.

Thus, in the first block 10 of memory overwrites the largest current result of counting symbols like sync symbols at any position of the cycle, which is then compared with the results of counting at subsequent positions of the cycle. The resulting difference (between the number of the first memory block 10 and the input number) at the output of the subtraction block 11 in the form of a binary number in a parallel code is compared in the second comparison block 12 with the threshold number G' _z coming to its second input (which is the controlled input of the decision node 4 ) from the output of block 8 for selecting the threshold. In this case, if the number from the output of the subtraction unit 11 is less than the threshold number G' _z , then from the output of the second comparison unit 12, a "single" (inhibiting) potential is supplied to the reset input of the comparison counter 13, which sets and holds it in the "zero" state. In the opposite case, when in the i-th clock interval, the number from the output of the subtraction unit 11 is equal to or greater than the number G' _z , then the "zero" (allowing) potential comes from the output of the second comparison unit 12, and the comparison counter 13 counts one clock pulse , arriving at its clock input, which is the clock input of the decisive node 4. In this case, if the largest binary number written to the first memory block 10 in any j-th clock interval and corresponding to the result of accumulation at the j-th position of the cycle, will be exceed by an amount equal to or greater than the threshold number G' _z each of the N-1 subsequent numbers coming one after another from the additional output of the shift register block 3, then the comparison counter 13 will count the next N-1 clock pulses in a row, after which at its output a pulse synchronization signal is generated. This signal is applied to the reset input of the shaper 5 cyclic pulses and to the first input of the OR element 20, the output of which is an additional output of the decision node 4 and is combined with the reset inputs of the first memory block 10 and the shift register block 3. As a result of the action of the pulse synchronization signal, the first memory block 10 and the shift register block 3 are reset, and the phasing of the shaper 5 of the cyclic pulses is performed. Further, the process of searching for the cyclic timing signal is repeated, and if there was no failure of synchronism in cycles, then the synchronization signal from the output of the decisive node 4 will confirm the cyclic phase of the output signal. Since the number n of shift registers in the shift register block 3 is limited, it is possible to overflow the bit memory cells of the shift register block 3 when summing symbols similar to sync symbols. As a result, the operation algorithm of the device may be disturbed and the probability of false operation of the decisive node 4 increases. To exclude such situations, an overflow decoder 19 is connected to the output of the first memory block 10, which, when writing to the first memory block 10 of the critical binary number A=B-M, where B - the maximum possible n-bit binary number, generates a voltage drop, which is supplied to the second input of the OR element 20, resetting the first memory block 10 and block 3 of the shift registers.

The process of generating threshold numbers by block 8 for choosing a threshold for the decisive node 3 is as follows.

The second inputs of the elements 7 ₁ ,7 ₂ ,7 ₃ prohibition receive binary elements with M=3 outputs with serial numbers m=1, 2, 3 of the converter 22 of the synchrogroup, which are the corresponding outputs of the identifier 1 or 1-1 of the clock signal, and the first inputs these prohibition elements - a sequence of pulses from the output of the shaper 5 cyclic pulses. As a result, only that symbol from the corresponding output of the converter 22 of the synchrogroup will pass to the output of each prohibition element, and with inversion, which coincides in time with the “single” pulse (single symbol “1”) of the shaper 5 of the cyclic pulses. Thus, if, for example, in the bits of the shift register 21 of the identifier 1 of the clock signal, M = 3 correctly received sync symbols of the sync group and at the time of advancement of the first character "0" of the sync group "011" (Fig. 2b) into the bit of the shift register 21 with a serial number m =1 simultaneously receive a "single" pulse shaper 5 cyclic pulses, then at the output of each of the M=3 elements 7 ₁ ,7 ₂ ,7 ₃ prohibition symbol "0" will appear (there are no errors in the synchrogroup). If all M symbols of the sync group are distorted, i.e. in the bits of the shift register 21 is the sync group “100”, the sync group “000” will appear at the corresponding outputs of the converter 22 of the sync group, then the symbol “1” will appear at the output of each of the M prohibition elements (three errors in the sync group). In the general case, with each arrival of a cyclic pulse at the outputs of M prohibition elements, from 0 to M=3 "single" symbols (sync symbol errors) can be recorded, depending on the probability of error of the binary symbol of the received signal. Moreover, in the intervals between cyclic pulses, each with a duration of N-1=14 symbols "0", at the outputs of elements 7 ₁ , 7 ₂ , 7 _{3 of} the prohibition, N-1=14 symbols "0" will be periodically recorded.

Similar operations are performed in the shift register 21-1 and the converter 22 of the sync group of the 1-1 sync signal identifier (Fig. 2d).

The outputs of the elements 7 ₁ , 7 ₂ , 7 ₃ are connected to the corresponding one-bit inputs of the adder 14 distorted sync symbols of the sync group, which counts the distorted sync symbols (symbols "1" at the inputs of the adder) in binary code. The adder 14 is a combination adder of parallel action [7]. The output of the adder 14 of the distorted sync symbols of the sync group is connected to the signal input of the accumulating adder 15, which counts the total number of distorted sync symbols of different sync groups. By counting the number D' of distorted sync symbols during the counting time of a rather large number of cyclic pulses S', it is possible to periodically determine the probability (frequency) of erroneous sync symbol reception with a certain degree of accuracy according to the formula P _{os =} D'/MS', i.e. make a current assessment of the degree of distortion of the received signal. When this counter 6 cycles counts the total number S' cyclic pulses, during which the transmitted MS' synchronization symbols. The counting coefficient (capacity) of the counter 8 cycles is chosen equal to the value S', therefore, after counting each S' cyclic pulses, a single pulse is formed at its output, after which it is reset to "zero". With the help of this pulse, the result of counting D' of distorted sync symbols by the accumulating adder 15 is written to the second memory block 16, instead of the previous binary number stored in it, recorded after the end of the count of the previous S' cyclic pulses. With some delay, determined by the first delay element 17, the accumulating adder 15 is reset to "zero" and the process of analyzing the quality of the received signal during the next S cyclic pulses is repeated.

The signal input of the accumulating adder 15 digital data is received synchronously with the pulses of the shaper 5 cyclic pulses. Therefore, in order to provide the accumulating adder 15 with a reliable sequential summation of numbers in a binary code, pulses from the output of the shaper 5 of cyclic pulses with a certain delay [7] determined by the second delay element 18 must be fed to its synchronization input.

The threshold selection block 8, depending on the value of the binary number D' recorded in the second memory block 16, selects a certain binary threshold number G' _z depending on the communication conditions, which is fed from its output in a parallel code to the control input of the decisive node 4.

Thus, during the counting time of each S' cycles, a certain threshold number G' _z is supplied to the decisive node 4, which in each particular case can take one of z=1, 2, ..., Z discrete values (gradations) depending on the quality the received signal, determined by the value of the error of the sync symbol R _OS. The required number of gradations Z of the threshold number G' _z is selected from the calculation of maintaining the probability of a false operation of the decisive node 4 (false detection of the cyclic phase of the signal during the average time interval between two adjacent failures of synchronism in cycles) with various changes in the value of Р _os In this case, the law of formation of specific values threshold numbers G' _z block 8 threshold selection can be symbolically written

where F is a pre-selected rule for block 8 selection of the threshold, according to which the value of R OS _≈D '/MS', taking values within the z-th measurement interval, is in accordance with a well-defined value of the threshold number G'_z;

A _z and B _z - respectively, the lower and upper limits of the value of R _OS for the z-th interval.

Accordingly, the required noise immunity of the device, which is determined by the probability of a false alarm, is provided by the choice of the law of formation of threshold numbers G' _z for the threshold selection block 8 according to the corresponding measured values of the value P _os falling within any z-th interval with boundaries A _z and B _z , according to the principle: the greater the value of P _os , the greater should be the threshold number G' _z .

The value of S', which determines the counting factor of the counter of 6 cycles, must be chosen, on the one hand, large enough to ensure the required accuracy of estimating the error probability P _os of the clock signal, on the other hand, small enough to ensure the measurement of the value of P _os within between two failures of synchronism on cycles and tracking changes in communication conditions. If we assume that failures of synchronism in cycles occur at time intervals that are much longer than the counting time S' of cyclic pulses (which takes place in practice), then the value of S' can be chosen in the following form [6]

where B ₁ - the upper limit of the value of R _OS within the first measurement interval, which corresponds to the smallest threshold number G'_z;

][ - means rounding to the nearest whole number.

To determine the effectiveness of the proposed method for searching for the time position of the frame clock signal (CS) or the cyclic phase of the signal, it is necessary to find out which is better in terms of reducing the search time for the CS:

- either use the responses of the sync signal identifier (OS) as the primary source of sync information, which, like in many other framing devices, performs the function of a sync group (GS) decoder from M sync symbols [3] and accumulate them in accordance with the algorithm of the devices based on on the previously obtained optimal algorithm for searching for the temporary position of the CS (1*);

- either use the sync information contained directly in the received binary sequence and, at the same time, sum not the responses of the DS from each position of the cycle, but the sync symbols of the sync groups (true or false) coming to the OS input, according to the algorithm (2*).

This operation can be performed using the OS, the block diagram of which is shown in Fig. 1 (OS 1) or in FIG. 2d (OS 1-1), each of which will be called the adder of symbols similar to the sync symbols of the sync group (SS). At the same time, synchronization information is taken from the output of the SS at each analyzed position of the cycle not in the form of binary symbols "1" and "0" (responses), as from a single-bit output of the DS (OS), but in the form of summation results of symbols similar to the synchro-symbols of the synchro-group.

To solve the problem, it is necessary to determine the amount of information received both from each DS response and directly from the sync symbols of the sync group and then compare the accumulation time of the same amount of sync information with these two methods of accumulating DS responses and symbols of similar sync symbols of the sync group, as done in [5].

содержащейся в системе Y относительно системы X, состоящую из источника информации X при приеме М символов, можно определить сначала количество информации, содержащейся в каждом приятом символе

и, воспользовавшись свойством аддитивности информации [10], определить величину

. По общему определению количества информации [8] имеемTo solve the problem, it is necessary to determine the amount of information received at the input of the DS during the decoding of M sync symbols and the amount of information obtained at the same time at its output. Consider three systems, which we will conventionally denote as X, Y, and Z. Let the X system be a symbol transmission source, and the Y and Z systems be a demodulator and a DS demodulator, respectively. In this case, we will monitor system X through systems Y and Z separately. To determine the amount of information

contained in the system Y relative to the system X, consisting of the source of information X when receiving M symbols, you can first determine the amount of information contained in each received symbol

and, using the information additivity property [10], determine the value

. According to the general definition of the amount of information [8], we have

и r_j - безусловные вероятности того, что системы X и Y принимают состояния x_i и y_j соответственно; Р (y_j/x_i) условная вероятность того, что система Y будет находиться в состоянии y_j, если система X приняла состояние x_i. Предположим, что система X приняла вполне определенное состояние x₁, например, передан первый символ синхрогруппы - «1». Тогда в формуле (1) индекс суммирования i принимает только одно значение i=1, соответственно безусловная вероятность передачи синхросимвола i₁=1.where

and r _j - unconditional probabilities that systems X and Y take states x _i and y _j respectively; P (y _j /x _i ) conditional probability that system Y will be in state y _j if system X has taken state x _i . Suppose that the system X has taken a well-defined state x ₁ , for example, the first symbol of the sync group is transmitted - "1". Then in formula (1) the summation index i takes only one value i=1, respectively, the unconditional probability of transmitting the sync symbol i ₁ =1.

System Y can take two values - y ₁ (the symbol "1" is accepted) and y ₀ (the symbol "0" is accepted), while r ₁ =r ₀ =0.5, and the possible values of the conditional probabilities in formula (1) will look like

Taking into account (2), formula (1) is transformed to the form

If the subsequent transmitted symbol should take on the opposite value - "0" in accordance with the structure of the clock signal, then it is easy to show that the amount of information received by the Y system will also be determined by expression (3), i.e. the amount of information contained in each received sync symbol is independent of what particular value each sync symbol in the sync group takes on.

Taking into account (3), the total amount of information received by system Y when receiving a sync group will be equal to

Using formula (1), we now determine the amount of information

содержащейся в системе Z, о состоянии системы X:

contained in system Z, about the state of system X:

In this case, we also assume that the system X has received a well-defined state x' ₁ (a sequence of M symbols has been transmitted), while i=1, and the unconditional probability δ _i =1. System Z can also take two states - z ₁ (“single” DS response) and z ₀ (“zero” DS response), and the unconditional probabilities of system Z being in these states will be equal to

Possible values of conditional probabilities in formula (5) can be written as

Taking into account (6) and (7), expression (5) will have the form

where P _p =1-P _osh .

определяемых формулами (4) и (8)To determine the gain G ^(M) by the amount of synchronization information received by the system Y in relation to the system Z when receiving M symbols at any value of the value P _p >0.5, it is enough to find the ratio of the values

defined by formulas (4) and (8)

(в двоичных единицах) и G^(M) (в разах) по формулам (4), (8) и (9) соответственно при различных Р_п и при M₁=3 и М₂=4.For example, the table shows the results of calculating the values

(in binary units) and G ^(M) (in times) according to formulas (4), (8) and (9), respectively, for different P _p and for M ₁ =3 and M ₂ =4.

т.е. при хороших условиях связи системы Y и Z эквиваленты в части получаемых сведений о переданном синхросигнале. Однако с уменьшением Р_п в системе Z происходит более быстрое «разрушение» синхроинформации, чем в системе Y, т.е. при использовании в качестве первичного источника синхроинформации откликов ДС для обнаружения временного положения ЦС, теряется определенное количество информации, имеющейся на приемной стороне (в системе Y). Причем эти потери тем значительнее, чем хуже условия связи и чем больше синхросимволов М в синхрогруппе.From the analysis of the data in the table, it follows that when

those. under good communication conditions, the Y and Z systems are equivalent in terms of received information about the transmitted clock signal. However, with a decrease in P _p in the Z system, a faster "destruction" of synchronization information occurs than in the Y system, i.e. when using DS responses as the primary source of synchronization information to detect the temporal position of the DS, a certain amount of information available on the receiving side (in the Y system) is lost. Moreover, these losses are the more significant, the worse the communication conditions and the more sync symbols M in the sync group.

The optimal DS search algorithm (1*) assumes summation of DS responses from the same cycle positions, i.e. in fact, the synchronization information contained in the DS responses is summed up from cycle to cycle. Using the property of additivity of information [8], one can pose the question: how many cycles or cycle intervals (CI) Q _z it is necessary to analyze the DS at the same position of the cycle in order to obtain the required amount of information, for example, equal to the value R (in binary units) . Obviously, the value of Q _z will be equal to

If the summation of synchronization information from cycle to cycle is performed in the Y system, i.e. from each sync symbol of the sync group, i.e. in accordance with the algorithm (2*), then to obtain the same amount of information about the X system under the same communication conditions, the number of analysis CIs will be equal to

If the gain in time of accumulation of a given amount of synchronization information in system Y in relation to system Z or the gain in time of searching for a DS (with the considered methods of summing synchronization information) is presented as a ratio of Q _z /Q _Y , then the value of this gain will completely correspond to the expression (9)

Thus, in order to determine the time gain in the search for the DS at a specific value of P _p > 0.5 in the case when the source of synchronization information is not the responses of the DS, but symbols similar to the sync symbols of the sync group, it is sufficient to determine the values of the quantities

In conclusion, it should be noted that the implementation of the proposed invention - the method of framing for signals with a lumped or distributed cycle sync group, when compared with the implementation of the known method - the prototype, in which the responses of the identifier (decoder) of the sync signal are used as the primary source of synchronization information, allows achieve the following advantages when working in a channel with variable parameters:

1. Reducing the search time for the DS or the recovery time of synchronism by cycles by summing at each position of the cycle not the responses of the sync signal identifier, but the summation of all symbols similar to the sync symbols of the sync group, using the full sync information about each sync symbol of the sync group, true and false [5]. In this case, the search for the temporal position of the DS is performed in a manner corresponding to the optimal algorithm (2*), in accordance with which a reduction in the search time for the DS in relation to the algorithm (1*) is achieved, without worsening the probability of false detection of the DS.

2. Increasing the accuracy of estimating the error probability of the sync symbol P _oc experimentally by counting not the number D of distorted responses of the sync signal identifier during S cycles, but the number D' of distorted sync symbols of sync groups during S' cycles. As a result, it is possible to more accurately estimate the error probability experimentally sync symbol according to the formula Р _os =D'/MS', as required for the optimal DS search algorithm (1*) or (2*), and, accordingly, select threshold numbers based on a more accurate calculation of the analysis interval for operation in a channel with variable communication parameters with the provision of the required noise immunity and the elimination of false detections of the DS in the time intervals between adjacent failures of synchronism in cycles.

3. Reduction of the DS search time if there was a failure of synchronism in cycles, and a decrease in the probability of a false operation of the decisive node after the restoration of the communication channel due to signal loss or relatively long exposure to powerful interference in the signal reception area by resetting the memory block of the decisive node and the block shift registers when any summation result is reached at any of the N positions of the allowed value cycle.

Literature

1. Shadrin B. G. Optimization of the search algorithm for a cyclic sync signal Communications technology. Ser. TRS, 1983, no. 10(31), p. 120-125.

2. Kislyuk L.D. Optimization of inertial frame synchronization devices - Issues of radio electronics. Ser. TRS, 1972, no. 3 s. 35-42.

3. Koltunov M.N., Konovalov G.V., Langurov Z.I. Synchronization by cycles in digital communication systems. - M.: Communication, 1980. - 152.

4. Shadrin B. G. On the required amount of analyzed data with an optimal algorithm for searching for the phase of a cyclic clock signal - Technique of communication facilities. Ser. TRS, 1984, no. 10, p. 47-49.

5. Shadrin B.G. Comparative analysis of two methods of accumulating synchro-information with the optimal algorithm for searching for a synchro-signal - Communication equipment. Ser. TRS, 1984, no. 10, p. 43-46.

6. Description of the invention to the author's certificate of the USSR No. 1172052 H04L 7/08 - Device for synchronization in cycles, Publ. 08/07/1985, Bull. №29/ Shadrin B.G.

7. Soloviev G.N. Computer arithmetic units. - M.: Energy, 1978. - 176 p.

8.. Wetzel E.S. Probability Theory. - M.: Nauka, 1969. - 576 p.

Claims (3)

1. The method of framing for signals with a lumped or cycle-distributed sync group, according to which a binary sequence containing a cyclic sync signal in the form of a lumped or cycle-distributed sync group is fed to the information input of the sync signal identifier, the output signal of which is from a single-bit output with a serial number r=1 is fed to the input of the least significant bit with the serial number r=1 of the first input of the adder, the output signal of which in a parallel n-bit binary code is fed to the signal input of the shift register unit, the main and additional outputs of which are connected, respectively, to the second input of the adder and the signal input decision node, the clock input of which is combined with the corresponding inputs of the sync signal identifier, the block of shift registers and the shaper of cyclic pulses, while the block of shift registers includes n N-bit shift registers, in which clock inputs and inputs are separately combined reset, which are respectively the clock input and reset input of the shift register block, and the input and output bits, as well as the outputs of the input bits of all n N-bit shift registers of the shift register block are, respectively, the signal input, output and additional output of the shift register block, and at upon arrival of each clock pulse at the clock input of the block of shift registers, the input bits of n N-bit shift registers of this block are rewritten from the output of the adder in a parallel n-bit binary code, the result of summing the symbols "1" at the corresponding one of the N positions of the cycle with the corresponding serial number i = 1, 2, ..., N, in addition, the results of the summation of symbols at each of the N positions of the cycle from the additional output of the block of shift registers are fed sequentially in time with the frequency of the clock pulses to the signal input of the decisive node, the signal input of which is the first input of the block subtraction combined with the first input the house of the first comparison block and the data input of the memory block, the output of which is combined with the second inputs of the subtraction block and the first comparison block, in which two numbers are compared at its inputs, while if in the corresponding clock interval the number at the first input of the first comparison block exceeds the number at its second input, then a pulse signal is generated at the output of the first comparison block, which is fed to the control input of the memory block, ensuring that it rewrites the largest number coming to its data input and the first inputs of the first comparison block and the subtraction block, from the output of which binary numbers , following with the frequency of clock pulses and corresponding to the difference in numbers between the largest number from the output of the memory block and each number entering the first input of the subtraction block, is fed to the first input of the second comparison block, in which the binary numbers corresponding to the difference in numbers are compared with a threshold number, coming to its second input, which is the control input m of the decisive node, from the output of the threshold selection block, while the logic level from the output of the second comparison block is fed to the reset input of the comparison counter, the clock input of which is the clock input of the decisive node, while if at one of the N positions of the cycle the result of summing the symbols "1 "exceeds the result of summing the symbols "1" at any other position of the cycle by at least a threshold number, then an enabling "zero" potential is applied to the reset input of the comparison counter, and using the comparison counter, N-1 clock pulses are counted at its output, which is the output of the decisive node, a synchronization pulse signal is generated, which is fed to the reset input of the cyclic pulse shaper block, confirming or correcting the phase of the output sequence of cyclic pulses from the output of the cyclic pulse shaper, which is fed to the input of the cycle counter and to the first input of the prohibition element with a serial number m = 1, characterized in that R-1 single-digit outputs of the sync signal identifier with serial numbers r = 2, 3, ..., R and M-1 of prohibition elements with serial numbers m = 2, 3, ..., M, where R is the minimum required number of single-bit outputs or the number of bits of the R-bit output of the identifier sync signal, which is selected from the condition R = ]log ₂ M[, where ][ is rounding up to the nearest largest integer, M is the number of sync symbols in a concentrated or cyclically distributed sync group of a binary signal at the information input of the sync signal identifier, following one after another in time with conditional serial numbers m = 1, 2, ..., M, and the cycle duration or the repetition period of synchrogroups among information symbols equal to Tc = N binary symbols, moreover, additional bit outputs of the sync signal identifier with serial numbers r = 2, 3, ..., R are connected to the corresponding bit inputs with the same serial numbers r = 2, 3, ..., R of the first input of the adder, the first inputs M-1 of prohibition elements with serial numbers m = 2, 3, ..., M are combined and connected additionally to the first input of the prohibition element with a serial number m = 1, and the second inputs of M prohibition elements with serial numbers m = 1, 2, ..., M are connected to the corresponding additional outputs of the identifier sync signal with the same serial numbers m = 1, 2, ..., M, in addition, an adder of distorted sync symbols of the sync group is additionally introduced, accumulating the adder, the second memory block, the first delay element, the second delay element, the overflow decoder and the OR element, while in in the synchronism mode by cycles, each cyclic pulse from the output of the cyclic pulse shaper must coincide in time with the corresponding M sync symbols of each converted sync group, arriving simultaneously with M additional outputs of the sync signal identifier with serial numbers m = 1,2, ..., M, while, if in input binary signal has no distorted synchrosymbols of synchrogroups, then during the action of each cyclic pulse on the first M sync symbols “1” are simultaneously fed from the corresponding M additional outputs of the sync signal identifier to the second inputs of the M prohibition elements to the second inputs of these prohibition elements, and M symbols “0” are supplied from the outputs of the M prohibition elements to the corresponding single-bit inputs of the adder of the distorted sync symbols of the sync group, which means that there are no errors in the sync symbols of the sync group, respectively, at the output of this adder, a “zero” number is formed in the binary code, in the opposite case, when in the input binary signal all M sync symbols of each sync group are distorted, then during the action of each cyclic pulse at the first inputs of the M prohibition elements on the second inputs of these prohibition elements simultaneously supply M sync symbols "0" from the corresponding M additional outputs of the sync signal identifier, and from the outputs of the M prohibition elements, sync symbols "1" are fed to the corresponding single-bit inputs of the adder of distorted sync symbols sync groups The groups are distorted, respectively, at the output of this adder, the result of summing the symbols "1" at its inputs is represented, in this case, in the form of the number M in a parallel binary code, which is fed synchronously with the corresponding cyclic pulse of the cyclic pulse shaper to the signal input of the accumulating adder, using of which the distorted sync symbols of the sync groups are summed from cycle to cycle for S' cycles counted by the cycle counter, after which a pulse is generated at its output, which is fed to the control input of the second memory block, providing rewriting and storing a new result of counting D' of distorted sync symbols with the output of the accumulating adder connected to the data input of the second memory block, in addition, a pulse from the output of the cycle counter is fed through the first delay element to the reset input of the accumulating adder, zeroing its contents, and the count of distorted sync symbols of the sync groups by the accumulating adder, to the input of the synchronizing and which cyclic pulses are fed from the output of the cyclic pulse shaper through the second delay element, are repeated for the next S' cycles, while the current result of counting distorted sync symbols recorded in the second memory block during each S' cycles is fed to the signal input of the threshold selection unit, in which, according to the measured value of the estimate of the error probability of the sync symbol Р _os = D'/MS', the value of which is within the corresponding one of the Z intervals of permissible values of the value of Р _os , form the corresponding threshold number G _z in a parallel binary code with the corresponding ordinal number of threshold number gradation z = 1, 2, ..., Z, which is fed from the output of the threshold selection block to the control input of the decision node, in which, in order to avoid overflow of any bits of N-bit shift registers with identical serial numbers of the block of shift registers to the output of the first memory block, additionally connect an overflow decoder, at the output of which when writing to the first memory block of the critical binary number A = B-M, where B is the maximum possible n-bit binary number, a voltage drop is formed, which is fed to the input of the OR element, to the other input of which a synchronization pulse signal is supplied from the output of the comparison counter, in this case, the output of the OR element is connected to the reset input of the first memory block, which is an additional output of the decision node, and the reset input of the shift register block, ensuring that the first memory block and the shift register block are reset to zero when any signal is received at the corresponding input of the OR element. 2. The method according to claim 1, characterized in that in the sync signal identifier for receiving a binary signal with a lumped sync group of M sync symbols with conditional serial numbers m = 1, 2, ..., M and a cycle duration or a sync group repetition period equal to Tc = N binary characters, use an M-bit shift register, in which the number of bits M with serial numbers m = 1, 2, ..., M, corresponding to the order of bits from the high (output) bit at m = 1 to the low (input) bit at m = M, which is the information input of the sync signal identifier, the clock input of which is the clock input of the M-bit shift register, the bit outputs of which with serial numbers m = 1, 2, ..., M are connected to the corresponding inputs of the sync group converter, the outputs of which with serial numbers m = 1, 2, ..., M, which are additional outputs of the sync signal identifier with the same serial numbers m = 1, 2, ..., M, are additionally connected to the corresponding one-bit inputs of the adder of symbols similar to the synchro-symbols of the synchro-group, the output of which is the R-bit digital output of the sync signal identifier, consisting of R one-bit outputs with serial numbers r = 1, 2, ..., R. 3. The method according to claim 1, characterized in that in the sync signal identifier for receiving a binary signal with a sync group of M sync symbols uniformly distributed over the cycle with conditional serial numbers m = 1, 2, ..., M and a cycle duration or a repetition period of the sync group T _c = N = MT _with binary symbols, where T _with = K - the repetition period of synchronization symbols among information symbols, equal to K binary symbols, use an L-bit shift register, in which the number of L = K(M-1)+1 bits with serial numbers

corresponding to the sequence of digits from the most significant (output) digit at m = 1 to the least significant (input) digit at m = L, which is the information input of the sync signal identifier, the clock input of which is the clock input of the L-bit shift register, the outputs of M bits of which are with ordinal numbers

at M = 3 or

(M-1)K+1 at M>3 is connected to the corresponding inputs of the sync group converter, the outputs of which with serial numbers m = 1, 2, ..., M, which are additional outputs of the sync signal identifier with the same serial numbers m = 1, 2, ..., M, is additionally connected to the corresponding single-bit inputs of the adder of symbols similar to the synchro-symbols of the synchro-group, the output of which is the R-bit digital output of the synchro-signal identifier, consisting of R single-bit outputs with serial numbers r = 1, 2, ..., R.

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