RU2743233C1 - Method of transmitting and receiving discrete messages in complex of decametric radio communication - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to radio communication and can be used in departmental communication systems of decametre range for generation, transmission and reception of radiograms (RG), with required probabilistic characteristics of correct and false detection of RG. In the method of transmitting and receiving discrete messages in a complex of decametre radio communication during generation of the symbols, the symbols of the service address sequence (SAS) are uniformly distributed among the symbols of the service phasing and encoded information sequences. Ratio of symbols of three categories carrying different information is characterized by value X - number of service or information symbols through which one symbol of service address sequence follows. In a distributed sequence for correct detection thereof with a required probability, it is allowed to receive several symbols distorted in binomial distribution among correctly received remaining symbols of the address sequence.

EFFECT: technical result is high noise immunity of reception, high probability of correct detection.

1 cl, 1 dwg

Description

The invention relates to radio communication and can be used in departmental communication systems of the decameter range, using signals with angular keying and intended for the formation, transmission and reception of address discrete messages, limited in duration - radiograms (RG), with the required probabilistic characteristics of correct and false detection of RG ...

There is a method of transmitting and receiving discrete messages in a decameter radio communication complex with multichannel (parallel) transmission of binary sequences, according to which, in the transmitting set, a binary message from a message source is encoded in an encoder with an error-correcting code and fed to an N-channel modulator, from the output of which a multifrequency signal are emitted into the air using a radio transmitting device (RPDU) and a transmitting antenna, and in the receiving set, the signal is received using a receiving antenna and a radio receiving device (RPU), from the output of which the filtered and converted signal is fed to the input of the N-channel demodulator, after which the demodulated signal decoded in a decoder and presented to the message receiver [1].

In this method, the data stream after encoding at a rate V (bit / s) is distributed in the N-channel modulator into N parallel subchannels at a rate V / N (bit / s) in each subchannel with the formation of the corresponding N keyed subcarriers of the baseband signal emitted from using the RPDU and the transmitting antenna on the air. In this case, the duration of the transmitted binary signal T in each subchannel becomes N times longer than the original one.

However, this method of transmitting and receiving discrete messages in a decameter radio communication complex has the following disadvantages:

The transmitted multifrequency signal is characterized by a large peak factor, which does not allow the use of a multi-frequency signal with the maximum radiation power due to the need to limit the level of the multifrequency signal at the input of the multi-frequency signal in order to avoid nonlinear distortions in the output signal [2], [3].

In relation to the single-channel method of decameter radio communication with single-channel (sequential) data transmission, in which the peak factor of the emitted single-frequency signal is commensurate with unity, the use of the above method, in contrast to the single-channel method, does not allow achieving the required communication range with the use of a medium or low power transmission device, which in some cases it is unacceptable when transmitting short messages, for example, for transmitting object control commands over the required distances.

There is a method of transmitting and receiving discrete messages in a decameter radio communication complex with a test pulse and prediction (SIIP) with a single-channel (sequential) transmission of discrete messages [2], according to which the original binary message in the transmitting set is encoded with a noise-immune code in the encoder and fed to a single-channel a modulator, from the output of which the modulated signal is fed to the RPDU and emitted into the air using the transmitting antenna, and in the receiving set the signal is received using the receiving antenna and the RPU, from the output of which the filtered and converted signal is fed to the input of a single-channel demodulator, after which the demodulated signal is decoded in the decoder and receive the original message. When transmitting test pulses and a data stream with a rate of V (bit / s), one carrier frequency is manipulated in a single-channel modulator.

When these signals are received in a single-channel demodulator, the reverse operation of recovering the transmitted signals is performed.

However, this method of transmitting and receiving discrete messages in a decameter radio communication complex has the following disadvantages:

1. This method requires the implementation of a complex algorithm for the formation of transmitted signals and processing of received signals, which allows to overcome the consequences of intersymbol interference with an increase in the data transmission rate. However, this leads to a decrease in the reception immunity due to a decrease in the energy of the transmitted signal element with a duration of T [3] and a deterioration in the characteristics of the electromagnetic compatibility of the transmitting and receiving technical means of the radio communication complex due to the expansion of the spectrum of the transmitted signal due to the transmission of additional test pulses.

2. Expansion of the spectrum of the transmitted signal requires a corresponding increase in the bandwidth when receiving this signal, which further reduces the noise immunity of reception due to an increase in the likelihood of falling into a wider reception band of spectral components of station or sighting radio interference.

3. The implementation of this method when transmitting short messages is not effective due to the impossibility of the required assessment of the response of the radio channel when transmitting test pulses.

Of the known methods of transmitting and receiving discrete messages in decameter radio communication complexes, the closest in essence to the problems being solved and most of the coinciding essential features is the method of transmitting and receiving discrete messages in a decameter radio communication complex with single-channel (sequential) transmission of discrete messages, according to which in the transmitting set using an encoder, which can be a personal computer (PC), the original message from an electronic medium or a PC typed from the keyboard is programmed with a noise-immune code, the necessary binary information is added to it and fed to a single-channel modulator, from the output of which the modulated signal are emitted into the air with the help of the RPDU and the transmitting antenna, and in the receiving set, the signal reflected from the ionosphere is received using the receiving antenna and the radio receiver, from the output of which the filtered and converted signal is fed to the input single-channel th demodulator, after which the demodulated signal using a decoding device, which can also be used by a PC, is decoded by software and the original message is obtained on the PC display screen, either on an electronic medium or in a printed form [4], p. 107.

According to this method of transmitting and receiving discrete messages, the data stream from the output of the encoder at a rate of V (bit / s) manipulates one carrier frequency in a single-channel modulator. Depending on the multiplicity of the seal k [3], p. 573, the modulator can generate angle-shift keying signals, such as, for example, single-shot relative phase telegraphy (RPT) signals or frequency telegraphy (FT) signals with a transmission rate V = 1 / T (bit / s) at k = 1 and at a selected the duration of the signal element T, signals of double TFT (DOFT) or double frequency telegraphy (DFC) with a doubled transmission rate V = 2 / T (bit / s) at k = 2, etc.

When these signals are received in a single-channel demodulator, the reverse operation of recovering the binary sequence is performed.

A PC can be used here as a coding device, which can simultaneously be a source of messages by typing the original transmitted text of the message from the PC keyboard or by entering the initial information from an electronic medium. When addressing the transmission of a dialed message in the form of a RG, it is encoded with the selected error-correcting code in the PC programmatically, after which, to the coded binary information sequence (IP), consisting of Z information symbols (encoded message), the following service symbols are added by software or otherwise. sequences [5]:

1) service sequence of points (SPT) - a meander, consisting of K binary symbols, transmitted at the beginning of the RG to enter the synchronism of the clock synchronization receiver;

2) service phasing sequence (SPF) phasing code combination of binary symbols, consisting of Q symbols, which allows you to unambiguously determine the position of information symbols;

3) service address sequence (SAS) - an address code combination of binary symbols, consisting of R symbols and containing information about the address of the radio subscriber to whom the radio message is sent.

In some cases, when forming a digital selective calling (DSC) signal, other service information is also transmitted [5].

The modulating binary sequence of the address RG formed in this way through the serial interface module as part of the PC, for example, via the C1-TG telegraph interface from the PC output with the selected transmission rate - no more than 600 (bit / s) to exclude intersymbol interference when transmitting over a decameter radio channel [ 1], is fed to the input of the modulator, for example, to form the most noise-immune OFT signal [3], which is further amplified in power in the RPDU and radiated into the air using a transmitting antenna.

A PC can also be used here as a decoder and a message recipient, where the reverse operation is performed - restoring the original text of the message with the decoded original message displayed on the PC monitor or electronic medium, provided that the decoder finds its address in the WG service sequence at the output of the demodulator.

The disadvantages of this method of transmitting and receiving discrete messages in a decameter radio communication complex include the following:

1. When using OFT signals for message transmission, erroneously received symbols are doubled at the demodulator output, which reduces the noise immunity of reception by half (in terms of error probability) in relation to the reception of signals of ideal phase telegraphy (FT) - in the absence of negative factors - "reverse operation »With a spontaneous change in the phase of the carrier vibration [3]. Double errors equally affect both the main text of the RG - IP, encoded in the encoder, and the service information - SFP and SAP, on the probability of correct reception of which the value of the probability of non-reception (skipping) of the RG as a whole depends significantly.

2. The detection in the receiving set of its address - SAP, in the demodulated sequence of binary symbols is performed by the classical method known in the technical literature - using a discrete identifier of the desired address code combination of binary symbols, i.e. code combination decoder [5], [6]. At the output of such a discrete identifier, a log response appears. "1", when a group of consecutive binary symbols is detected in the demodulated sequence, completely corresponding to the address combination of symbols in the WG, transmitted by the transmitting set. However, in this case, with an increase in the number of symbols in the address combination of symbols in order to reduce the likelihood of false detection of the RG, the probability of its skipping significantly increases due to the appearance of at least one erroneously pleasant symbol in the address code combination.

3. The receiving set does not contain a device for detecting the emitted signal, recognizable by the type of manipulation, the speed of the symbols, characteristic features - points, as well as the SFP. With the help of this device, it is possible to limit the duration of the time intervals for searching for the address WG in the output signal of the demodulator. In the absence of such a device, a continuous search for the RG is performed, including in the time intervals between the transmission of the next RG, when at the output of the demodulator there is a chaotic alternation of the symbols "1" and "0" due to the action of the voltage of noise of various origins at the input of the RGU. This leads to frequent false detections of the WG due to an increase in the probability of typing at the output of the demodulator a combination of symbols similar to the address codeword of symbols.

The tasks to be solved by the present invention - a method of transmitting and receiving discrete messages in a decameter radio communication complex, are:

1) increasing the noise immunity of receiving the basic information - IP, a radiogram transmitted by OFT signals, by reducing the number of double errors in independent messages contained in each radio message - SFP, SAP, IP;

2) increasing the probability of correct detection of the SAP RG;

3) reducing the probability of false detection of the SAP RG.

The solution to the set tasks is achieved by the fact that in the known method of transmitting and receiving discrete messages in a decameter radio communication complex, in accordance with which, in the transmitting set of the complex, using a coding device, which is used as a personal computer (PC), a modulating binary sequence of a discrete message - a radiogram (WG), containing at the beginning of the WG a service sequence of points (SPT) - a meander with a duration of K binary symbols, a service phasing sequence (SPF) following it in time with a duration of Q symbols, and an information sequence (IP) with a duration of Z symbols - the result of encoding the original messages from the source of messages, the output signal of the modulator is amplified in power in the radio transmitting device and radiates the WG into the air using the transmitting antenna, and in the receiving set of the complex, the radio signal reflected from the ionosphere is received using the receiving antenna and the radio receiving device, filtering the converted and converted output signal of which is demodulated in the demodulator, and in the decoding device, which is used as a PC, the binary sequence of the RG is decoded and the original message is presented to the recipient of the messages, in addition, a radiogram forming device (RFR) is introduced into the transmitting set, in which the formation of the modulating binary sequence of the RG by uniformly introducing R symbols of the service address sequence (SAS) among the Q symbols of the SFF and the following part of the IP, consisting of L <Z information symbols, for this the sequence from the output of the encoder at a selected rate is fed to the the sequence is simultaneously fed to the input of the clock synchronization device (TCB), the information input of the M-bit shift register with the number of bits M = L + Q with ordinal numbers m = 1, 2, ..., M, corresponding to the order of the bits - from the senior (output) discharge - at m = 1, to a lower th (input) bit - at m = M, and to the information input of the N-bit shift register with the number of bits N = L + Q + R with ordinal numbers n = 1, 2, ..., N with the same order of the bits, while for sequential advancement of discrete information (DI) from the output of the encoder through the bits of the shift registers, the sequence of clock pulses from the output of the TCB is fed to the clock input of the M-bit shift register, and to the clock input of the M-bit shift register through a delay element, while before forming of the modulating sequence RG in each bit of the R-bit storage register with the ordinal numbers of the bits r = 1, 2, ..., R corresponding to the sequence in time of the SAP symbols, write the corresponding SAP symbols, in addition, the information inputs for rewriting the CI of the two extreme bits of the Bit register shift with ordinal numbers n = 1, N is connected to the outputs of the corresponding two extreme bits of the R-bit storage register with ordinal numbers r = 1, R, the outputs of the remaining bits of the R-bit storage register with serial numbers r = 2, 3, ..., (R-1) are connected to the information inputs of rewriting the ID of the corresponding bits of the N-bit shift register with serial numbers n = ( 2 + X), (3 + 2X), ..., [(R-1) + (R-2) X], where X is the largest integer selected from the condition X <(N-R + 1) / ( R-2), the information inputs for rewriting the DI of the remaining M bits of this shift register, following in the order of increasing their sequence numbers, are connected to the corresponding outputs of the bits of the M-bit shift register with sequence numbers, following in the same order, while, if upon arrival of the next i-th clock pulse from the TCB output, Q is filled with SFP symbols and the following L symbols of the IP from the output of the encoder of the last M bits of the N-bit shift register and all bits of the M-bit shift register, the output of each of the first Q bits of which with serial numbers m = 1, 2, ..., Q are additionally connected to corresponding to the input of the decoder, then using the decoder, detection of the SPP is performed and a pulse is generated by its output signal by means of a pulse shaper, which is fed to the pulse input of the rewriting of the DI in the bits of the N-bit shift register, as a result, the rewriting is carried out in the bits of this shift register of the DI from the outputs of the bits M-bit register

shift and from the outputs of the digits of the R-bit storage register, after which, with the arrival of the next (i + 1) -th clock pulse from the output of the TCS from the information output of the N-bit shift register to the output of the UFR and then to the input of the modulator, they are fed element by element without breaking synchronous sequence of symbols with the previously transmitted symbols of the initial part of the RG - SPT, followed by the generated manipulating sequence of the remainder of the radiogram with a uniform distribution of R EPS symbols among Q SPP symbols and L symbols of the subsequent IP.

In addition, in the receiving set of the decameter radio communication complex, a device for detecting and converting radio messages (ROPR) is additionally introduced, to the input of which a demodulated binary sequence is fed from the output of the demodulator, and which is simultaneously fed into the ROPR to the inputs of an additional TCB and signal analyzer, as well as to information inputs additional M-bit and N-bit shift registers, similar to the shift registers of the UFR of the transmitting set, while for the sequential advancement of the DI from the output of the demodulator through the bits of the shift registers, the sequence of clock pulses from the output of the additional TCS is simultaneously fed to the clock inputs of the additional M-bit and N- bit shift registers, and to the clock inputs of the signal analyzer and the search interval limiter, when the signal analyzer detects the signal by the characteristic features: the presence of the SPT at the beginning of the WP and the subsequent SPP, decimated by the SAP symbols, the temporal location of which among the SPP symbols It is known that the output signal of the signal analyzer is fed to the first input of the search interval limiter, with the help of which the enabling logic level "1" is formed and from its first output it is fed to the control input of the adder, the duration of the enabling logic level is set no more than D <N + K / 2 clock intervals (TI) of the additional TCS, within which they search in the additional N-bit shift register of a sequence of a similar SAP by the maximum number of matching symbols, in the absence of such a level that allows the search, the opposite logic level "0" at the control input of the adder provides reset and hold in the zero state of the adder, to the R single-bit inputs of which logic levels are fed from the outputs of the corresponding equivalence elements, the outputs of the two extreme bits of the additional N-bit shift register with serial numbers n = 1, N are connected to the first inputs of the corresponding equivalence elements, the second inputs of which are connected to the outputs of the corresponding two extreme digits of the additional R-bit storage register, similar to the storage register of the UDF of the transmitting set, with the ordinal numbers of the digits r = 1, R, the remaining bit outputs of the additional R-bit storage register with the ordinal numbers r = 2, 3, ... , (R-1) is connected to the second inputs of other corresponding equivalence elements, the first inputs of which are connected to the corresponding bit outputs of an additional N-bit shift register with ordinal numbers n = (2 + X), (3 + 2X), ..., [( R-1) + (R-2) X], the outputs of the remaining M bits of this shift register, following in the order of increasing their ordinal numbers, are connected to the information inputs for rewriting the DI of the corresponding bits of the additional M-bit shift register with ordinal numbers in the order their increase, the information output of which is connected to the first input of the AND element, the output of which is the output of the UOPR, and the second input of the AND element is connected to the second th output of the search interval limiter, thus, from the moment of detection of the RG, they begin to search for their own (for a given radio subscriber) SAP, for this, at each shift of the input sequence in an additional N-bit shift register, a symbol-by-symbol comparison is made in each of the R equivalence elements at its two inputs - the symbol at the output of the corresponding bit of the additional N-bit shift register and the symbol at the output of the corresponding bit of the additional R-bit storage register, in which the corresponding SAP symbol is written similarly to the R-bit storage register of the UDF of the transmitting set, while the outputs of the individual elements of equivalence appear logical symbols "0" - if the compared symbols do not match, or logical symbols "1" - if they coincide, while in each clock interval, using the adder, the unit responses are summed at the outputs of the equivalence elements, and at the beginning of the first TI from the moment the resolving level "1" at the first output of the search interval limiter, along its leading edge with the help of the first additional pulse shaper, a pulse is formed, which is fed through the first input of the OR element to the pulse input of the DI rewriting into the RAM memory cells, providing the number zero in the RAM memory cells binary code arriving at the beginning of the first TI from the outputs of the adder, then, within the same TI, the first result of summing the unit responses at the outputs of the equivalence elements will arrive at the outputs of the adder, which, arriving at the second inputs of the second comparison block, is compared with the number zero at its first inputs - from the outputs of the RAM, since the result of summation in the first and in any other TI will most likely be greater than zero if the characters "1" and "0" appear equally at any positions of the received binary sequence, then a voltage drop will appear at the output of the second comparison block - logic level "1", which is fed through the second input of the OR element to the pulse input for rewriting the DI in the RAM memory cells, ensuring the writing of the number from the outputs of the adder into the RAM memory cells, and, accordingly, the equality of the compared numbers at the inputs of the second comparison block and at its output, the logical level "0" appears again, in the next second TI, when the input sequence has advanced one bit in the additional M-bit and N-bit shift registers in the direction of their first bits, they start summing again using the adder of single responses at the outputs of the equivalence elements when comparing in them another sequence of symbols at the outputs of the same bits N- bit shift register, in this case, if the result of summing the single responses has become larger than that written in the RAM in the previous TI, then the larger result is overwritten in the RAM instead of the previous one, and from the RAM outputs a new number in binary code is fed to the first inputs of the first comparison block, to the second whose inputs serve a threshold number in binary code from the outputs of the sensor n threshold number, in general, if in the considered i-th TI the maximum number overwritten in RAM is less than the threshold number, then it is considered that the address sequence is not found in this TI, and proceeds to search for it on the next (i + 1) th TI , in this case, if at the next sequence shift on the (i + 1) th TI, the result of summing the single responses at the outputs of the equivalence elements will be greater than all previous summation results, which are overwritten in RAM, and will be greater than the threshold number from the outputs of the threshold number sensor, which means the detection of its own SAP, then at the output of the first comparison unit, a logical level "1" is formed, along the leading edge of which a pulse is formed using the second additional pulse shaper, which is fed to the pulse input of the rewriting of the DI in the bits of the additional M-bit shift register, as a result the bits of this shift register are overwritten by the symbols of the IP and the symbols of the SFP of the detected RG (without the symbols of the SAP) from the corresponding of the additional N-bit shift register, at the same time a pulse from the output of the second additional pulse shaper is fed to the second input of the search interval limiter, and at its second output, another enabling logic level "1" is formed, the duration of which (in TI) is equal to the duration of the received RG ( without taking into account the number of SCT symbols), this level is fed to the second input of the AND element, while with the arrival of subsequent clock pulses, the contents of the additional M-bit shift register, which is the first initial part of the received RG without SCT symbols, from the information output of this shift register element by element is fed to the output of the UOPR through the first input of the AND element and then to the input of the decoding device, the subsequent second part of the received RG consists only of IP symbols and enters the information input of an additional M-bit shift register and then, moving along the bits of this shift register, to decoder input, following n The first part of the RG without violating the synchronous sequence of binary symbols, after the end of the RG entering the decoding device, the AND element, which acts as an inhibiting element, is "locked" by the logic level "0" from the second output of the search interval limiter.

Comparative analysis with the prototype shows that the introduction of essential distinctive features is novelty and allows, as will be shown below, to solve the assigned tasks.

Let us consider the effectiveness of the proposed invention on the example of the functioning of a decameter radio communication complex, the electrical structural diagram of which is shown in the figure with L = 8, Q = 4, M = 12 R = 7, N = 19, X = 2, R <Z. Adjacent bits of shift and storage registers are conventionally separated by dotted lines. For the purpose of clarity and simplification of the representation of electrical connections, the inputs and outputs of the bits of the shift and storage registers are indicated by the directions of the arrows of the electrical connections.

The decameter radio communication complex contains a transmitting set 1 containing an encoder 2, which is used as a personal computer (PC), with the help of which a modulating binary sequence of a discrete message - radiograms (RG) is formed, as well as serially connected modulator 3, a radio transmitting device 4 and the transmitting antenna 5, as well as the receiving set 6 containing the serially connected receiving antenna 7, the radio receiving device 8 and the demodulator 9, as well as the decoding device 10, which is used as a PC.

In addition, the transmitting set contains a radiogram forming device (RFR) 11, the input and output of which are connected, respectively, to the output of the encoder 2 and to the input of the modulator 3. The UVR 11 contains an M-bit shift register 12, in which the number of bits is equal to M = Q + L = 12 with ordinal numbers m = 1, 2, ..., 12, corresponding to the order of the bits - from the most significant (output) bit - at m = 1, to the least significant (input) bit - at m = 12, N-bit shift register 13, in which the number of bits is equal to N = Q + L + R = 19 with serial numbers n = 1. 2, ..., 19, corresponding to the order of the bits - from the most significant bit to the least significant one at Q <R <L, where R is the number of symbols in the SAP, R-bit storage register 14, in which the number of bits is R = 7 with the ordinal numbers of the bits r = 1, 2, ..., 7, corresponding to the order of the symbols of the SAP, as well as the UTS 15, the input of which, which is the input of the UFR 11, is combined with the information inputs of the M-bit shift register 12 and the N-bit shift register 13 corresponding to the information inputs the first bits of these shift registers. The output of the TCB 15 is connected to the clock input of the N-bit shift register 13 and through the delay element 16 is connected to the clock input of the M-bit shift register 12, the information inputs for rewriting discrete information (DI) of the two extreme bits of the N-bit shift register 13 with sequence numbers n = 1.19 connected to the outputs of the corresponding two extreme bits of the R-bit storage register 14 with serial numbers r = 1.7. The outputs of the remaining bits of the R-bit storage register 14 with serial numbers r = 2,3, ..., 6 are connected to the information inputs for rewriting the ID of the corresponding bits of the N-bit shift register 13 with serial numbers n = (2 + X), (3 + 2X),…, [(R-1) + (R-2) X] = 4, 7,…, 16, where X is the largest integer selected from the condition X <(N-R + 1) / ( R-2), which is performed when X = 2. The information inputs for rewriting the DI of the remaining M bits of the N-bit shift register 13, following in the order of increasing their ordinal numbers, are connected to the corresponding outputs of the bits of the M-bit shift register 12 with ordinal numbers, following in the same order, with the output of each of the Q first bits of the M-bit shift register 12 with serial numbers m = 1,2,3,4 is additionally connected to the corresponding input of the decoder 17, the output of which through the pulse shaper 18 is connected to the pulse input for rewriting the DI into the bits of the N-bit shift register 13, information output which, corresponding to the information output of its first bit, is the output of the UVR 11.

In addition, the receiving set 6 contains a device for detecting and converting radio messages (ROPR) 19, the input and output of which are connected, respectively, to the output of the demodulator 9 and the input of the decoding device 10. ROPR 19 contains an _{additional Bit shift register 12 1} , an additional N-bit shift register 13 ₁ , an additional R-bit storage register 14 ₁ , similar to the corresponding shift registers 12, 13 and storage 14 from the UFR 11 of the transmitting set 1, as well as an additional UTS 15 ₁ , the input of which, which is the input of the UOPR 19, is combined with the information inputs of the signal analyzer 20, an additional M-bit shift register 12 ₁ and an additional N-bit shift register 131, the output of an additional TCB 15 _{1 is} connected to the clock input of the signal analyzer 20, to the clock input of the search interval limiter 21, to the clock input of an additional N-bit shift register 13 ₁ and the clock input of the additional M-bit shift register 12 ₁ , you the path of the signal analyzer 20 is connected to the first input of the search interval limiter 21, the first output of which is connected to the control input of the adder 22 and through the first additional pulse shaper 18 _{1 is} connected to the first input of the OR element 23, the output of which is connected to the pulse input of rewriting the DI of the random access memory ( RAM) 24, the outputs of which are combined with the corresponding first inputs of the first comparison unit 25 and with the corresponding first inputs of the second comparison unit 25 ₁ , the output of which is connected to the second input of the OR element 23, the second inputs of the second comparison unit 25 _{1 are} combined with the corresponding information inputs for rewriting DI into the memory cells of the RAM 23 and with the corresponding outputs of the adder 22, the second inputs of the first comparison unit 25 are connected to the corresponding outputs of the threshold number sensor 26, and the output of the first comparison unit 25 through the second additional pulse shaper I82 is connected to the second input of the search interval limiter 21 and with the pulse input for rewriting the DI in the bits of the additional M-bit shift register 12 ₁ , the outputs of the two extreme bits of the additional Bit shift register 13 ₁ with serial numbers n = 1.19 are connected to the first inputs of the corresponding equivalence elements (27 ₁ , 27 ₇ ) the second inputs of which are connected to the outputs of the corresponding two extreme bits of the additional R-bit storage register 14 ₁ with serial numbers r = 1.7, the outputs of the remaining bits of the R-bit storage register 14 ₁ with serial numbers r = 2, 3, ..., 6 are connected with the second inputs of other corresponding elements of equivalence (27 ₂ , ..., 27 ₆ ), the first inputs of which are connected to the outputs of the corresponding bits of the additional N-bit shift register 13 ₁ with serial numbers n = (2 + X), (3 + 2X), ..., [(R-1) + (R-2) X] = 4, 7, ..., 16, the outputs of the remaining M bits of this shift register, following in the order of increasing their ordinal numbers, are connected to the information inputs of rewriting the DI, respectively of the current bits of the additional M-bit shift register 12 ₁ with serial numbers in the order of their increasing, the information output of which is connected to the first input of the I element 28, the output of which is the output of the UOPR 19, and the second input of the I element 28 is connected to the second output of the interval limiter search 21.

The decameter radio communication complex functions as follows. In transmitting set 1, the original message or informational text of a radio message (RG), typed from the keyboard of a personal computer (PC) used as an encoder 2, is encoded with a noise-immune code [3] using a special program installed in the PC. In this case, the number of symbols of the information sequence (IP) after the coding of the original text (message) of the radiogram becomes equal to Z symbols.

Further, in the coding device - PC 2, an SFP with a duration of Q symbols is added to the next in time first information binary symbol from the IP of the encoded binary message. In addition, ahead (in time) of the TFP, an SPT is also added - a meander, with a duration of K symbols, necessary to enter the synchronism of an additional clock synchronization device (TCS) 15 ₁ [5] in the receiving set 6 of the complex.

The modulating sequence formed in this way is fed from the output of the encoder - PC, using a serial interface module as part of the PC, for example, at the C1-TG junction at the required speed to the input of the UFR 11. Similar PCs of the "Baguette" type, equipped with modules of serial interfaces of various types manufactured by KB "Korund", Moscow.

The task of the UDF 11 is the final formation of the modulating binary sequence of the RG by uniformly introducing among the symbols of the TFP from Q symbols and the following encoded IP from L <Z information symbols,

constituting the main part of the encoded message or the encoded message as a whole.

To do this, in the UFR 11, the input sequence from the output of the encoder 2 is fed to the clock synchronization device (TCS) 15 and to the information input of the M-bit shift register 12, in which the number of M = Q + L = 4 + 8 = 12 bits with serial numbers m = 1, 2, ..., 12, corresponding

the order of the bits - from the most significant (output) bit - at m = 1, to the least significant (input) bit - at m = 12, and is equal to the number of Q SFP symbols and L IP symbols in the binary sequence at the output of the encoder 2, excluding the next one in front in time SPT - meander.

The information input of the M-bit shift register 12 and any other shift register is actually the information input of the last (input) bit of the shift register. Accordingly, the information output of any shift register is the output of the first (output) bit of the shift register. The information input and the information output of the shift register are decoupled, respectively, from the information input of overwriting the DI of the last bit and the output of the first bit of this shift register using the necessary logic elements.

At the same time, the input sequence is fed to the information input of the N-bit shift register 13, in which the number N = Q + L + R = 19 bits with sequence numbers n = 1. 2, ..., 19, corresponding to the order of the digits - from the most significant bit to the least significant one at Q <R <L, where R is equal to the number of binary SAP symbols entered in this shift register 13 evenly among the M binary symbols of the sequence at the output of the encoder.

High-speed TCB 15 [7] (in operating conditions without interference) when several points arrive at the beginning of the sequence, the SCT enters synchronism and provides with each clock pulse at its output the sequential advancement of the binary symbols of the sequence from the output of the encoder 2 along the bits of the N-bit shift register 13. With some small delay, determined by the delay element 16, the same symbols are sequentially advanced along the bits of the M-bit shift register 12. A small delay of clock pulses is necessary to eliminate failures when writing the ID from the outputs of the bits of the M-bit register to the bits of the N-bit register shift. The delay element 16 can be performed, for example, using an even number of serially connected elements NOT [8].

Binary characters of the address sequence for a particular radio subscriber are recorded for storage in the bits of the R-bit storage register 14 in advance - before the formation of the manipulating sequence RG. When transmitting a WG to another radio subscriber, the address sequence is replaced.

The outputs of the bits of the R-bit storage register 14 are connected to the information inputs for rewriting the CI of the corresponding bits of the N-bit shift register 13, and the information inputs for rewriting the CI of the remaining M bits of the N-bit shift register 13 are connected to the corresponding outputs of the bits of the M-bit shift register 12. The serial numbers of the connected bits of the indicated registers 12, 13 and 14 for inputs and outputs are given above. At the same time, when, when the next clock pulse arrives from the output of the TCB 15, the M symbols of the SFP and the following part of the IP from the output of the encoder 2 from the output of the encoder 2 of all bits of the M-bit shift register 12 are filled (without taking into account the previously passed through the M-bit shift register, ) and the last M bits of the N-bit shift register 13, the decoder 17 will work on a combination of Q = 4 SFP symbols. As a result, the pulse from the output of the pulse shaper 18 will provide rewriting in the bits of the N-bit shift register 13 of the logical levels from the outputs of the bits of the M-bit shift register 12 and from the outputs of the bits of the R-bit storage register 14. Reliability of rewriting the DI into the bits of the shift register 13 is ensured, as noted above, the delay element 16. When subsequent clock pulses arrive from the output of the TCB 15, from the information output of the N-bit shift register 13 to the output of the UFR 11 and then to the input of the modulator 3, the required manipulating sequence of the radiogram will be advanced element by element with a uniform distribution R symbols of the address sequence among the Q symbols of the SPT and L <Z symbols of the subsequent encoded IP. In this case, the speed of the symbols at the output of the UVR 11 does not change.

If it is required to transmit the RG by the OFT signals, then in the modulator 3 the input binary sequence is recoded [3] in order to introduce relativity and is fed to the phase modulator. In the radio transmitting device 4, the signal is amplified in power and, with the help of the transmitting antenna 5, the RG is emitted into the air.

In the receiving set 6, the RG is received using the receiving antenna 7 and the radio receiving device 8, from the output of which the signal filtered from interference is demodulated in the demodulator 9 and fed to the input of the UOPR 19. In this device, the demodulated signal is fed to the inputs of the additional TCS 15 ₁ and the signal analyzer 20, as well as to the information inputs of additional M-bit and N-bit shift registers 12 ₁ and 13 ₁ , in which the binary sequence, which begins, as indicated above, with the SPT, under the influence of clock pulses from the output of the TCB 15 ₁ moves sequentially along bits of these shift registers.

The task of the signal analyzer 20 is to detect radiograms according to their characteristic features: the presence of an SPT at the beginning of the RG and the subsequent SPP, decimated by the SAP symbols, the temporal location of which among the symbols of the phasing sequence is known. Signal analyzer 20 can be made, for example, based on the shift register and decoder SFP and a fragment of a meander.

When the WG is detected, the output signal of the signal analyzer 20 is fed to the first input of the search interval limiter 21, with the help of which the enabling logic level "1" is formed and from its first output it is fed to the control input of the adder. The duration of the enabling logic level is set at no more than D clock intervals (TI) of the additional TCB 15 ₁ , within which a search is performed in the additional N-bit shift register 13 _{1 for a} sequence of a similar SAP by the maximum number of matching symbols. Considering that the number of binary symbols K in the SPT is significantly greater than in the TFP, and that under poor communication conditions, a false set of TFP symbols is possible, it is preferable to choose the value D from the condition: D <N + K / 2. In the absence of such a level that allows the search, the opposite logic level "0" at the control input of the adder provides reset and hold in the zero state of the adder, to the R single-bit inputs of which logic levels are supplied from the outputs of the corresponding equivalence elements. The outputs of the two extreme bits of the additional N-bit shift register 13 ₁ with ordinal numbers n = 1.19 are connected to the first inputs of the corresponding elements of equivalence 27 ₁ , 27 ₇ , the second inputs of which are connected to the outputs of the corresponding two extreme bits of the additional R-bit storage register 14 ₁ , similar to the R-bit storage register of the UDF of the transmitting set, with the ordinal numbers of bits r = 1.7, the remaining outputs of the bits of the additional R-bit storage register 14 ₁ with the serial numbers r = 2, 3, ..., 6 are connected to the second inputs of others corresponding elements of equivalence, the first inputs of which are connected to the corresponding bit outputs of the additional N-bit shift register with sequence numbers n = 4, 7, ..., 16, the outputs of the remaining 12 bits of this shift register, following in the order of increasing their sequence numbers, are connected to information inputs for rewriting the corresponding bits of the additional M-bit shift register ha 12 ₁ with serial numbers in the order of their increasing, the information output of which is connected to the first input of the element And 28, the output of which is the output of the UOPR 19, and the second input of the element And 28 is connected to the second output of the search interval limiter 22, thus, from the moment of detection of the RG, they begin to search for their own (for a given radio subscriber) SAP, for this, for each shift of the input sequence in an additional N-bit shift register 13 ₁ , a character-by-character comparison is made in each of the 7 equivalence elements 27 ₁ ... 27 ₇ at its two inputs - a symbol at the output of the corresponding bit of the additional N-bit shift register 13 ₁ and the symbol at the output of the corresponding bit of the additional R-bit storage register 14 ₁ . In this case, logical symbols "0" will appear at the outputs of individual elements of equivalence - if the compared symbols do not match, or logical symbols "1" - if they match. In this case, in each clock interval using the adder 22 [8], the unit responses are summed at the outputs of the equivalence elements 27 ₁ ... 27 ₇ . At the beginning of the first TI, from the moment the enable level "1" appears at the first output of the search interval limiter 21, a pulse is generated on its leading edge using the first additional pulse shaper 18 ₁ , which is fed through the first input of the OR element 21 to the pulse input of rewriting the DI into the cells RAM memory 24, providing a record in the RAM memory cells 24 of the number zero in a binary code, arriving at the beginning of the first TI from the outputs of the adder 22. Further, within the same TI, the first result of the summation of single responses at the outputs of the equivalence elements 27 ₁ ... 27 ₇ , which, arriving at the second inputs of the second comparison unit 25 ₁ , is compared with the number zero at its first inputs - from the outputs of the RAM 24. Since the result of summation in the first and in any other TI will most likely be greater than zero if the symbols “ 1 "and" 0 "at any positions of the received binary sequence, then at the output of the second comparison block 25 ₁ by there will be a voltage drop - a logic level "1", which, through the second input of the OR element 21, is fed to the pulse input for rewriting the DI in the memory cells of RAM 24, providing a number from the outputs of the adder 22 to the memory cells of the RAM 24, ensuring equality of the compared numbers at the inputs of the second the comparison unit 25 ₁ and at its output the logic level "0" appears again. In the next second TI, when the input sequence has advanced one bit in the additional M-bit and N-bit shift registers in the direction of their first bits, the summation is again started using the adder 22 of single responses at the outputs of the equivalence elements when analyzing another sequence of characters in N -bit shift register and distributed among other characters as well as the characters of the address sequence. In this case, if the result of summing the single responses has become larger than that written in RAM 24 in the previous TI, then the larger result is overwritten in RAM instead of the previous one, and from the RAM outputs a new number in binary code is fed to the first inputs of the first comparison unit 25, to the second inputs of which a threshold number in binary code is supplied from the outputs of the threshold number 26 sensor. In general, if in the considered i-th TI the maximum number rewritten in RAM 24 is less than the threshold number, then it is considered that the address sequence is not found in this TI, and go to its search on the next (i + 1) th TI. In this case, if at the next sequence shift on the (i + 1) th TI, the result of summing the single responses at the outputs of the equivalence elements will be greater than all the previous summation results, which are overwritten in RAM, and will be greater than the threshold number from the sensor outputs of the threshold number 26, which means the detection of its own SAP, then at the output of the first comparison unit 26, a logical level "1" is formed, along the leading edge of which a pulse is generated with the help of a second additional pulse shaper 18 ₂ , which is fed to the pulse input for rewriting the DI in the bits of an additional M-bit shift register, As a result, the IP symbols and the SFP symbols of the detected RG (without the SAP symbols) from the corresponding bits of the additional N-bit shift register 13 ₁ are rewritten into the bits of this shift register.

At the same time, a pulse from the output of the second additional pulse shaper 182 is fed to the second input of the search interval limiter 21, and at its second output another enabling logic level "1" is formed, the duration of which (in TI) is equal to the duration of the received WG (excluding the number of SPT symbols). This level is fed to the second input of the AND element 28, while with the arrival of subsequent clock pulses, the content of the additional M-bit shift register 12 ₁ , which is the first initial part of the received RG, consisting of SFP and IP symbols without SPT and SAP symbols, from the information output of this shift register is fed elementwise to the output of the UOPR through the first input of the AND element 28 and then to the input of the decoding device 10. The subsequent second part of the received RG consists only of the IP symbols and is fed to the information input of the additional M-bit shift register from and then to the input decoding device 10 following the first part of the WG without breaking the synchronous sequence of binary symbols. At the end of the arrival of the RG in the decoding device 10, the AND element 28, which acts as an inhibiting element, is "locked" by the logic level "0" from the second output of the search interval limiter 21, which significantly reduces the probability of false detection of the RG.

Let us consider a set of events favorable to the detection of EPS in the general stream of received binary information. Correct SAS detection will take place when the first and last SAS symbols with sequence numbers r = 1, R are located in the first and last bits of the N-bit shift register with sequence numbers n = 1, N, while the number of correctly received symbols should reach some threshold number i. Denoting by P (P = i) the probability that after the analysis of D sequences is completed, i true “single” responses will be counted from one of them, and a smaller number of responses from any other. Let us write down these probabilities of correct detection of SAP when counting from one of the sequences exactly 1, 2, ..., i, ..., R "single" responses:

Here R _P is the probability of receiving the EPS symbol R _P = 1-R _Osh (P _Osh is the probability of the error of the EPS symbol); R _L - the probability of a false SAP symbol at any of the D-1 analyzed positions of the analysis interval D TI; C ⁱ _R - the number of combinations of R elements by i (here it is assumed that the distortion of the SAP symbols, as well as the appearance of false APS symbols in D-1 of the analyzed sequences at the outputs of the equivalence elements 27 ₁ , ..., 27 ₇ do not depend on the sequence number) ... Expressions in square brackets in formulas (1) represent the probabilities that at the end of the analysis of D sequences from any of the D-1 sequences that are not the required one, there will be less than 1, 2, ..., i, ..., R false SAP symbols. Let us denote these probabilities in general form by P (A <i), i.e.

Accordingly, the value of the value [P (L <i)] ^D-1 will represent the probability that at the end of the analysis of D sequences, not from one of them, except for the desired SAP, will not receive more than i-1 false SAP symbols. Thus, the general expression for P (P = i) can be represented as

Since the events under consideration, the probability of occurrence of each of which is determined by formula (3), are mutually independent, then the total probability of correct detection of the desired AP will be equal to

If the maximum number of "single" responses is limited by the threshold number i = F, then the probability of correct EPS detection is considered when more than the number of responses have been accumulated from one of the analyzed D sequences. This probability in relation to the proposed method can be represented taking into account (2) and (3) in the form

Let us now find the exact expression for determining the probability of false detection of the SAP, taking into account the fact that the analysis begins after the adder 22 is reset to zero. Since the analysis of the sequences for compliance with the SAP in the N-bit shift register 131 is performed sequentially in time, a false detection of the SAP can occur during the analysis of the first sequence from the moment of detection of the RG, or the second, etc., up to the D-1 sequence, if when analyzing the previous sequences of false detection of EPS did not occur. Let us write down these probabilities of false detection of EPS when summing up i “single” responses.

In this case, false detection of SAP can occur only when more “single” responses are received from one of the D-1 analyzed sequences, which is not the desired one, than from any other sequence.

Let us denote by P (A = i) the probability that at the end of the analysis of D sequences, i false “single” responses will be counted from one of them, and a smaller number of responses from any other. Let us write down these probabilities of false detection of SAP when counting from one of the sequences exactly 1, 2,…, i,…, R “single” responses:

Here, the expressions in the left square brackets of each of the formulas represent the probabilities that at the end of the analysis in any of the D-1 analyzed sequences, less than 1, 2,…, i,…, R “single” responses were detected. These probabilities were previously presented in the form (2). The expressions in right square brackets in each of the formulas (6) represent the probabilities that at the end of the analysis of D sequences, no more than i-1 “single” responses will come from the true EPS. By analogy with (2), we denote these probabilities in general form by P (P <i), i.e.

Taking into account (7), the general expression for P (A <i) will have the form

By analogy with (4), the total probability of false detection of an accident can be written as

If the maximum number of "single" responses is limited by the threshold number i = F, then the probability of false EPS detection is considered when more than the number of responses have been accumulated from one of the analyzed sequences. This probability can be represented taking into account (2) and (3) in form

It is assumed here that, in accordance with the optimal search algorithm for SAP based on the maximum a posteriori probability, the decision on the choice of the required SAP is made after the analysis of D sequences is completed. In the proposed complex (Fig. 1), false detection of SAP can occur when analyzing the sequence from which the maximum number of "single" responses exceeding the threshold number F. The number of analyzed binary sequences favorable to the event in question is equal to D-1. Accordingly, the probability of false detection of SAP will be determined by expression (10) without taking into account the last factor:

Let us consider the probabilistic characteristics of the known methods of transmitting and receiving radio messages, the implementation of which is made in the form of known communication complexes. Traditionally, SAP detection is performed using a decoder or a discrete identifier [6] of the address code combination of symbols.

Using the probability multiplication theorem [10], we determine the probability of correct detection of SAP when decoding a combination of R true symbols of SAP in one of the clock intervals (TI) with the sequential advancement of the received RG in the shift register 13 ₁ :

Let the search for SAP in a known complex is carried out by, for example, analysis in the N-bit shift register 13 _{1 of the} received RG using a code combination decoder of R consecutive symbols. For this, the R inputs of the decoder are connected to the outputs of the corresponding R first bits of the shift register 13 ₁ . With the sequential advancement of the RG in the bits of the shift register, the flow of D TI, as in the proposed complex, we will search for SAP. Let us determine the probability that at the last D-th TI SAP will be detected in the form of a response at the output of the decoder The sought-after probability R _ON will be equal to the product of two independent events: the absence of decoder responses at each shift of discrete information during the first D-1 clock pulses at the clock input shift register from the start of the search and the appearance of a response at the last D-th shift of information. Taking into account (12), we can write:

It is assumed here that with the sequential advancement of the RG binary sequence along the shift register bits, the appearance of a false SAP symbol at any time position of the RG controlled by the decoder, except for the true time position of each SAP symbol, when the detection of SAP is recorded, is equally probable and equal to R _L = 0.5.

The probability of false detection _RL SAP view of the above can be represented as follows:

In fact, in the known communication complexes, the number of shifts of the received binary signal in a hypothetical shift register, R bits of which are controlled by a continuous SAP decoder, is not equal to D, as in the proposed complex, but much more, for example, S, that is, e, S >> D , since the search interval for EPS is not specified, including in the pauses between the received WGs. Accordingly, expression (14) will take the form:

Comparing expressions (11) with Р _Л = 0.5 and (15), it is obvious that P (Л> F) <Р _ЛО , i.e. the probability of false detection of the SAP during the implementation of the invention is less than the probability of false detection of the SAP of the prototype.

In accordance with formula (5), the probability of correct detection of SAP when using the proposed method of transmitting and receiving discrete messages in a decameter radio communication complex with R _L = 0.5 and with the same number D of analyzed sequences will have the form:

For a visual comparison of formulas (13) and (5), we take R = 4, P _P = 0.9, F = 2, then

Each of the expressions (17) and (18) consists of two factors, without making any final calculations, so that you can see how each of the factors of the compared formulas differs, we get:

Accordingly, the inequality P (P>F)> P _PO is satisfied, i.e. The proposed method for transmitting and receiving discrete messages in a decameter radio communication complex surpasses the known method in terms of the attainable probability of correct detection of RG. In fact, the value of P (P> F) will even more exceed the value of P _PO , since the number D of the analyzed binary sequences during the search for SAP is not controlled and can be much larger than the limited analysis interval D≤N + K / 2 (TI) selected during the implementation the proposed method.

In conclusion, it should be noted that the implementation of the proposed invention - a method for transmitting and receiving discrete messages in a decameter radio communication complex when comparing it with the implementation of a known prototype method that forms a WG in the traditional way, when first a service sequence of points (SPT) is transmitted, then a continuous service phasing sequence (SPT) of symbols (phasing code combination of symbols), after which a continuous service address sequence (SAS) of symbols (address code combination of symbols) is transmitted, then - an encoded information sequence (IP) of symbols (coded message), and when receiving a WG in the traditional way the phasing code combination is detected and its address code combination is recognized with the help of appropriate decoders (discrete identifiers) of grouped combinations of correctly received symbols [4], [5], [6], allows you to achieve the following advantages when the compared complexes operate in the same radio communication conditions (with the same modulation methods, transmission rates of radiograms and with the same values of the probability of erroneous reception of radiogram symbols):

1. When using signals of relative phase telegraphy (OFT) for transmitting radiograms, errors are doubled regardless of the methods of demodulation of the received signals [3], [9].

According to the proposed method of decameter radio communication, when forming the RG, the symbols of the service address sequence (SAS) are evenly distributed among the symbols of the service phasing and encoded information sequences. The ratio of symbols of three categories, carrying different information, is characterized by the value X - the number of service or information symbols through which one symbol follows the address sequence. Accordingly, when implementing the proposed method for decameter radio communication, a decrease in the number of erroneously received service phasing and information symbols in the received RG is achieved by reducing the number of double errors, when double errors affect adjacent symbols from different categories:

1) the symbol of the service phasing sequence and the symbol of the service address sequence;

2) the symbol of the encoded information sequence and the symbol of the service address sequence.

In this case, the sequence of service address symbols before decoding the WG is excluded.

2. The proposed method for transmitting and receiving discrete messages in a decameter radio communication complex surpasses the known method in terms of the attainable probability of correct detection of the RG with the same number of R symbols in the SAP.

3. The proposed method for transmitting and receiving discrete messages provides a decrease in the number of erroneously received symbols of the SAP when exposed to impulse noise with any modulation methods and corresponding demodulation of the received WG. Since, in accordance with the proposed method, R EPS symbols, in contrast to the traditional method, are evenly distributed among other RG symbols, when exposed to impulse noise in the grouped (continuous) EPS symbols, more symbols are distorted than in the distributed EPS.

In addition, with the traditional method of finding its address (using a decoder), the RG is skipped if at least one character of the desired sequence is distorted. In a distributed sequence, for its correct detection, with the required probability, it is allowed to accept several symbols distorted when they are binomially distributed among the correctly received remaining symbols of the address sequence [10].

To reduce the likelihood of false detection of your address, it is necessary when using a known method to increase the number of characters in a continuous SAP. However, this will lead to an even lower probability of correct detection of the WG and an increase in the probability of missing the WG.

When using the proposed method, it became possible to achieve optimization of the indicated probabilities by increasing the symbols of the distributed AP and choosing the permissible number of distorted symbols when detecting its address with the required probability of correctly detecting the RG.

4. In accordance with the proposed method, the introduction of a restriction on the number D of analyzed binary sequences when searching for the SAP, can significantly reduce the probability of false detection of the SAP and exclude false decoding in the time intervals between the reception of neighboring RGs.

Sources of information

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3. Fink L.M. The theory of transmission of discrete messages. M .: Soviet radio. 1970.728 s.

4. Klovsky D. D. Signal transmission theory. Textbook for universities. M .: Communication. 1973.376 s.

5. Automated radio communication with ships / Ed. K.A.Semenov. - Leningrad: Shipbuilding, 1989 (B-ka ship communications engineer). - 336 p.

6. Koltunov M.N., Konovalov G.V., Langurov Z.I. Cycle synchronization in digital communication systems. - M .: Communication, 1980 .-- 152 p.

7.A.S. 1062879 A (USSR). Device for phase synchronization / B.G. Shadrin, Ya.Z. Yagood. - Publ. in BI, 1983, No. 47.

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9. Nazarov V.I. Reception of signals of relative phase telegraphy with a rotating phase. - "Electrosvyaz", 1964, No. 11, p. 9.

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Claims (1)

A method of transmitting and receiving discrete messages in a decameter radio communication complex, according to which in the transmitting set of the complex using a coding device, which is used as a personal computer (PC), a modulating binary sequence of a discrete message is formed - a radiogram (RG) containing at the beginning of the RG service sequence of points (SPT) - a square wave with a duration of K binary symbols, a service phasing sequence (SPP) with a duration of Q symbols and an information sequence (IP) with a duration of Z symbols - the result of encoding the original message from a message source, the modulator output signal is amplified in terms of power in the radio transmitting device and radiate the WG on the air using the transmitting antenna, and in the receiving set of the complex, the radio signal reflected from the ionosphere is received using the receiving antenna and the radio receiving device, the filtered and converted output signal of which is the demodule are decoded in the demodulator, and in the decoding device, which is used as a PC, the RG binary sequence is decoded and the original message is presented to the message recipient, characterized in that, in addition, a radiogram forming device (RFR) is introduced into the transmitting set, in which the formation of the modulating RG binary sequence is completed by uniformly introducing R symbols of the service address sequence (SAS) among the Q symbols of the SFT and the following part of the IP, consisting of L <Z information symbols, for this, the sequence from the output of the encoder at a selected rate is fed to the input of the SDF, in which this sequence is simultaneously is fed to the input of the clock synchronization device (TCB), the information input of the M-bit shift register with the number of bits M = L + Q with serial numbers m = 1,2, ..., M, corresponding to the order of the bits - from the most significant (output) bit - at m = 1, to the least significant (input) bit - at m = M, and on inf The normalization input of the N-bit shift register with the number of bits N = L + Q + R with sequence numbers n = 1,2, ..., N with the same order of the bits, while for sequential advancement of discrete information (DI) from the output of the encoder along bits of the shift registers, the sequence of clock pulses from the TCB output is fed to the clock input of the M-bit shift register, and to the clock input of the M-bit shift register through a delay element, while, before the formation of the modulating sequence of the RG, to each bit of the R-bit storage register with ordinal the numbers of bits r = 1,2, ..., R corresponding to the sequence in time of the symbols of the SAP, write the corresponding symbol of the SAP, in addition, the information inputs of rewriting the CI of the two extreme bits of the N-bit shift register with sequence numbers n = 1, N are connected to outputs of the corresponding two extreme bits of the R-bit storage register with serial numbers r = 1, R, the outputs of the remaining bits are R-bit of the second storage register with ordinal numbers r = 2,3, ..., (R-1) is connected to the information inputs of rewriting the ID of the corresponding bits of the N-bit shift register with ordinal numbers n = (2 + X), (3 + 2X), ... , [(R-1) + (R-2) X], where X is the largest integer, which is selected from the condition X <(N-R + 1) / (R-2), information inputs for rewriting the DI of the remaining M bits of this shift register, following in the order of increasing their ordinal numbers, are connected to the corresponding outputs of the bits of the M-bit shift register with ordinal numbers, following in the same order, while if, when the next i-th clock pulse arrives from the TCB output, Q is filled with symbols SFP and the following L symbols of the IP from the output of the encoder of the last M bits of the N-bit shift register and all bits of the M-bit shift register, the output of each of the first Q bits of which with serial numbers m = 1,2, ..., Q is additionally connected to the corresponding input of the decoder, then using the decoder The device detects the SPP and, according to its output signal, a pulse is generated by means of a pulse shaper, which is fed to the pulse input of rewriting the DI in the bits of the N-bit shift register, as a result, overwriting the bits of this shift register of the DI from the outputs of the M-bit shift register and c the outputs of the bits of the R-bit storage register, after which, with the arrival of the next (i + 1) -th clock pulse from the output of the TCS, from the information output of the N-bit shift register to the output of the UDF and then to the input of the modulator, they are fed element by element without breaking the synchronous sequence symbols with the previously transmitted symbols of the initial part of the RG - SPT, the following formed manipulating sequence of the remaining part of the radiogram with a uniform distribution of R symbols of the SAP among Q symbols of the SFP and L symbols of the subsequent IP, in addition, a detection device is additionally introduced into the receiving set of the decameter radio communication complex and transformation of radiograms ( UOPR), to the input of which a demodulated binary sequence is fed from the output of the demodulator, and which in the UOPR is simultaneously fed to the inputs of an additional UTS and a signal analyzer, as well as to the information inputs of additional M-bit and N-bit shift registers, similar to the shift registers of the UFR transmitting set , while for the sequential advancement of the DI from the output of the demodulator along the bits of the shift registers, the sequence of clock pulses from the output of the additional TCB is simultaneously fed to the clock inputs of the additional M-bit and N-bit shift registers, and to the clock inputs of the signal analyzer and the search interval limiter, upon detection RG signal analyzer according to the characteristic features: the presence of a SPT at the beginning of the RG and the subsequent SPP, decimated by the symbols of the SAP, the temporal location of which among the symbols of the SFP is known, the output signal of the signal analyzer is fed to the first input of the limiter the logic level "1" and from its first output is fed to the control input of the adder, the duration of the enabling logic level is set no more than D <N + K / 2 clock intervals (TI) of the additional TCB, within which the search is performed in the additional N-bit shift register a sequence of such an SAP for the maximum number of matching symbols, in the absence of such a level that allows the search, the opposite logic level "0" at the control input of the adder provides a reset and hold in the zero state of the adder, to the R single-bit inputs of which logic levels are fed from the outputs of the corresponding equivalence elements, the outputs of the two extreme bits of the additional N-bit shift register with ordinal numbers n = 1, N are connected to the first inputs of the corresponding equivalence elements, the second inputs of which are connected to the outputs of the corresponding two extreme bits of the additional R-bit storage register, similar to the UV storage register P of the transmitting set, with the ordinal numbers of the digits r = 1, R, the remaining outputs of the digits of the additional R-bit storage register with the ordinal numbers r = 2,3, ..., (R-1) are connected to the second inputs of other corresponding elements of equivalence, the first inputs which are connected to the corresponding bit outputs of the additional N-bit shift register with the ordinal numbers n = (2 + X), (3 + 2X), ..., [(R-1) + (R-2) X], the outputs of the remaining M bits of this shift register, following in the order of increasing their ordinal numbers, are connected to the information inputs of rewriting the DI of the corresponding bits of the additional M-bit shift register with ordinal numbers following in the increasing order, the information output of which is connected to the first input of the AND element, the output of which is the output UOPR, and the second input of the AND element is connected to the second output of the search interval limiter, thus, from the moment of detection of the RG, they begin to search for their own (for a given radio subscriber) SAP, for this p At each shift of the input sequence in the additional N-bit shift register, a symbol-by-symbol comparison is made in each of the R equivalence elements at its two inputs - the symbol at the output of the corresponding bit of the additional N-bit shift register and the symbol at the output of the corresponding bit of the additional R-bit storage register, in which the corresponding SAP symbol is written in the same way as the R-bit register of storage of the UDF of the transmitting set, while at the outputs of the individual elements of equivalence, logical symbols "0" appear - if the compared symbols do not match, or logical symbols "1" - if they match, while in each the clock interval, using the adder, the unit responses are summed at the outputs of the equivalence elements, and at the beginning of the first TI from the moment the permission level "1" appears at the first output of the search interval limiter, along its leading edge with the help of the first additional pulse shaper, the comfort pulse, which, through the first input of the OR element, is fed to the pulse input for rewriting the DI into the RAM memory cells, ensuring that the number zero in a binary code is written into the RAM memory cells, arriving at the beginning of the first TI from the outputs of the adder, then within the same TI to the outputs of the adder the first result of summing the unit responses at the outputs of the equivalence elements will arrive, which, arriving at the second inputs of the second comparison block, is compared with the number zero at its first inputs - from the outputs of the RAM, since the summation result in the first and in any other TI will be more than zero with a high probability if the symbols "1" and "0" appear equally probable at any positions of the received binary sequence, then a voltage drop will appear at the output of the second comparison unit - a logic level "1", which is fed through the second input of the OR element to the pulse input of overwriting the DI in the RAM memory cells , providing the writing of the number from the outputs of the adder into the memory cells of the RAM, and, accordingly, the equality numbers to be compared at the inputs of the second comparison block and at its output will again appear the logical level "0", in the next second TI, when the input sequence has advanced one bit in the additional M-bit and N-bit shift registers in the direction of their first bits, they start again summation using the adder of single responses at the outputs of the equivalence elements when comparing in them a different sequence of symbols at the outputs of the same bits of the N-bit shift register, while if the result of the summation of the single responses has become larger than that recorded in the RAM in the previous TI, then a greater result overwritten in RAM instead of the previous one and from the outputs of the RAM a new number in binary code is fed to the first inputs of the first comparison unit, to the second inputs of which the threshold number in binary code is supplied from the outputs of the threshold number sensor, in general, if in the considered i-th TI the maximum the number overwritten in RAM is less than the threshold number, then it is considered that the address the th sequence is not found in this TI, and proceeds to search for it on the next (i + 1) th TI, while if at the next shift of the sequence by the (i + 1) th TI, the result of summing the unit responses at the outputs of the equivalence elements becomes greater of all previous summation results, which is overwritten in RAM, and will be more than the threshold number from the outputs of the threshold number sensor, which means the detection of its own SAP, then at the output of the first comparison block, a logical level "1" is formed, along the leading edge of which a pulse is generated using the second additional of the pulse shaper, which is fed to the pulse input of the rewriting of the DI in the bits of the additional M-bit shift register, as a result, the symbols of the MT and the symbols of the SPP of the detected RG (without the SAP symbols) from the corresponding bits of the additional N-bit shift register are rewritten into the bits of this shift register, simultaneously the pulse from the output of the second additional pulse shaper is fed to the second the input of the search interval limiter, and at its second output, another enabling logical level "1" is formed, the duration of which (in TI) is equal to the duration of the received RG (excluding the number of SPT symbols), this level is fed to the second input of the AND element, while with the arrival of subsequent clock pulses, the contents of the additional M-bit shift register, which is the first initial part of the received RG without the SPT symbols, is fed elementwise from the information output of this shift register to the output of the ROPR through the first input of the AND element and then to the input of the The RG consists only of IP symbols, provided that L <Z, and enters the information input of the additional M-bit shift register and then, moving along the bits of this shift register, to the input of the decoding device, following the first part of the RG without disturbing the synchronous sequence binary symbols, at the end of the arrival of the RG in the decoding device, the element And, acting as an element of prohibition, is "locked" by the logic level "0" from the second output of the search interval limiter.

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