RU2747777C1 - Method of receiving signals of relative phase telegraphy in devices for receiving signals with phase manipulation - Google Patents

Abstract

FIELD: telecommunications.

SUBSTANCE: method of receiving signals of relative phase telegraphy in devices for receiving signals with phase manipulation is proposed, according to which the RPT input signal is simultaneously fed to the inputs of the reference coherent voltage generator (hereinafter – RCVG) and the phase detector (hereinafter – PD), in which the input signal is coherently detected using the reference coherent voltage from the RCVG output. The video signal from the PD output is fed to the regenerator, providing registration of a sequence of binary characters at the moment of receipt of clock pulses from the output of the clock frequency allocation unit to the clock inputs of the regenerator and the subsequent code converter (hereinafter – CC), in which the binary sequence is recoded from the output of the regenerator in order to remove relativity. The output of the CC is the output of a demodulated binary signal, while an additional demodulated signal from the output of the CC, the sequence of clock pulses from the output of the clock frequency allocation unit and the video signal from the PD output are fed to the corresponding inputs of the additionally introduced error detection and correction unit.

EFFECT: increased noise immunity of signal reception.

1 cl, 2 dwg

Description

The invention relates to telecommunications and can be used to receive binary data by the method of relative phase telegraphy.

There is an autocorrelation method for receiving signals of relative phase telegraphy (OFT) in devices for receiving signals with phase shift keying, in accordance with which the received signal is delayed in the delay line for the duration of one signal transmission and is used as a reference voltage for coherent detection of the input signal of the OFT by a phase detector ( PD), after which the video signal from the PD output is fed to the limiter and then to the regenerator, which ensures the registration of a sequence of binary symbols at the limiter output at the moments of clock pulses from the clock synchronization unit as part of the regenerator [1].

However, this method of receiving OFT signals is characterized by insufficient reliability.

Of the known methods of receiving signals of relative phase telegraphy (RFT) in devices for receiving signals with phase shift keying, the closest in essence to the problems being solved and most of the coinciding essential features is the method for comparing polarities, in accordance with which the input signal of RFT is simultaneously fed to the inputs of the reference coherent voltage generator ( FOKN) and a phase detector (PD), in which coherent detection of the input signal is performed using the reference voltage from the FOKN output, the video signal from the PD output is fed to the regenerator, which ensures the registration of a sequence of binary symbols at the moments of clock pulses from the output of the clock frequency selection unit to clock the inputs of the regenerator and the subsequent code converter (KP), in which the binary sequence from the output of the regenerator is re-encoded in order to remove the relativity, and the KP output is the output of the demodulated binary signal [2].

The disadvantages of this method of receiving OFT signals, as well as other similar methods of receiving OFT signals, include the doubling of errors due to the fact that single errors arising at the output of the PD due to the action of interference are doubled at the output of the CP. Moreover, error doubling occurs regardless of whether the received signal contains any redundant service information or only basic binary information that can be encoded during transmission by any redundant correction code.

As redundant service information in communication systems, a cyclic sync signal (DS) can be used, which is introduced into the transmitted information bit stream in the form of a periodic sequence of single sync symbols evenly distributed among information symbols, which can be of two types [3]:

- single-character DS - sync symbol "1", or sync symbol "0", regularly repeated among the main information symbols with a repetition period of sync symbols T _s , determined in the number of k binary symbols (DS), equal to the duration of the cycle or the cycle interval T _c = T _c = k DS;

- DS in the form of a synchro group (SG) uniformly distributed over the cycle, consisting of M single sync symbols, regularly repeated among information symbols with a cycle repetition period T _c = MT _c , where T _c = k is the repetition period of sync symbols in number to DS (for M = 1, this type of DS turns into a single-character DS with a cycle duration T _c = T _c ).

In all the above cases, such a binary signal is similar to a binary signal formed by the code (k, k-1) with minimal redundancy [4], in which the time position and the value of the redundant sync symbol ("1" or "0") in each codeword of to DS is previously known.

The frame sync signal is introduced into the transmitted information bit stream to maintain synchronism in the cycles of the receiving part relative to the transmitting part of the synchronous communication system [3].

In addition, the service address sequence (SAS), which is known (except for the source of the radiogram) to the recipient of the radiogram, can be used as redundant service information in the transmission of short messages (radiograms). [five]. With a uniform distribution of the service symbols of the SAP among the information symbols of the radio message, the transmitted binary sequence according to the type of distribution of the service symbols among the information symbols becomes similar to the binary sequence containing the above-considered cyclic information known upon receipt. In this case, the distributed EPS can be considered as a distributed SG with the number of sync symbols M equal to the number R of the service symbols in the EPS with a repetition period of the EPS service symbols T _c = k DS and with one frame interval of duration T _c = RT _c = Rk. EPS symbols distributed among information symbols can be considered as single sync symbols of one long-term SG or as binary information generated by a code (k, k-1) with minimal redundancy, in which the time position and value of the redundant sync symbol ("1" or "0" ) in each codeword of k DSs is known in advance.

However, the redundant service information contained in the demodulated signal in the form of redundant service sync symbols evenly distributed among the information symbols, the sequence and values of which are previously known upon receipt, is not used to increase the noise immunity of the basic information transmitted by the CFT signals.

The problem to be solved by the present invention - a method for receiving signals of relative phase telegraphy in devices for receiving signals with phase shift keying, is to increase the noise immunity of receiving CFT signals by correcting erroneously received information binary symbols, to determine which excess service information is used, contained in the received signal in in the form of a periodic sequence of single sync symbols evenly distributed among the information symbols.

The solution to the problems posed is achieved by the fact that in the known method of receiving signals of relative phase telegraphy (RFT), in devices for receiving signals with phase shift keying, in accordance with which the input signal of RFT is simultaneously fed to the inputs of the reference coherent voltage generator (PCV) and the phase detector (PD ), in which coherent detection of the input signal is performed using the reference coherent voltage from the output of the FOKN, the video signal from the output of the PD is fed to the regenerator, which ensures the registration of a sequence of binary symbols at the moments of arrival of clock pulses from the output of the clock frequency selection unit to the clock inputs of the regenerator and the subsequent code converter ( CP), in which the binary sequence is re-encoded from the output of the regenerator in order to remove the relativity, and the CP output is the output of the demodulated binary signal, while the additionally demodulated signal from the CP output, the tact sequence output pulses from the output of the clock frequency extraction unit and the video signal from the PD output are fed to the corresponding inputs of the additionally introduced error detection and correction unit (ERC), in which the erroneously received information symbols in the demodulated signal are detected and corrected, for the determination of which redundant service information is used, contained in the demodulated signal in the form of service sync symbols known during reception, regularly repeated among the main information symbols with a repetition period T _c = k determined in the number of k≥3 binary symbols (DS), such a demodulated signal is similar to a binary signal generated by the code (k, k-1) with minimal redundancy, in each codeword of which from to DS, the time position and the value of the redundant sync symbol ("1" or "0") are previously known, while in each codeword the symbols that follow sequentially in time are denoted by conditional serial numbers i = 1,2, ..., k , of which the sync symbol is denoted by the conditional serial number i = 2, in addition, in the corresponding combinations of unrecoded characters registered by the regenerator and coinciding in time with the symbols at the output of the control panel with conditional serial numbers i = 1,2, ..., k, are denoted by conditional serial numbers i ^! = 1 ^! , 2 ^! ,…, K ^! , in this case, if an erroneously received sync symbol is found in any code combination from to DS from the CP output, using the property of the periodicity of sync symbols and information about their values in each code combination from to DS, then this is a consequence of the fact that due to duplication of errors when receiving the OFT signal, one of the two symbols at the output of the regenerator with conditional serial numbers i is distorted ^! = 1 ^! , 2 ^! , and the least reliable symbol is the one that corresponds to the lowest absolute value of the video signal voltage at the PD output during registration, therefore, if the inequality | Z ₁ ^! | <| Z ₂ ^! |, where | Z ₁ ^! | and | Z ₂ ^! | - respectively, the absolute values of the voltage of the video signal at the output of the PD, measured in relative units by any known method at the moments of registration of symbols with conditional serial numbers i ^! = 1 ^! , 2 ^! , then in this codeword the information symbol with the conditional serial number i = 1 is corrected (inverted) from the output of the CP. if the sign of the inequality is reversed when | Z ₂ ^! | <| Z ₁ ^! |, then in this code combination the information symbol with the conditional serial number i = 3 is corrected, while the BOCO output is supplied with the corrected demodulated binary signal delayed relative to the demodulated binary signal at the output of the CP, by the required number of DSs required to carry out the DS correction.

Comparative analysis with the prototype shows that the introduction of essential distinctive features is novelty and allows, as will be shown below, to solve the assigned tasks.

Let us consider the effectiveness of the proposed invention on the example of the functioning of a device for receiving signals of relative phase telegraphy with increased noise immunity, the electrical structural diagram of which is shown in Fig. one.

FIG. 2 shows timing diagrams explaining the operation of the device.

The parameters and the number of components of the device are selected to receive an OFT signal containing a redundant service cyclic sync signal in the form of a sync group (SG) uniformly distributed over the cycle, consisting of M = 3 single sync symbols, regularly repeated among information symbols with a cycle repetition period T _c = 3T _c , where T _c = k = 6 DS is the repetition period of the sync symbols.

In addition, the number L of bits of the analog-to-digital converter (ADC), which determines the accuracy of converting the analog level into digital form and the corresponding number of shift registers in the comparison unit L = 3.

Adjacent bits of shift and storage registers are conventionally separated by dotted lines. For the purpose of clarity and simplification of the representation of electrical connections, the inputs and outputs of the discharges of the shift registers are indicated by the directions of the arrows of the electrical connections.

A device for receiving signals of relative phase telegraphy with increased noise immunity, contains a series-connected coherent detector 1, a regenerator 2 and a code converter (CP) 3, the other input of which is connected to the output of the clock frequency selection unit 4, one input of which is connected to the other output of the coherent detector 1, the other input of which and the other input of the clock frequency selection unit 4 are combined and are the input of the device, as well as the comparison unit 5 and the control unit 6, and the output of the CP 3 is the output of the demodulated binary signal and the first output of the device.

In addition, the device contains an error detection and correction unit 7 (BOCO), the clock input of which is combined with the clock input of the comparison unit 5, another input of the regenerator 2 and the output of the clock frequency selection unit 4, the information input BOCO7 is connected to the output of the CP 3, the other 2M = 6 inputs BOKO7 with conditional serial numbers m ₁ = 1 ₁ , 2 ₁ , 1 ₂ , 2 ₂ , 1 _{3 (M)} , 2 _{3 (M)} , connected to the corresponding 2M = 6 outputs of the control unit 6 with similar conditional serial numbers m ₁ = 1 ₁ , 2 ₁ , 1 ₂ , 2 ₂ , 1 _{3 (M)} , 2 _{3 (M)} , M = 3 of the first inputs of which with serial numbers m = 1,2,3 (M) are connected to the corresponding outputs BOCO 7 with the same serial numbers m = 1,2,3 (M), and the second M = 3 inputs of the control unit 5 with serial numbers m = 1,2,3 (M) are connected to the corresponding outputs of the comparison unit 5 with the same ordinal numbers m = 1,2,3 (M), where M = 3 is the number of single sync symbols in the sync group (SG) of the service cyclic sync signal, evenly distributed over the cycle, as part of the demod signal, regularly repeated among the main information symbols with a cycle repetition period T _c = MT _c = 18, where T _c = k = 6 is the repetition period of sync symbols in the number of k = 6 binary symbols (DS), the signal input of the comparison unit 5 is connected to the output of the coherent detector 1, while BOCO 7 contains the first and second N-bit shift registers 8 ₁ and 8 ₂ , in each of which the number of N = 3 + (M-1) k = 15 bits with serial numbers n = 1,2 , ..., 15 (N), corresponding to the order of sequential advancement of binary information through the bits of each shift register - from the most significant bit, which is the information input of the shift register (for n = 15), to the least significant bit, which is the information output of the shift register (for n = 1 ), the combined clock inputs and the combined information inputs of the shift registers are, respectively, clock and information inputs of BOCO7, as well as M-bit storage register 9 with ordinal numbers of bits m = 1,2,3 (M) corresponding to the sequence order i M = 3 sync symbols in the distributed sync group of the cyclic sync signal, the outputs of which are connected to the first inputs of the corresponding adders modulo two 10 ₁ , 10 ₂ , 10 _{3 (M)} with the same serial numbers m = 1,2,3 (M), with the second inputs of these adders modulo two 10 ₁ , 10 ₂ , 10 _{3 (M)} with serial numbers in the order of their increasing are connected to the outputs of the corresponding bits of the first N-bit shift register 8 ₁ with serial numbers n = 2.8 , 14, also following in the order of their increasing, and the output of each of the M = 3 of these adders modulo two with the corresponding serial number m, which is the corresponding output of BOCO 7 with the same serial number m, is connected through the corresponding NOT element with the corresponding one-bit digital input adder 12, the digital output of which is connected to the digital input of the cyclic synchronization unit (DCS) 13, the output of which is connected to the phasing input of the cyclic pulse generator (DC) 14, the clock input of which is combined with the clock input of the DCS 13 and clock inputs of the N-bit shift registers 8 ₁ and 8 ₂ , and the output of the generator of the DI 14 is connected to the pulse input for rewriting the DS into the bits of the second N-bit shift register 8 ₂ , the information output of which is the output of the corrected demodulated binary signal and the second output of the device, the outputs of the other 2M = 6 bits of the first N-bit shift register 8 ₁ with serial numbers n = 1,3,7,9,13,15 are connected to the first inputs of the corresponding other 2M = 6 adders modulo two 10 ₄ , 10 ₅ , ..., 10 _{9 (3M)} with serial numbers m = 4.5, ..., 9 (3M), the outputs of which are connected to the information inputs of the DS rewriting into the corresponding bits of the second N-bit shift register 8 ₂ with serial numbers n = 1,3,7,9,13,15, while the second inputs of these 2M = 6 adders modulo two 10 ₄ , 10 ₅ , ..., 10 _{9 (3M)} with serial numbers m = 4.5, ..., 9 (3M), following one after another in the order of increasing their ordinal numbers, are the corresponding 2M inputs BOKO7 with conditional th serial numbers m ₁ = 1 ₁ , 2 ₁ , 1 ₂ , 2 ₂ , 1 _{3 (M)} , 2 _{3 (M)} .

=1,2,3(L), причем каждый разрядный выход с соответствующим порядковым номером

, подключен к информационному входу соответствующего N-разрядного регистра сдвига

с таким же порядковым номером

, по структурному построению аналогичному N-разрядным регистрам сдвига 8₁ и 8₂ БОКО7, тактовый вход которого объединен с тактовыми входами других таких же L-1 N-разрядных регистров сдвига, с тактовыми входами узла дискретизации 15 и АЦП 16 и является тактовым входом блока 5 сравнения, а также М=3 узлов сравнения 18₁,18₂,18_3(М) с порядковыми номерами m=1,2,3(М), выходы которых являются соответствующими выходами блока 5 сравнения с такими же порядковыми номерами m=1,2,3(М), при этом каждый узел сравнения 18_m с соответствующим порядковым номером m имеет два идентичных L-разрядных цифровых входа с порядковыми номерами разрядных входов

=1,2,3(L) каждого L-разрядного цифрового входа, причем каждый разрядный вход с соответствующим порядковым номером

первого L-разрядных цифрового входа подключен к выходу разряда с порядковым номером n=l+(m-l)k=l N-разрядного регистра сдвига

с таким же порядковым номером

а каждый разрядный вход с соответствующим порядковым номером

второго L-разрядного цифрового входа этого же узла сравнения 18_m подключен к выходу разряда с порядковым номером n=2+(m-1)k=2 N-разрядного регистра сдвига

с таким же порядковым номером

Comparison unit 5 consists of a series-connected sampling unit 15, the signal input of which is the signal input of the comparison unit 5, and an analog-to-digital converter (ADC) 16, which converts analog levels from the output of the sampling unit to L-bit binary numbers with serial numbers of bit outputs

= 1,2,3 (L), and each bit output with the corresponding serial number

, connected to the information input of the corresponding N-bit shift register

with the same serial number

, structurally similar to the N-bit shift registers 8 ₁ and 8 ₂ BOCO7, the clock input of which is combined with the clock inputs of other similar L-1 N-bit shift registers, with the clock inputs of the sampling node 15 and ADC 16 and is the clock input of the block 5 comparison, as well as M = 3 comparison nodes 18 ₁ , 18 ₂ , 18 _{3 (M)} with serial numbers m = 1,2,3 (M), the outputs of which are the corresponding outputs of the comparison unit 5 with the same serial numbers m = 1,2,3 (M), while each comparison node 18 _m with the corresponding serial number m has two identical L-bit digital inputs with the serial numbers of the bit inputs

= 1,2,3 (L) of each L-bit digital input, with each bit input with a corresponding sequence number

of the first L-bit digital input is connected to the output of the bit with the serial number n = l + (ml) k = l N-bit shift register

with the same serial number

and each bit input with the corresponding serial number

the second L-bit digital input of the same comparison unit 18 _{m is} connected to the output of the bit with the ordinal number n = 2 + (m-1) k = 2 N-bit shift register

with the same serial number

The control unit 6 consists of M = 3 control command generators (FCU) 19 ₁ , 19 ₂ , 19 _{3 (M)} with serial numbers m = 1,2,3 (M), each of which 19 _m with the corresponding order number m consists of from the element NOT 11 ₄ , the output of which is connected to the first input of the first element And 20 ₁ , the second input of which is combined with the second input of the second element And 20 ₂ and is the first input of the FCD, which is one of the first M = 3 inputs of the control unit 6 with the corresponding serial number m, and the first input of the second element And 20 _{2 is} combined with the input of the element NOT 11 ₄ and is the second input of the FCD, which is one of the second M = 3 inputs of the control unit 6 with the corresponding serial number m, and the outputs of the first and second elements And (20 ₁ , 20 ₂ ) of this FKU 19 _m are the first and second outputs of the FKU and the control unit 6 with conditional serial numbers m ₁ = l _m , 2 _m , which together with similar outputs of other M-1 = 2 FKU are corresponding 2M = 6 outputs of the control unit with conditional ordinal numbers m ₁ = l ₁ , 2 ₁ , 1 ₂ , 2 ₂ , 1 _{3 (M)} , 2 _{3 (M)} .

The device works as follows.

The data signal modulated by the method of relative phase telegraphy (OFT) (with a phase difference between adjacent messages of 0 or 180 °) is fed to the coherent detector 1 and block 4 of the clock frequency selection. In coherent detector 1, quasi-coherent detection of the input signal is performed, i.e. the operation of multiplying the input signal by the generated reference coherent voltage, followed by filtering the multiplication result with a low-pass filter. The coherent reference voltage in the coherent detector 1 can be generated from the input signal by any known method.

Thus, the coherent detector 1 can consist of a coherent voltage driver and a phase detector, which is a series-connected multiplier and a low-pass filter. The coherent reference voltage is applied to the input of the block 4 for selecting the clock frequency.

The detected signal from the first output of the coherent detector 1, which is a video signal with a zero average level (since the positive and negative messages are symmetrical about the zero level in the absence of interference voltage at the input of the coherent detector 1), is fed to the input of the regenerator 2 and to the signal input of the comparison unit 5 ... In the regenerator 2, the symbols are registered at the reference points in time specified by the clock frequency allocation unit 4, i. E. if at the moment of arrival of the clock pulse the output voltage of the coherent detector 1 is positive, then the regenerator 2 registers the symbol "1", but if at this moment the voltage of the coherent detector 1 is negative, then the symbol "0" is recorded.

In block 4 allocating the clock frequency, narrow clock pulses are formed, corresponding in time to the least distorted part of the detected messages (usually the middle of the messages). Structurally, the block 4 allocating the clock frequency can be made, for example, of the input converter containing its own correlators, working with a time shift relative to each other, and a closed synchronization device. In this case, the result of comparing the output signals of the correlators is used to match the phase of the oscillator of the closed-loop synchronization device.

From the output of the regenerator 2, the binary symbols are fed to the code converter (KP) 3, where they are re-encoded in order to remove the relativity introduced into the binary sequence of symbols on the transmitting side. The binary stream at the output of CP 3 contains a service cyclic sync signal consisting of M = 3 single sync symbols in a sync group (SG) uniformly distributed over the cycle, periodically repeated among information symbols with a cycle repetition period T _c = T _c M, where T _c = k - the repetition period of sync symbols, defined in the number of k ≥ 3 binary symbols (DS), in this case k = 6. The limiting smallest value k = 3 is explained by the fact that at k = 2 there is an uncertainty in the definition of the least reliable information symbol, which is obvious from the analysis of the timing diagrams shown in Fig. 2 at Т _с = k = 2.

For clarity, FIG. 2a shows a transmitted sequence of binary data containing a cyclic sync signal in the form of an SG uniformly distributed over the cycle, consisting of M = 3 single sync symbols (SG sync symbols are marked with bold arrows), periodically repeated among information symbols with a cycle repetition period T _c = 3T _s , where T _с = k = 6 DS - the period of the synchrosymbol repetition among information symbols in the number of binary symbols. Here, each codeword consists of five information symbols and one redundant sync symbol distributed over the SG cycle from three sync symbols - 110, i.e. the sync symbol repetition period within each cycle and in the total binary data stream is T _c = k = 6 DS. Such a demodulated signal is similar to a binary signal generated by the (k, k-1) code with minimal redundancy, in which the time position and value of the redundant sync symbol in each codeword from to the DS is known upon reception.

FIG. 2b shows the same sequence of binary data, but only after the relative re-coding of symbols, which is necessary for the transfer of information by the OFT method. This sequence of symbols performs phase modulation (0-180 °) of the carrier wave on the transmitting side.

FIG. 2c shows the video signal at the output of the coherent detector 1 (zero average is indicated by a straight line), here also the clock pulses of the block 4 of the clock frequency selection are shown, at the moments of which the symbols are registered by the regenerator 2 (Fig.2e).

In CP 3, the binary sequence from the output of the regenerator 2 is shifted by one clock interval (Fig.2e), after which the symbols of both sequences are compared with each other (for example, in an adder modulo two with an inverse output), as a result, from the output of CP 3 to the first output the device receives a demodulated signal (Fig. 2g), correctly received sync symbols are marked with bold arrows, and distorted symbols - with thin arrows).

In each combination of k following consecutive symbols at the output of the CP, conditional ordinal numbers i = 1,2, ..., k are assigned (Fig. 2g,), of which the conditional ordinal number i = 2 is assigned to a sync symbol. In addition, in the corresponding combinations of non-recoded symbols recorded directly at the output of the PD (Fig.2e) and the corresponding levels at the moments of registration of these symbols, recorded by the sampling node 15 (Fig.2d), coinciding in time with the symbols at the output of the CP with conditional ordinal numbers i = 1,2,…, k, are assigned conditional ordinal numbers i ^! = l ^! , 2 ^! ,…, K ^! ... In this case, if at the output of one of the M = 3 adders modulo two, the symbol "1" appears - a sync symbol failure in the corresponding one of the M combinations of any cycle with a duration of T _c = Mk DS, which means that one of the two symbols with conditional ordinal numbers i ^! = 1 ^! , 2 ^! at the output of the regenerator, while the least reliable is the symbol, which corresponds to the lowest absolute voltage of the PD [6].

If there were no distortions of the received signal, then the video signal at the output of the coherent detector 1 in shape corresponding to the modulating binary sequence on the transmitting side (Fig. 2b) would completely coincide in shape with the modulating sequence. Due to the delay in the communication channel, the video signal in FIG. 2c is shown slightly offset in time from the baseband signal shown in FIG. 2b.

However, due to the action of interference in the communication channel at one of the moments t _{1 of the} registration of the next symbol, the video signal instead of a positive one takes a negative value (Fig. 2c), i.e. at this point in time, the interference voltage at the input of the device acts in antiphase with respect to the signal voltage, while the polarity of the output oscillation of the coherent detector 1 is opposite with respect to if only one signal was received at the input of the device without interference.

Thus, at time t _1, an erroneous registration of the first symbol of one of the k-element combinations of symbols takes place (Fig. 2c, d, e), i.e. instead of the symbol "1", the symbol "0" was adopted, which is indicated by the number 1 (distorted symbols are marked with thin arrows).

At time t _2, an erroneous registration of the second symbol of another k-element combination of unrecoded symbols occurs, i. E. instead of the symbol "0", the symbol "1" was adopted (Fig. 2c, d, e), which is designated by the number 2.

After the relative re-coding of symbols in the code converter 3 (Fig. 2g), single errors occurring at the output of the regenerator 2 (Fig. 2e) are doubled (erroneous symbols are marked with thin arrows).

Thus, if an erroneously received sync symbol is detected in any code combination of k DSs from the output of KP 3, then this is a consequence of the fact that due to doubling of errors when receiving the OFT signal, one of the two symbols at the output of the regenerator with conditional sequence numbers is distorted i ^! = 1 ^! , 2 ^! , and the least reliable is the symbol, which, during registration, corresponds to the lowest absolute value of the video signal voltage at the output of PD 1 [6]. Moreover, if the inequality | Z ₁ ^! | <| Z2 ^! |, where | Z ₁ ^! | and | Z ₂ ^! | - respectively, the absolute values of the voltage of the video signal at the output of the PD, measured in relative units by any known method at the moments of registration of symbols with conditional serial numbers i ^! = 1 ^! , 2 ^! , then in the code combination from the KP output, the information symbol with the conditional serial number i = 1 is corrected (inverted). if the sign of the inequality is reversed when | Z ₂ ^! | <| Z ₁ ^! |, then in this codeword the information symbol with the conditional serial number i = 3 is corrected.

To identify the distorted sync symbols and correct one of the two information symbols adjacent to each distorted sync symbol, the received sequence from the first output of the device is fed to the information input of the error detection and correction unit 7 (BOCO). In this case, BOCO 7 contains the first and second N-bit shift registers 8 ₁ and 8 ₂ , in each of which the number of N = 3 + (M-1) k = 15 bits with ordinal numbers n = 1,2, ..., 15 ( N), corresponding to the order of sequential advancement of binary information through the bits of each shift register - from the most significant bit, which is the information input of the shift register (for n = 15), to the least significant bit, which is the information output of the shift register (for n = 1).

Under the influence of clock pulses (Fig. 2c), the input sequence (Fig. 2g) moves synchronously along the bits of two N-bit shift registers 8 ₁ and 8 ₂ . To detect each sync symbol failure in each distributed SG of M = 3 synchronous symbols to the outputs of the corresponding bits of the first N-bit shift register 8 ₁ , one of the inputs of the corresponding M = 3 adders modulo two (10 ₁ , 10 ₂ , 10 _{3 (M )} ). The other inputs of these adders modulo two are connected to the outputs of the corresponding bits of the M-bit storage register 9 [7], simulating the logic levels ("1", "1", "0") of the sync symbols of the distributed SG.

The outputs of the adders modulo two, which are M outputs of BOCO 7, through the corresponding elements NOT (11 ₁ , l1 ₂ , 11 _{3 (M)} ) are connected to the corresponding one-bit inputs of the digital adder 12 [7], which provides the summation of single responses at its inputs at each shift of discrete information by one bit in the shift register 8 ₁ under the influence of clock pulses - TI. A single response (symbol "1") at any input of the digital adder 12 means that in the corresponding bit of the shift register 8 ₁ and the corresponding clock interval there is a symbol similar to the required sync symbol SG.

With the correct reception of all M = 3 sync symbols of the distributed SG in any cycle (Fig. 2a) and the location of all M sync symbols in the required bits of the shift register 8 ₁ (Fig. 1) in the corresponding clock interval, the result of summation in this clock interval - digit 3 in binary code at the output of digital adder 12. At the same time, at the output of each of M = 3 adders modulo two (10 ₁ , 10 ₂ , 10 _{3 (M)} ), which are the corresponding M = 3 outputs of BOCO 7 , a logic level “0” appears - no failure of the corresponding sync symbol.

From the output of the digital adder 12, the results of the counting of symbols similar to sync symbols in the SG are fed to the input of the cyclic synchronization device (UTS) 13, which determines the _{time position M = 3 cyclically repeating with a period T c} = 18 of the sync symbols SG in the corresponding bits of the N-bit shift register 8 ₁ and generates synchronizing pulses.

Structurally, the UTS 13 can consist, for example, of Q = Mk accumulating adders that count symbols similar to synchrosymbols of the SG for each shift of discrete information by one bit in the shift register 8 ₁ during a given time interval and a decision node that determines the number of the accumulating adder, which received the largest number of responses from the output of the digital adder 12, and forming a synchronizing pulse. The structure of such a UTS is given in [8].

The output of the DCS 13 is connected to the phasing input of the cyclic pulse generator (DC) 14, the clock input of which is combined with the clock inputs of the DCS 13 and N-bit shift registers 8 ₁ and 8 ₂ , and the output of the DC generator 14 is connected to the pulse input for rewriting the DS into the bits of the second N-bit shift register 8 ₂ .

The DI generator generates a DI with a repetition period T _c (Fig.2a, i) and is phased from the DTC in such a way that when each cyclic pulse arrives, M sync symbols SG of each cycle of the received binary signal will be located in the corresponding identical bits of the first and second shift registers 8 ₁ and 8 ₂ with serial numbers n = 2, (2 + 1⋅k), (2 + 2⋅k) = 2, 8, 14. In this case, the first (in time) sync symbol SG (in this case, the symbol "1" ) of each cycle must be located in the bits of the shift registers 8 ₁ and 8 ₂ with the serial number n = 2. The DI generator can be made, for example, based on a binary counter and a decoder.

Outputs of other 2M = 6 bits of the first N-bit shift register 8 ₁ with serial numbers n = 1,3,7,9,13,15 are connected to the first inputs of the corresponding other 2M = 6 adders modulo two 10 ₄ , 10 ₅ , ... , 10 _{9 (3M)} with serial numbers m = 4.5, ..., 9 (3M), the outputs of which are connected to the information inputs for rewriting the DS into the corresponding bits of the second N-bit shift register 8 ₂ with the same serial numbers n = 1, 3,7,9,13,15 digits. In this case, the second inputs of these 2M = 6 adders modulo two 10 ₄ , 10 ₅ , ..., 10 _{9 (3M)} , following each other in the order of increasing their ordinal numbers, are the corresponding 2M LOCO inputs with conditional ordinal numbers m ₁ = 1 ₁ , 2 ₁ , 1 ₂ , 2 ₂ , 1 _{3 (M)} , 2 _(3M) .

Through each pair of adders to module two (10 ₄ , 10 ₅ ; 10 ₆ , 10 ₇ ; 10 ₈ , 10 ₉ ), it is possible to forcibly rewrite DS (binary symbol "1" or "0") from the outputs of the corresponding every two bits of the first register shift 8 ₁ with serial numbers n = 1,3; 7.9; 13,15 into the corresponding bits of the second shift register 8 ₂ with identical ordinal numbers of bits: either without inversion of two symbols, or with inversion of one of the two symbols, at the time of arrival of the cyclic pulse - DI (Fig. 2i). Moreover, if on the second inputs of these adders modulo two 10 ₄ , 10 ₅ , ..., 10 _{9 (3M)} , which are the corresponding 2M inputs of BOCO with conditional serial numbers m ₁ = 1 ₁ , 2 ₁ , l ₂ , 2 ₂ , 1 _{3 (M)} , 2 _{3 (M)} , "zero" control levels (symbols "0") are supplied, which is possible when in the corresponding clock interval at the time of the arrival of the DI from the output of the DI generator 14, all the sync symbols of the corresponding SG are received correctly and at the output of each adder modulo two (10 ₁ , 10 ₂ , 10 ₃ ), and accordingly, a logic level (symbol) "0" will appear on each of the M = 3 BOCO outputs, then DS or logic levels in all bits of the second the shift register 8 ₂ will remain unchanged, since the rewritable logic levels from the bits of the first shift register 8 ₁ coincide with the logic levels of the identical bits of the second shift register 8 ₂ . If, when the DI arrives, the SG sync symbols are received erroneously, and a logic level "0" is received from each of the M = 3 outputs of the comparison unit 5, then the second inputs of the adders modulo two with odd ordinal numbers m = 10 ₅ , 10 ₇ , 10 ₉ log will arrive. level "0", and the second inputs of the adders modulo two with even serial numbers m = 10 ₄ , 10 ₆ , 10 ₈ will receive a log. level "1" from the corresponding inputs BOCO 7 with conditional serial numbers m ₁ = 1 ₁ , 2 ₁ , l ₂ , 2 ₂ , l _{3 (M)} , 2 _{3 (M)} . As a result, in the second N-bit shift register 8 _{2, the} corrected (inverted) will be the information symbols preceding the distorted sync symbols, which are located in the bits with ordinal numbers n = 1,7,13, and the DSs located in other bits of this shift register will remain without change. When changing the output levels of the comparison unit 5 to the opposite - log. "1", the information DSs, following the distorted synchrosymbols, which are located in the digits with ordinal numbers n = 3.9.15 of the second shift register 8 _2, will be corrected (inverted).

As noted above, in order to determine the least reliable symbol adjacent to the distorted sync symbol, it is necessary to compare the absolute values of the video signal amplitudes at the moments when the regenerator registers 2 symbols with conditional serial numbers i ^! = 1 ^! , 2 ^! in an unrecoded sequence (Fig. 2e). The execution of these actions is carried out in the block 5 of the comparison.

In block 5 of comparison from the signal input, the video signal is fed to the signal input of the sampling unit 15, in which the instantaneous values of the video signal are stored at the moments of registering the symbols by the regenerator 2 (Fig.2d, the average zero value of the quantized levels is also indicated by a straight line). Memorizing the instantaneous values of the video signal levels is necessary for reliable operation at the reference points in time of the analog-to-digital converter (ADC) 16. The sampling unit 15 can be made, for example, in the form of an electronic key and an integrating RC-circuit storing the values of instantaneous levels.

ADC 16 at the time of arrival of each clock pulse from block 4 converts the corresponding absolute value of the level of block 15 (Fig.2d) into an L-bit digital form in the form of a code number in a direct code (L is the number of ADC bits, determine the accuracy of converting instantaneous values of analog levels into digital form: the higher the bit depth, the higher the conversion accuracy) and memorizing this number until the next clock pulse arrives. Thus, the code numbers at the output of the ADC 16 represent the absolute values of the levels of the coherent detector 1 (in digital form) at the moments of registering the symbols by the regenerator 2. These absolute levels correspond in time to the recoded symbols at the output of the CP 3.

Since the received binary sequence from the output of CP 3 in BOCO 7 is fed to the information inputs of N-bit shift registers 8 ₁ and 8 ₂ for the simultaneous detection of mistakenly received M≤3 sync symbols in the SG of each cycle and correction of erroneously received information symbols, then the absolute values of the levels coherent detector 1, in time must correspond to the symbols from the output of the KP 3. Therefore, the output of each bit of the ADC 16 is also fed to the information input of the corresponding N-bit shift register (17 ₁ , 17 ₂ , 17 _{3 (L)} ) similar to the shift registers 8 ₁ and 8 ₂ by the number of digits and their ordinal numbers. Since all M SG symbols are analyzed at the same time, as part of the comparison block 5, it is required to have M = 3 comparison nodes 18 ₁ , 18 ₂ , 18 _{3 (M)} , each of which is designed to compare two numbers in a binary code corresponding to the absolute values of the levels voltage of coherent detector 1 when registering symbols with conditional serial numbers i ^! = 1 ^! , 2 ^! (Fig.2e) in an unrecoded codeword of symbols that coincide in time with symbols with conditional ordinal numbers i = 1.2 at the output of CP 3. Taking into account the synchronous advancement of DS sequences along the bits of N-bit shift registers 8 ₁ , 8 ₂ BOCO 7 and 17 ₁ , l7 ₂ , 17 _{3 (L)} of the comparison unit 5, the outputs of the compared bits of the N-bit shift registers 17 ₁ , 17 ₂ , 17 _{3 (L)} of the comparison unit 5 in FIG. 1 by analogy with FIG. 2e are designated by numbers 1 and 2.

With the arrival of each clock pulse in each of the comparison nodes (18 ₁ , 18 ₂ , 18 _{3 (M)} ), a comparison is made of two numbers in a binary code corresponding to the absolute value of the voltage levels of the coherent detector 1 at the moments of registration of two neighboring symbols with conditional serial numbers i = 1 ^! , 2 ^! , which for each of the M code combinations from to DS of each cycle T _{c are} denoted as | Z ^! ₁ | and | Z ^! ₂ |. The corresponding bit DS of the ADC 16 of each cycle are located in bits with serial numbers n = 1,2,7,8,13,14 of each of the shift registers 17 ₁ , 17 ₂ , 17 _{3 (L)} in the clock interval when the DI with output of the shaper DI 14. In this case, each comparison node 18 ₁ , 18 ₂ , 18 _{3 (M)} forms at its output the symbol "0", if the first number | Z ^! ₁ | less than the second number | Z ^! ₂ |, Otherwise, when | Z ^! ₂ | <| Z ^! _l |, a logical level or symbol "1" is formed at the output of the corresponding comparison node.

The outputs of the comparison nodes 18 ₁ , 18 ₂ , 18 _{3 (M)} with M = 3 outputs of the comparison unit 5 are fed to the corresponding second inputs of the control unit 6, in which the incoming control logic levels are fed to the second inputs of the corresponding control command generators (FCU) 19 ₁ , 19 ₂ , 19 _{3 (M)} with serial numbers m = 1,2,3 (M), the first inputs of which are supplied with other control levels from the first inputs of the control unit 6 with the same serial numbers of the inputs.

Consider in more detail the process of correcting erroneously received information symbols in the received sequence of binary symbols in accordance with FIG. 2.

As a result of interference in the communication channel at one of the moments of registration of the next symbol t _{1, the} video signal (Fig. 2c) instead of a positive one takes a negative value, i.e. at this moment in time, the interference voltage at the input of the device acts in antiphase with respect to the signal voltage. Thus, at the moment of time t _{1 there} is an erroneous registration of the symbol with the conditional serial number i ^! = 1 ^! in one of the code combinations of uncoded symbols, i.e. instead of the symbol "1" adopted the symbol "0" (Fig. 2c, d, e).

After the relative re-coding of symbols by the encoder 3 (Fig. 2g), single errors occurring at the output of the regenerator 2 (Fig. 2d) are doubled (erroneous symbols are marked with thin arrows). Referring to FIG. 2a, g, the second from the beginning of the first cycle, a distorted sync symbol with a serial number n = 2 in the distributed SG (HO) follows in the second repetition period of single sync symbols T _2c within the first cycle interval T _c . This second sync symbol is located in the bit with the serial number n = 2 + 1k = 8 of the first and second shift registers 8 ₁ and 8 ₂ BOCO7 in one of the clock intervals, in time coinciding with the arrival of the next cyclic pulse (DI) from the output of the shaper DI 14. Accordingly, at the output of the adder modulo two 10 ₂ BOCO7, the symbol "1" appears (error of the second synchrosymbol in the SG), which is fed to the first input of the FKU 2 of the control unit 6. And this means that in the non-transcoded code combination of symbols (Fig. 2e) either the previous symbol with the conditional serial number i is distorted ^! = 1 ^! , or a symbol with a conditional serial number i ^! = 2 ^! , coinciding in time with the distorted sync symbol.

In the second comparison node 18 ₂ of the comparison unit 5, a comparison of two absolute values of the output voltage of the coherent detector 1 - | Z ^! _l | and | Z ^! ₂ |. Referring to FIG. 2d at the moment t _{1 the} symbol with the conditional serial number i is registered ^! = l ^! corresponding to the level | Z ^! ₁ |, while | Z ^! ₁ | <| Z ^! ₂ |, i.e. the least reliable is the symbol with the conditional ordinal i ^! = 1 ^! ... In this case, the output node comparison February ₁₈ a comparison result appears - the symbol "0", which is supplied to the second input of PKU ₂ With simultaneous admission to the first "1" input of PKU ₂ symbols output from the modulo adder two 10 _2, and the second input FKU2 - the symbol "0" from the control unit 6, at the second output of FKU ₂ of the control unit 6, the symbol "0" will appear, which goes to the second input of the adder modulo two 10 ₇ BOCO 7, and at the first output of FKU2 - the symbol "1" , which is fed to the second input of the adder modulo two 10 ₆ BOCO 7 and provides the passage of the DS from the output of the discharge with the ordinal number n = 7 of the first shift register 8 ₁ to the output of the adder modulo two 10 ₆ with inversion. At the same time, the opposite (inverse) symbol with respect to the symbol stored in this bit in the considered clock interval will arrive at the information input of rewriting the DS into the bit with the serial number n = 1 + 1k = 7 of the second shift register 8 ₂ from the output of the adder modulo two 10 ₆ ... Accordingly, the receipt of DI at input DS rewriting pulse discharges in the second shift register _{2 August} happen correcting erroneously received information symbol stored in the discharge of the second shift register ₈ February.

At time t ₂ , symbol 2 is registered ^! (Fig. 2e), which corresponds to the level | Z ^! ₂ | from the output of the coherent detector 1. In accordance with FIG. 2a, g, a distorted sync symbol with a conditional serial number i ^! = 2 ^! in the SG follows in the third period T _3c within the same cycle interval T _c . This third sync symbol is located in the bit with the serial number n = 14 of the first and second shift registers 8 ₁ and 8 ₂ BOCO7. Accordingly, at the output of the adder modulo two 10 ₃ BOCO7, the symbol "1" (error of the third synchrosymbol in the SG) will appear, which is fed to the first input of the FKU ₃ of the control unit 6.

In block 5 of comparison in the third node of comparison 18 ₃ is a comparison of two absolute values of the level of the coherent detector 1- | Z ^! _l | and | Z ^! ₂ |. In this case, in accordance with FIG. 2d after the moment of time t _{2 the} inequality | Z ^! ₂ | <| Z ^! ₁ |, i.e. the least reliable is the symbol with the conditional ordinal i ^! = 2 ^! ... Accordingly, at the output of the comparison unit 18 _{3, the} symbol "1" will appear, which is fed to the second input of the FKU ₃ . As a result, at the second output of the FKU ₃ of the comparison unit 5, the symbol "1" will appear, which is fed to the second input of the adder modulo two 10 ₉ BOCO7, and at the first output of the FKU ₃ - the symbol "0", which is fed to the second input of the adder modulo two 10 ₈ SIDE 7. In this case, the opposite (inverse) symbol with respect to the symbol stored in this bit will arrive at the information input of rewriting the DS into the bit with the serial number n = 15 of the shift register 8 ₂ from the output of the adder modulo two 10 _9. In this case, the information symbol stored in the bit with the ordinal number n = 13 of the second shift register 8 ₂ BOCO7 remains unchanged.

The corrected binary sequence (Fig. 2h) is removed from the information output of the second N-bit shift register 8 ₂ (Out. 2).

If the received binary sequence does not contain a cyclic sync signal in the form of a sync group of M sync symbols uniformly distributed over the cycle, periodically repeated among information symbols, then the binary information is removed as in any other known device for receiving OFT signals from the output of the code converter 3 (Out. 1).

It should be noted that the proposed in FIG. 1, the electrical structural circuit is universal and realizable for any values of integers characterizing the parameters M, L, k, including when M = 1, i.e., when the cyclic sync signal is one-symbol i.e. T _c = T _c DS. When M = 1, the structure of the proposed device (Fig. 1) is greatly simplified: N-bit shift registers 8 ₁ and 8 ₂ must be three-bit - N = 3 + (M-1) k = 3. The same three-bit shift registers 17 ₁ ... 17 _L will be required in the comparison unit 5, in which only one comparison unit 18 and one FCU in the control unit 6 should be used.

Thus, in the proposed device, due to the inversion of erroneously received information symbols, an increased noise immunity of reception is realized.

To assess how the reliability of receiving binary information increases when using error correction, it is necessary to compare the error probabilities without correction and with correction of erroneous symbols.

Let the transmitted binary data signal contain single sync symbols, periodically repeating every k-1 symbols of the main information, i.e. formally, binary information is transmitted by the code (k, k-1). In each received codeword (at the output of the control panel), the symbols following sequentially in time will be denoted by the conditional serial numbers i = 1,2,3 ,, ..., k, and by the conditional serial number i = 3, for the convenience of further presentation, we will denote a sync symbol. In addition, in the corresponding combinations of non-transcoded symbols registered by the regenerator, coinciding in time with the symbols at the output of the control panel with conditional serial numbers i = 1,2, ..., k, we denote by conditional serial numbers i ^! = l ^! , 2 ^! ,…, K ^! ...

Let us first determine the probability that the symbol with the conditional serial number i = 2 (preceding the distorted synchrosymbol) in the k-bit combination of symbols at the output of the CP will be correctly corrected with the known value of the probability of erroneous registration of the symbol Р _ФТ at the output of the PD with coherent detection. Obviously, the correct correction of the symbol with the conditional sequence number i = 2 will be performed if the symbol with the conditional sequence number i is distorted in the corresponding combination of unrecoded symbols ^! = 2 ^! , and two adjacent symbols (1 ^! and 3 ^! ) are received correctly, the rest of the symbols of this combination can be distorted in an arbitrary way. The probability of such an event will be equal to

Similarly, you can determine the probability that the symbol with the conditional serial number i = 4 (following the distorted sync symbol) will be correctly corrected. In this case, the symbol with the conditional ordinal number i ^! = 3 ^! should be garbled, and characters 2 ^! and 4 ^! taken correctly. The probability of this event is determined by expression (1). Since the events under consideration are incompatible, the probability that if the sync symbol fails, one of the two information symbols will be correctly corrected, will be equal to

Let us now determine the probability of a false correction of one of the information symbols adjacent to the distorted sync symbol. False correction of a symbol with a conditional sequence number i = 2 can occur if the corresponding combination of uncoded symbols contains symbols with conditional sequence numbers i ^! = 1 ^! , 2 ^! distorted, and the character 3 ^! received correctly, while the rest of the symbols of this combination can be distorted in an arbitrary way. The probability of such an event is

Obviously, the probability of a false correction of a symbol with a conditional ordinal number i = 4 will also be determined by expression (3), and the probability that if a sync symbol fails, a false correction of one of the two information symbols will be equal to

If the correction of the distorted symbols is not performed and l distorted information symbols are recorded during the reception of R k-bit combinations (sync symbols are not taken into account, since they are excluded in the future), then with a sufficiently large R the probability of a signal element error will be equal to [9]

When using the correction of erroneous symbols, the mathematical expectation of the number of correctly corrected information symbols during the reception of R combinations will be written in the form [9]

Similarly, you can determine the mathematical expectation of the number of distorted information symbols due to false correction during the reception of R combinations

Taking into account formulas (5), (6), and (7), the desired error probability when using the correction of erroneous symbols can be determined in the form

The ratios that estimate the noise immunity of FT and TFT in a channel without fading under fluctuation noise are known [4]:

- функция Крампа,Where

- Crump function,

h ² - the ratio of the signal energy to the specific power of the noise. Substituting (9) and (10) into (8), we find the error probability in the absence of signal fading

необходимо в соотношении (11) заменить h на μh₀/μ₀ (

- среднее квадратичное значение коэффициента передачи сигнала μ, h₀ - математическое ожидание величины h) и усреднить это выражение по всем возможным значениям величины μ, имеющей плотность вероятности W(μ) [4]:To determine the probability of error under conditions of slow signal fading

it is necessary in relation (11) to replace h by μh ₀ / μ ₀ (

is the root-mean-square value of the signal transmission coefficient μ, h ₀ is the mathematical expectation of the value h) and to average this expression over all possible values of the quantity μ, which has a probability density W (μ) [4]:

Let us calculate the integral (12) for the case when the probability density of the quantity μ is distributed according to the Rayleigh law [4]

For this, we represent (12) in the form

Where

Taking into account (13), expressions (15) and (16) will be written in the form [4]

Determination of the quantity B by formula (17) in this case is reduced to calculating an integral of the form

Integrating (20) by parts, we find

и вводя обозначение

, получимChanging the variable under the integral sign by the formula

and introducing the notation

, we get

Where

, получимDifferentiating I ₁ (k) with respect to the parameter

, we get

from where

=0, что дает

Подставляя (24) в (22) и учитывая, что

получимThe constant of integration is determined by substituting in (23) and (24)

= 0, which gives

Substituting (24) into (22) and taking into account that

get

Taking into account (18), (19), (26), expression (14) takes the form

- вероятность ошибки для системы с ОФТ при когерентном приеме и релеевских замираниях. Используя (27) определим выигрыш по вероятности ошибки в канале с релеевскими замираниями за счет корректирования ошибок в следующем видеWhere

- the probability of error for a system with OFT with coherent reception and Rayleigh fading. Using (27), we determine the gain in error probability in a channel with Rayleigh fading due to error correction in the following form

Below is a graph for calculating the value of ε by formula (28) at k ₁ = 4. k ₂ = 6. k ₃ = 16 (curves 1, 2, 3, respectively).

The graph of the calculation of the winnings by the probability of an error due to the correction of erroneously received information symbols

Conclusion

It can be seen from the graph that the gain ε in terms of the error probability due to the correction of erroneously received information symbols increases with a decrease in the repetition period of the sync symbols T _c = k DS, i.e. implementation of the proposed method for receiving UFT signals containing single service sync symbols, periodically repeating among the main information symbols, makes it possible to increase the noise immunity of receiving basic information, both when operating in a channel with constant parameters and in a channel with variable parameters.

Information sources

1. N.A. Sartasov, V.M. Edvabny, V.V. Gribin Shortwave trunk radio receivers. M .: Communication. 1971.288 s.

2. Nazarov V.I. Reception of signals of relative phase telegraphy with a rotating phase. - "Electrosvyaz", 1964, No. 11, p. nine.

3. Koltunov M.N., Konovalov G.V., Langurov Z.I. Cycle synchronization in digital communication systems. - M .: Communication, 1980. - 152 p.

4. Fink L.M. The theory of transmission of discrete messages. M .: Soviet radio. 1970.728 s.

5. Automated radio communication with ships / Ed. K.A. Semenov. - L .: Shipbuilding, 1989 (Library of ship communications engineer). - 336 p.

6. Khvorostenko N. P. Statistical theory of demodulation of discrete signals. - M .: Communication, 1968 .-- 335 p.

7. Soloviev G.N. Computer arithmetic devices. - M .: Energy, 1978 .-- 176.

8.A.S. USSR No. 1138954. Cyclic synchronization device / B.G. Shadrin - 1985.

9. Wentzel E.S. Probability theory. - Moscow: Nauka, 1969 .-- 576 p.

Claims (1)

A method for receiving signals of relative phase telegraphy (RFT) in devices for receiving signals with phase shift keying, in accordance with which the input signal of RFT is simultaneously fed to the inputs of a reference coherent voltage generator (PCV) and a phase detector (PD), in which coherent detection of the input signal is performed with using the reference coherent voltage from the FOKN output, the video signal from the FD output is fed to the regenerator, which ensures the registration of a sequence of binary symbols at the moments of clock pulses from the output of the clock frequency selection unit to the clock inputs of the regenerator and the subsequent code converter (CP), in which the binary sequence is re-encoded with the output of the regenerator in order to remove the relativity, and the output of the CP is the output of the demodulated binary signal, characterized in that the demodulated signal from the output of the CP, the sequence of clock pulses from the output of the clock frequency and video extraction unit the signal from the output of the PD is fed to the corresponding inputs of the additionally introduced error detection and correction unit (BOCO), in which the erroneously received information symbols in the demodulated signal are detected and corrected, to determine which they use the redundant service information contained in the demodulated signal in the form of known at reception service sync symbols, regularly repeated among the main information symbols with a repetition period of sync symbols T _c = k, determined in the number of k≥3 binary symbols (DS), such a demodulated signal is similar to a binary signal generated by the code (k, k-1) with minimal redundancy, in each codeword of which of k DS, the time position and the value of the redundant synchrosymbol ("1" or "0") are previously known, while in each codeword the symbols that follow sequentially in time are denoted by conditional serial numbers i = 1, 2, ... , k, of which the conditional serial number i = 2 mean a synchrosymbol, in addition, in the corresponding combinations of unrecoded symbols registered by the regenerator and coinciding in time with the symbols at the output of the control panel with conditional serial numbers i = 1, 2, ..., k, are denoted by conditional serial numbers i ^! = l ^! , 2 ^! ,…, K ^! , in this case, if an erroneously received sync symbol is found in any code combination of k DS from the CP output, using the property of periodicity of sync symbols and information about their values in each code combination of k DS, then this is a consequence of the fact that due to doubling errors when receiving the OFT signal, one of the two symbols at the output of the regenerator with conditional serial numbers i ^{! =} 1 is ^distorted! , 2 ^! , and the least reliable symbol is the one that corresponds to the lowest absolute value of the video signal voltage at the PD output during registration, therefore, if the inequality | Z ₁ ^! | <| Z ₂ ^! |, where | Z ₁ ^! | and | Z ₂ ^! | - respectively, the absolute values of the voltage of the video signal at the output of the PD, measured in relative units by any known method at the moments of registration of symbols with conditional serial numbers i ^! = 1 ^! , 2 ^! , then in this codeword from the KP output the information symbol with the conditional serial number i = 1 is corrected (inverted) if the inequality sign is reversed when | Z ₂ ^! | <| Z ₁ ^! |, then in this code combination the information symbol with the conditional serial number i = 3 is corrected, while the BOCO output is supplied with the corrected demodulated binary signal delayed relative to the demodulated binary signal at the output of the CP, by the required number of DSs required to carry out the DS correction.

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