RU2109405C1 - Error detecting and correcting device - Google Patents

Abstract

FIELD: radio engineering; radio communications; receiving digital messages in digital-message separate-transmission mobile-communication burst-error radio links. SUBSTANCE: during separate transmission with digital addition of message encoded by simple code with parity check, error is detected by counting odd number of ones in digital message provided by decoding unit 5 and by adding in modulo two message signals arriving from outputs of computing units 1 of separate reception circuits with aid of adder 4 to locate error and correct it in second shift register 7 by inverting erroneous data bit in received digital message. EFFECT: improved noise immunity in receiving digital signals using parity check coding in two receiving channels. 8 dwg

Description

 The invention relates to radio engineering, and in particular to radio communication technology, and can be used as a device for processing discrete messages in packet radio networks of mobile communications with diversity reception.

 A known radio communication system (ed. St. USSR N 1688423, 1991), the functional diagram of which contains an encoder, two decoders, a modulator, two D-flip-flops, a transmitter, a high-frequency antenna switch, a receiving and transmitting antenna, the first and second receivers, RS-trigger and a linear addition unit.

 The specified technical solution, while maintaining a given amount of information transmitted, reduces energy costs. However, in the case of unsteady radio channel caused by fluctuations in the medium of propagation of radio waves, the known functional diagram is not able to detect and evaporate errors in transmitted messages.

 The closest technical solution to the claimed one is a device (Andronov I.S. et al. Discrete message transmission on parallel channels. - Sov.radio, 1971), which implements a method of discrete addition with diversity reception and contains a decoding device in each channel, the inputs of which are connected with corresponding antenna devices, and their outputs are connected to the inputs of the addition unit, from the output of which the received discrete message is removed. Decisive devices of each channel bring the solution to the determination of the probabilistic transmitted symbol received on this channel. The final decision is made on the basis of the addition of discrete message symbols from the outputs of the solvers of single reception in the channels.

 However, the device has a drawback. The diversity reception of discrete messages is carried out on an odd number of branches, i.e. the implementation of such a technical solution requires the use of three to five identical receive channels and the corresponding number of equipment, which complicates its implementation and operation. In addition, the device does not provide detection and correction of single errors in discrete messages, which reduces the noise immunity of the radio as a whole.

 The purpose of the invention is the development of a device for detecting and correcting errors, which improves the noise immunity of receiving discrete messages encoded by a code with parity when using two reception channels.

 This goal is achieved by the fact that in the known device for receiving discrete messages containing the first and second decision nodes, the inputs of which are connected to the corresponding antenna devices, and the outputs of the first and second decision nodes are connected to the corresponding inputs of the addition unit, additionally introduced, an adder modulo two, decoding the node, the first and second shift registers, N-elements And and the clock sequence generator. The outputs of the first and second decision nodes are connected to the corresponding inputs of the adder modulo two, the output of the addition unit is connected to the input of the decoding node and to the first input of the second shift register. The modulator two output of the adder is connected to the input of the first shift register, the outputs of the bits of which are connected to the first inputs of the corresponding elements And, the second inputs of which are connected to each other and to the output of the decoding unit, and the outputs of the elements AND are connected to the corresponding bits of the second shift register. The output of the second shift register is the output of the error detection and correction device. The output of the generator of the clock sequence is connected, respectively, to the clock inputs of the decoding node, the first and second shift registers.

 With such a combination of essential features, the proposed device, along with the discrete addition of signals encoded by the code (n, n-1) with a parity check, simultaneously detects a single error, revealing an odd number of “1” in a discrete message, and corrects it by determining the location of the error by the method comparing incoming messages from the outputs of the decision branches of the diversity reception.

 In FIG. 1 shows a block diagram of the inventive device; in FIG. 2 is a block diagram of a decision node; in FIG. 3 is a block diagram of a decoding unit; in FIG. 4 is a block diagram of a first shift register; in FIG. 5 is a block diagram of a second shift register; in FIG. 6 is a block diagram of a clock sequence generator; in FIG. 7 is a timing diagram explaining the principle of operation of the inventive device; in FIG. 8 - calculation results of noise immunity of receiving discrete messages.

 The device for receiving discrete messages (Fig. 1) contains the first 1.1 and second 1.2 decision nodes (RU), antenna devices (AU) 2, an addition unit (BS) 3, an adder modulo two 4 (SMD), a decoding node (DU) 5 , the first 6 and second 7 shift registers (PC), N-elements And8, a clock sequence generator 10 (GPS) and the output 9 of the device for detecting and correcting errors. AC 2 are connected to the corresponding inputs of RU 1.1 and 1.2, the outputs of which are connected respectively to the inputs of BS 3 and to the inputs of the SMD 4. The output of BS 3 is connected to the input of the remote control 5 and the first input of the second PC 7. The output of the SMD 4 is connected to the input of the first PC 6, the outputs of which are connected to the first inputs of the corresponding elements And 8, and the second inputs of the N-elements And 8 are interconnected and connected to the output of the DC 5. The outputs of the elements And 8 are connected to the corresponding second inputs of the second PC 7, the output of which is the output 9 of the detection and correction device mistakes. The GPS output 10 is connected to the sync inputs of the remote control 5, the first PC 6 and the second PC 7, respectively.

 The decision nodes 1.1 and 1.2 are a well-known single-reception scheme and can be implemented, for example, in the form of cascade-coupled matched filter 1.1 and a linear detector 1.2 (Fig. 2) (Andronov I.S. et al. Transfer of discrete messages via parallel channels. - M .: Sov. Radio, 1971, p. 356., Fig. 7.9). The indicated source depicts a circuit with N-branches diversity. For the claimed device as RU 1, one branch of a single reception from this circuit is sufficient.

 The addition unit 3 performs discrete addition of message signals. Therefore, in the proposed device BS 3 can be performed according to the well-known logical addition scheme "OR" (Potemkin IS Functional units of digital automation. - Energoatomizdat, 1988, p. 15). At the output of the addition unit there will be a symbol of a discrete message if at least one of the outputs of RU 1.1 and 1.2 a decision has been made about the transmitted symbol of the discrete message received on this branch of reception.

 ДУ 5 is a well-known decoding unit (Information Transmission Technique in Automated Control Systems / Edited by N.I. Ivanov. - L .: YOU 1976, p. 187) and contains (Fig. 3) an n-bit shift register 5.1, which implements converting a parallel input code to a serial one, and n adders according to mod 2 5.2 (ibid., pp. 191-193), the output of which will generate an enable signal if an odd number of "1" is detected in the total discrete message at the output of BS 3. When this multi-input adder mod 2 can be built, for example, peers further scheme cm. Potemkin IS Functional units of digital automation p. 74, fig. 2.12).

 The first shift register 6 is designed to read and store information coming from the output of the adder modulo two 3.

 The circuit of the first PC that implements such a function in the claimed device is known and described (see Potemkin IS Functional units of digital automation, p. 277 of Fig. 10.1). Considering the interconnections with other elements, the circuit of the first PC 6 takes the form shown in FIG. 4.

The circuit of the first PC 6 includes N cascade-connected cells 6.1 ₁ , ..., 6.1 _i ,. . . , 6.1 _n , where N = {1, ... i, ... n}, and each cell contains a D-flip-flop 6.01, on all the combined C-inputs of which the clock sequence from the GPS output 10 is supplied. The second outputs of each cell are the subsequent input, as well as the first outputs that are connected to the corresponding first inputs of the N-elements I.

 The second shift register 7 is designed to correct an erroneously received character in the DS by inverting the logical state of the cell of the corresponding position to the opposite by the signal from the output of a certain place of the first PC 6 and by the resolution signal from the remote control 5 that detects this error.

 The scheme of the second PC 7, which implements such a function in the claimed device is known Ilyin V.A. Remote control and telemetry. - M .: Energoatomizdat, 1982, p. 386, fig. 9.18). Taking into account interconnections with other elements, the circuit of the second PC 7 takes the form shown in FIG. 5.

The circuit of the second PC 7 includes N cascade connected cells, 7.1 ₁ , ..., 7.1 _i ,. . .7.1 _n , where N = {1, ... i, .. n}, the first 7.035 and second 7.036 elements are N, the element is NOT 7.037 (Fig. 5, a). The output of the SMD 3 is connected to the first input of the first element And 7.035 and through the element NOT 7.037 to the first input of the second element And 7.036, the second inputs of which are connected to the GPS 10. Each i-cell of PC 7 (Fig. 5, b) is the same and contains RS -trigger 7.01, the first 7.021 and the second 7.022 delay elements (33), the first 7.031, the second 7.032, the third 7.033 and the fourth 7.034 elements I. The direct and inverse inputs of the ith cell through the first 7.021 33 and second 7.022 33 are connected respectively to direct 7.011 and inverse 7.012 inputs of the RS-flip-flop 7.01, on line 7.011 and inverse 7.012 the inputs of which are additionally connected the outputs of the third 7.033 and the fourth 7.034 elements of I. respectively. The direct output of the RS-flip-flop 7.01 is connected to the second inputs of the first 7.031 and the fourth 7.034 of the I-elements, and the inverse output of the RS-flip-flop 7.01 is connected to the second inputs of the second 7.032 and the third 7.033 of I. Both 7.031 and 7.032 are connected to the GPS output 10, and the first inputs of the third 7.033 and fourth 7.034 elements And are the i-th input of the second PC 7. The outputs of the first 7.031 and second 7.032 elements And are the outputs of the i-th cell and are connected to the corresponding inputs of the next ( i + 1) -th cell.

 GPS 10 (Fig. 6) is also a well-known circuit (I. Potemkin Functional units of digital automation, p. 273, Fig. 9.11a). The generator generates a single packet of clock pulses containing a predetermined number of pulses, cut from a continuous sequence C1, arriving at the same transmission rate or repetition rate as a discrete message, according to the START signal at the output of the BATCH.

GPS 10 contains an N-bit counter 10.2 (where N = 1, ..., i, ..., n) and an AND 10.1 element. At the first input of the element And 10.1 receives a sequence of pulses with a repetition rate equal to the transmission rate of discrete messages. The start of GPS 10 is carried out by the start signal of the end of the synchronization cycle with the received discrete message, which is connected to the R-input of the counter 10.2. The counter transfer CR-output of counter 10.2 is the second inverse input of AND 10.1 element, the output of which is connected to the summing input “1” of counter 10.2 and from which the output sequence of clock pulses of length n is taken, where n is the number of pulses in the packet equal to the bit depth of the discrete message
Adder 4 is a well-known functionally complete node that implements logical addition in mod 2. Such a scheme is known (I. Potemkin. Functional units of digital automation, p. 33, Fig. 1.10).

 The inventive device operates as follows.

 We believe that the transmission rate of the discrete message at the receiving end is known, and the length of the received discrete message is always the same and equal to n. The phase of entering synchronism before the start of the reception of the discrete message was carried out and the START signal was issued to start the generator of the synchronization pulse sequence 10. The discrete message was received at the AC 2 separated in space (Fig. 7, a and b) in order to de-correlate random fluctuations of the transmission coefficient of the medium in two paths receiving and ensuring the independence of errors at the outputs of RU 1.1 and 1.2. After RU 1.1 and 1.2 of each channel brings to the determination of the probabilistic transmitted symbol received on this branch (Fig. 7, c and d), addition (Fig. 7, f) in BC 3 and summation modulo two (Fig. 7 , e) a discrete message in the DMD 4. The latter determines the place of error in the received DS by the method of logical addition modulo two, followed by recording the received BS in the first RS 6.

 Recording a discrete message in PC 6 is as follows. From the GPS 10 output, n clock pulses are sequentially fed to the PC 6 clock input. When the first clock pulse arrives at the combined C-inputs of the D-flip-flops 6.01, the last one opens to record the state of its youngest neighbor (the first D-flip-flop 6.01 accepts the state of the bit of the discrete message coming from the input of the PC 6). Thus, information on the clock signals will be recorded in PC 6 until the completion of the discrete message reception cycle. The total signal from the output of BS 3 simultaneously arrives at the first input of the second PC 7 and at the input of the remote control 5, which detects an error in the DS by counting an odd number of logical "1" in the total DS.

 Record the total DS in RS 7 as follows. DS from the output of BS 3 is fed to the first input of RS 7. It is known that the RS-trigger changes its state when a signal corresponding to the level of a logical unit arrives at one of the inputs. Therefore, the input DS through the first input of the AND element 7.035 and by the enabling clock signal supplied to the second input of the same And element, will translate the RS-flip-flop 7.01 into a single state if the next bit of the input information corresponds to logical "1". If the next bit of the input information corresponds to a logical "0", then inverting in the element NOT 7.037 and passing through the first input of the element AND 7.036 by the enable clock received at the second input of the same element And, the RS-flip-flop 7.01 will go to zero. Thus, with the arrival of the next ith sync pulse, where IE {1,. .., n}, each RS-flip-flop 7.01 will accept the state of its youngest neighbor except the first, which will take on the state corresponding to the bit of the input DS.

 At the end of the DS reception cycle and the detection of an error at the output of the remote control 5 (suppose that the second position of the DS is received with an error), an enable signal is generated (Fig. 7, k), which will go to the first inputs of the N-elements And 8. Correction of the mistakenly received DS symbol is carried out by inverting the logical state of the cell corresponding to the position (place) in the second PC 7, to the opposite by the signal from the output of determining the location of the error of the first PC 6, and the resolving signal from the remote control 5 that detects this error.

Suppose that when receiving a DS in the second position, a mistake is made - "1" is accepted (Fig. 7, c). Then, after the addition of discrete messages from two branches, the SMD 4 will produce a sequence of pulses with "0" in all positions except the second one, where there will be "1", which determines the position of the error (bit is received incorrectly). In RS 7, the error correction process in the DS is as follows. We believe that the second bit in the DS is mistaken. Then, in the total signal received in SMD 4, in the second position there will be a signal corresponding to the logical "1", which will be received at the first input of the second element And ₂ . At the same time, an error correction signal in the form of a pulse corresponding to a logical "1" will be generated at the output of the remote control 5, which will go to the combined second inputs of the N-elements I. With the arrival of such signals at both inputs of the second element And _{2, the} error correction signal will be generated at the output the received bit of information DS. From the output of the second element And ₂ to the second input of the second cell of the PC 7.1 ₂ will receive a signal - logical "1". Next, the signal is supplied to the first inputs of the fourth elements And 7.034 and the third elements And 7.033. The logical state of the RS-flip-flop 7.01 in the second cell is equal to "1", since the DS summed in BS 3 will be written as "11001110" (Fig. 7, f), so the signal from the output of the second element And ₂ will pass through the fourth element And 7.034, since a logical "1" will be present at its second input. Therefore, the RS-flip-flop 7.01 will be brought to the zero state.

 Upon completion of the reception of the discrete message and determining the position of the error by the resolving pulse (Fig. 7, k) received from the output of the remote control 5 to the first inputs of the N-elements And 8, a single pulse of the second position will be transferred from the first PC 6 through the second element And 8 to the second cell of the second PC 7, where the error will be corrected by inverting the state of the second cell to the opposite (in this case, “0”). Thus, at the output 9 of the error detection and correction device, a discrete message will be generated (Fig. 7, m) without errors.

 Determine the probability of error when receiving DS proposed device.

Расчеты, проведенные на ПЭВМ, позволяют сделать вывод, что предлагаемое устройство обеспечивает более высокую помехоустойчивость чем устройство, реализующее способ дискретного сложения, а именно для одинаковых отношений сигнал/помеха h $\genfrac{}{}{0ex}{}{\text{2}}{\text{0}}$ предлагаемое устройство обеспечивает большую вероятность правильного приема чем устройство-прототип при приеме ДС длиной n, о чем свидетельствуют данные таблицы и графики вероятностных характеристик, приведенные на фиг. 8.It is known that the probability of a DS error of length n P $\genfrac{}{}{0ex}{}{\text{n}}{\text{osh}}$ is defined as the probability difference of a correctly received DS of length n P $\genfrac{}{}{0ex}{}{\text{n}}{\text{etc}}$ and probabilities of single errors P $\genfrac{}{}{0ex}{}{\text{1}}{\text{osh}}$ (Berezyuk N.S. Coding of information (2nd codes). - Kharkov, Higher School, 1978)
P $\genfrac{}{}{0ex}{}{\text{n}}{\text{osh}}$ = 1- (1-P _e ) ⁿ -C $\genfrac{}{}{0ex}{}{\text{1}}{\text{<figure-callout id="1" label="n P" filenames="00000005.png" state="{{state}}">n </figure-callout>}}$ P $\genfrac{}{}{0ex}{}{\text{1}}{\text{uh}}$ (1-P _e ) ^n-1 , (1)
Where
P _e - the probability of an error in receiving a signal element with linear addition
P _e = 3.24 / h ⁴ . (2)
For comparison, we determine the probability of error in a discrete addition device with the number of channels equal to N (Andronov I.S. et al. Transmission of discrete messages on parallel channels. - Sov. Radio, 1971, p. 360.)

Calculations performed on a PC allow us to conclude that the proposed device provides higher noise immunity than a device that implements the method of discrete addition, namely, for the same signal to noise ratio h $\genfrac{}{}{0ex}{}{\text{2}}{\text{0}}$ the proposed device provides a greater probability of correct reception than the prototype device when receiving a DS of length n, as evidenced by the data in the table and graphs of probability characteristics shown in FIG. eight.

 Thus, the use of this device for detecting and correcting errors can improve the noise immunity of receiving discrete messages by correcting single errors when encoding with a simple code (n, n-1), and also simplify the technical implementation and operation of the device as a whole, reducing the number of reception branches to two.

Claims (1)

 A device for detecting and correcting errors, containing the first and second decision nodes, the inputs of which are connected to the corresponding antenna devices, and the outputs to the corresponding inputs of the addition unit, characterized in that an adder modulo two, a decoding node, first and second registers are additionally introduced into it the shift, N elements And and the clock sequence generator, the outputs of the first and second decision nodes are connected to the corresponding inputs of the adder modulo two, the output of the addition unit to the input of the decoding node and to the first input of the second shift register, the adder output modulo two - to the input of the first shift register, the discharge outputs of which are connected to the first inputs of the corresponding elements And, the second inputs of which are connected to each other and to the output of the decoding unit, and the outputs of the elements And are connected to the corresponding the bits of the second shift register, the output of which is the output of the device, the output of the clock sequence generator is connected respectively to the clock inputs of the decoding unit, the first and second shift registers .

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