RU2344544C2 - Method of discrete information transfer - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: in method of discrete information transfer on transmitting side at every cycle initial binary symbols with application of three channels are transformed into three-digit combinations, which carry information on criterion of current binary symbol in block of zeros or block of units (criterion of unit, zero or symbol repetition in block), zeros in combination define channels locked in this cycle; at every cycle in unlocked channel carrying oscillation is modulated, for every channel modulation parameters differ from each other by value; on receiving side signal is demodulated, and at every cycle transmitted combination of binary symbols is restored; permitted combinations of ternary code are formed, elements of which are elements from Galois field GF(3); if errors are detected in combination, symbol of ternary code current symbol erasure is generated, if there is no error, then symbol of ternary code is generated, which corresponds to criterion of current binary symbol; correction of average erased symbols is done in those combinations of ternary code, where all three symbols are different; in accepted combinations of ternary code binary symbols are restored; symbols of ternary code combinations that correspond to repletion criterion are transformed into binary symbols and used for synchronisation of reception process.

EFFECT: increase of noise immunity and elimination of permanent component in signal.

3 dwg, 2 tbl

Description

The invention relates to the field of radio communications and can be used in information transmission systems operating in an unfavorable interference environment.

Currently, most simple and reliable computing systems and data transfer systems use binary codes for operation. Modern digital information transmission systems use coding methods described in [P.I. Penin. Digital information transmission systems. M .: Sov. Radio, 1976, pp. 70-74; B. Sklyar, Digital Communication. Theoretical foundations and practical application. M .. SPb., Kiev, 2003, pp. 113-116, B. Shevkoplyas, S. Sukhman, A. Bernov. Data transfer synchronization and encoding methods. Circuitry No. 12, 2001, p. 40 ... 42]. These are the unipolar and bipolar NRZ code, Manchester-2 code, AMI code, BNZS and HDB3 codes, which are varieties of AMI code, etc.

The main disadvantages of transmitting discrete information using such codes are as follows:

- when transmitting long blocks (sequences, chains) of units or zeros using codes such as NRZ and AMI, the signal contains a constant component, which leads to a violation of synchronization between the transmitting and receiving sides and complicates the implementation of the radio channel;

- when transferring long blocks using codes such as BNZS and HDB3 to compensate for the constant component in the signal, you have to pay by introducing redundancy and the complexity of the encoding and decoding algorithms, which also affects the complexity of the implementation of the equipment of the information transmission channel;

- when transmitting information using codes of the "Manchester-2" type, the payment for the absence of a constant component in the signal is also the extension of the working frequency band, as a result of which, where the frequency resource is limited, the use of such codes is not advisable.

In [P.I. Penin. Digital information transmission systems. - M .: Owls. radio, 1976, p. 68] it is shown that the transmission of digital information in the form of symbols of the ternary system (0, 1, 2) or (1,0, -1), which represent three different signal states, is closest to optimal. However, its application requires simple algorithms for converting binary information into ternary and simple inverse transformation, which has not been implemented.

The closest in technical essence to the proposed one is a method for transmitting discrete information using three-level coding, described in [B. Shevkoplyas, S. Sukhman, A. Bernov. Data transfer synchronization and encoding methods. Circuitry No. 12, 2001, p. 42, 43], adopted as a prototype.

The prototype method uses three levels: negative, zero and positive, when “guaranteed” changes in the signal level are created when switching from one signal interval to another, regardless of the structure of the transmitted binary sequence. In this case, there are no situations when the same state of a symbol is repeated in adjacent measures.

The prototype method is as follows. On the transmitting side, at each clock cycle (time interval equal to the duration of the binary symbol 7), each of the n binary symbols d _{i of the} original information sequence is converted into a three-level code symbol t _i according to the following recursive algorithm:

; j=1, 2,…, 6; символ «∧» означает логическое умножение (конъюнкция - И), символ «↔» - операцию сравнения (последовательность операций суммирования по модулю 2 («⊕» - исключающее ИЛИ) и логического отрицания («

» - инверсия НЕ):

).with an initial value of t ₀ = 0. Here with _ik is the search criterion for the symbol of the three-level code in the conversion table; i = 1, 2, 3, ..., n + 1;

; j = 1, 2, ..., 6; the symbol "∧" means logical multiplication (conjunction - AND), the symbol "↔" - the comparison operation (the sequence of operations of summation modulo 2 ("⊕" - exclusive OR) and logical negation ("

"- inversion NOT):

)

соответствуют приведенным в таблице 1 преобразования,Values D _k , T _k and

correspond to the transformations given in table 1,

Table 1

0 one -one T _k -one one -one 0 one 0 D _k one 0 0 one one 0

в качестве текущего значения символа трехуровневого кода t_i.in which the value of D _k should be compared with the current value of the binary symbol d _i , the value of T _k should be compared with the previous value of the symbol of the three-level code t _i-1 . At each measure, compare the pair (d _i , t _i-1 ) with the pairs (D _k , T _k ) from the conversion table, find the matching pairs and select the value corresponding to the pair (D _j , T _j )

as the current symbol value of the three-level code t _i .

Analysis of the transformation algorithm (1) shows that when transmitting a character string of the form 010101 ..., depending on the previous value of the symbol of the three-level code, there is a possibility that all subsequent characters of the new code will have the same polarity. As an example, below is the conversion of two different binary sequences when, as a result, sequences of unipolar pulses are obtained in a three-level code

This means that a constant component will appear in the signal (in areas marked in bold), which can lead to a violation of synchronization between the transmitting and receiving sides, and also complicates the implementation of the receiving part of the radio channel. For many information transfer systems this is unacceptable. Therefore, to eliminate this phenomenon in the prototype method, scrambling of data on the transmitting side and their descrambling on the receiving side are used.

, принимают текущий символ трехуровневого кода с его состоянием

и, в зависимости от комбинации этих состояний, в соответствии с таблицей 2 восстановления двоичного кодаOn the receiving side, the three-level code is inversely converted into two-level (binary) code, that is, the original binary characters are restored, and the clock signal is extracted based on the registration of the pulse edges. For this, the previous state of the received symbol of the three-level code is fixed.

, take the current character of the three-level code with its state

and, depending on the combination of these states, in accordance with Table 2 of binary recovery

table 2

one 0 0 one one 0

0 0 one one -one -one

-one one -one 0 one 0

по следующему рекуррентному алгоритму:uniquely determine the value of the current binary character of the source sequence

according to the following recursive algorithm:

. Здесь

- критерий поиска двоичного символа в таблице 2 восстановления. В таблице 2 значение

должно сравниваться с предыдущим значением принятого символа

трехуровневого кода, значение

должно сравниваться с текущим значением символа трехуровневого кода

, тогда значение

будет соответствовать текущему значению восстановленного двоичного символа

. На каждом такте сравнивают пару (

,

) с парами (

,

) из таблицы 2 восстановления, находят совпадающие пары и выбирают соответствующее паре (

,

) значение

в качестве текущего значения восстановленного символа двоичного кода исходной последовательности

.at initial value

. Here

- search criteria for a binary character in table 2 recovery. Table 2 value

must be compared with the previous value of the received character

three-level code value

should be compared with the current character value of the three-level code

, then the value

will match the current value of the restored binary character

. At each measure, a pair is compared (

,

) with pairs (

,

) from the recovery table 2, find matching pairs and select the appropriate pair (

,

) value

as the current value of the restored binary code character of the source sequence

.

The analysis of the prototype method shows that it has the following disadvantages:

- schemes of scrambling and descrambling, which are used to eliminate the constant component in the signal, are quite complex, and the efficiency of their use is determined by the number of long chains of alternating units and zeros in the original binary sequence, if any;

- the prototype method does not allow the correction of erroneous information symbols, which is somewhat feasible, since redundancy is introduced in the form of a negative level and a three-level code is formed in such a way that its two adjacent symbols always differ in state;

- Algorithms for converting and restoring the original binary information require signal delays on the transmitting and receiving sides.

To eliminate these shortcomings in the method of transmitting discrete information, which includes converting binary characters of the original sequence to characters with three possible states on the transmitting side, and restoring the original binary sequence, according to the invention, on the transmitting side, on each transmit side, by logical operations of multiplication, summation modulo 2 and inversions over the current and previous binary characters form columns consisting of one unit and two zeros, coming e in three channels; the position of the unit in the column determines information about the sign of the current binary character in the block of zeros or the block of units, zeros in the column block the channels on this measure; in an unlocked channel, at each cycle, the carrier oscillation is modulated; for each channel, the modulation parameters differ from each other in value; on the receiving side, the incoming signal is demodulated in a manner appropriate to the type of modulation; when the signal is present in any of the three channels, the other two channels are locked, then at each cycle, the corresponding column is restored by the modulation parameter; the condition for the difference of adjacent columns, i.e., the unresolved combination of two adjacent columns with a unit in the same position, defines twelve allowed combinations of the ternary code out of a possible twenty-seven with elements from the Galois field GF (3) 0, 1, 2 with a similar condition for distinguishing two adjacent combinations, that is, unresolved combinations, where two adjacent elements are the same; when an error is detected in the column, the erase character of the current ternary code symbol is generated; if there is no error, the ternary code symbol corresponding to the current binary character is generated; correction of erased symbols of the ternary code is carried out by logical operations of summing the extreme elements of the combination and conjugating the result of the summation in those combinations of the ternary code where all three elements are different; in the accepted combinations, by logical operations of summation and inversion over its elements corresponding to the signs of zero and one and the binary symbol restored on the previous measure, the current binary symbols are restored; elements of combinations corresponding to the sign of repetition of a binary symbol are converted into binary characters and used to increase the accuracy of synchronization, and the erased elements corresponding to the sign of repetition in those combinations where the two extreme elements are the same do not participate in the recovery of binary information, which is equivalent to their automatic correction with probability 0.5.

The proposed method for transmitting discrete information is as follows.

On the transmitting side, at each clock cycle, each of the n binary symbols d _{i of the} original information sequence is transformed into a column that characterizes one of the three possible states of the binary symbol according to the following recursive algorithm. The symbol of the original binary sequence d _{i is} compared with the previous symbol (delayed per cycle)

the comparison result (3) is logically multiplied by the intermediate result of the previous measure I _i-1 (i = 1, 2, ..., n)

the result of logical multiplication (4) is compared with the incoming symbol d _i

and the result of the second comparison (5) is summed modulo 2 (mod 2) with the incoming symbol d _i . At the same time, an intermediate result of this measure is obtained, which is used for similar operations of the next measure

As can be seen from (6), the intermediate result of the current measure is obtained in the form of a recurrence relation. Then, at the same time, the symbol d _i received at a given clock cycle and the intermediate result of a given measure I _i (6) are logically multiplied, the symbol d _i received at a given clock cycle is inverted and the inversion result is logically multiplied with an intermediate result of a given measure I _i (6), and the intermediate result of this tact I _i (6):

At each measure, one of the symbols (7) is one, and the other two are zeros. The correct operation of the recurrence mechanism (3) - (7) is ensured at the initial values

Symbols (7) each enter their own transmission channel, while the unit opens its own transmission channel, and zeros lock their channels. At each cycle in an unlocked channel, the carrier oscillation is modulated, for each channel, the modulation parameters differ from each other in value or type and are signs of a unit, zero, or duplicate binary symbol. Thus, at each measure, one of the three columns characterizing the sign of a binary symbol is transmitted.

Here "+" is the symbol of transposition; d _pi - elements of the formed column; the indices p = u, z or r of the elements of the column determine the operation (7), which this element was formed; i = 1, 2, ..., n. Each of the three possible columns carries information about the position of the current binary character in the unit block or block of zeros of the original binary sequence. The column U d _ui = 1, d _zi = 0, d _ri = 0, which means that this column carries information that the current character of the original binary sequence occupies an odd position in the unit block, and the unit sign will correspond to it. Accordingly, column Z carries information that the current character of the original binary sequence occupies an odd position in the block of zeros and it will correspond to the sign of zero, and column R carries information that the current character of the original binary sequence occupies an even position in the unit of units or block of zeros and it will correspond to the sign of repetition of a binary character. In this case, during transmission there cannot be two adjacent columns characterizing the same signs of a binary symbol. Then the transmission of binary information is presented as a sequence of combinations of three states (features) of a binary symbol (UZR): (ZRU), (URZ), (ZUR), etc. The condition for the difference of adjacent columns in these combinations leads to the fact that out of 27 possible combinations, only 12 are allowed:

The signs of unity, zero and repetition can be amplitude, frequency, phase or code (differ in amplitudes, carrier frequencies, phases of high-frequency filling or waveform).

:

.On the receiving side using standard methods corresponding to the type of modulation of the incoming signals [A.G. Zyuko, Yu.F. Korobov. Theory of signal transmission. M .: Communication, 1972, p. 136, Fig. 5.8 - coherent demodulation of multi-position signals; p.139, Fig.5.9 - incoherent demodulation of multi-position signals], determine the modulation parameter. Moreover, at the moment when the signal is present in any of the three reception channels, the other two channels are locked, then at each clock cycle the corresponding column is restored as the output effect of the three channels using the modulation parameter. A column formed on the transmitting side consists of three elements, while a binary symbol consists of one element. However, both the column and the binary symbol are formed in a single clock cycle. Therefore, the redundancy of combinations (10) is in the columns; therefore, it does not affect the information transfer rate, but it can be used to detect errors introduced by the transmission channel. As a result of this, a channel is realized with error detection in columns (9) due to sign redundancy. The detection of errors in the columns is carried out by a standard check for oddness, which is achieved by logical summation of the binary characters of the received feature column

:

.

If g _i = 1, therefore, there is no error, and a ternary code symbol is generated corresponding to the binary symbol P _i . For example, if P _i = U, then the generated symbol 1 if P _i = Z, then the symbol 0 if generated P _i = R, the generated character 2. Thus, the allowed codewords formed ternary code

If g _i = 0, then an error has been detected and an erase symbol X is generated. Thus, transformation (7) and the condition for distinguishing adjacent columns leads to a three-digit (ternary) code (11) with elements from the Galois field GF (3). As can be seen from (11), a change in the signs of a binary symbol in the original sequence is equivalent to a permutation of the elements in the corresponding combination from (11).

In (11), four types of combinations are distinguished. The first type includes the last six combinations, in which all three elements are different. The second - two combinations (212), (202), in which two extreme elements characterize the sign of a binary character in a block of zeros or ones. To the third - two combinations (121), (020), in which the middle element characterizes the sign of repetition. Finally, the fourth type includes two combinations (101), (010), which do not have elements characterizing the sign of the repetition of a binary symbol in a block. The processing of combinations of the ternary code is carried out after receiving the first combination and then with each shift of two clock cycles, the number of processed combinations of one kind or another will be determined by the structure of the original binary sequence, i.e. the number of units and zeros in it and their length. The shorter the blocks of ones and zeros (but not less than two characters) and the more there are, the more combinations of the first kind will be in the converted message. The longer the blocks of ones and zeros are, the more combinations of the second and third kind will be. Finally, if there are many sections in the original binary sequence where zeros and ones alternate (many blocks of unit length), then there will be more combinations of the fourth kind.

Taking advantage of the fact that combinations (11) should not have identical adjacent elements, and the elements of combinations are elements of the Galois field GF (3), they correct the middle erased element in combinations of the first type (where all three characters are different), provided that its two extreme item accepted correctly. To do this, carry out the following logical operations: summarize the non-erased elements of the combination and take the element conjugate to the summed result as the corrected one:

In (12), m = 3 is the significance of the code. If the middle element is erased in combinations of another type (where the extreme elements are the same), then the erased element is not corrected.

логически суммируют с исходным информационным символом

, восстановленным на предыдущем тактеThe elements of the accepted combinations of the ternary code corresponding to the signs of ones and zeros coincide with the corresponding binary characters, so they are directly used to restore the original binary sequence. When restoring the original binary information on these elements of the code combination of the i-th clock, the following operations are performed. The element of the current ternary code combination corresponding to the unit attribute,

logically summarize with the original information symbol

restored to the previous measure

where the symbol "∨" means logical summation (disjunction - OR). The result of logical summation (13) is subjected to the negation operation

the element of the current ternary code combination corresponding to the zero sign, t _{zi is} inverted and logically summed with the result of the negation operation (14)

the value of the information symbol of the original binary sequence restored at the current clock cycle is found as the negation of the result of logical summation (15)

.The resulting relation (16) is a recurrent algorithm for recovering the symbols of the original binary sequence at the initial value

.

Elements of combinations of the ternary code corresponding to the signs of repetition are converted into binary characters and used to synchronize the reception process. Moreover, in combinations of the third type (where the middle element characterizes the sign of repetition), the erased element does not participate in the recovery of binary information, therefore, it is automatically corrected.

Since any of the three channels on both the transmitting and receiving sides is active only at the moment of transmission or reception of the characteristic, and the signs are spaced at least by a beat, there will be no constant component in the signal. As shown above, the algorithm for introducing redundancy (a mechanism for converting binary characters to columns) is simple, the erased elements in the ternary code combinations are corrected by two logical operations, and the original binary sequence is restored on the receiving side by two logical operations. Correction of erroneous ternary code characters requires only two delay cycles.

In the converted binary sequences, depending on their structure, the number of processed combinations of the first type fluctuates around 1/2 of their total number, the number of combinations of the third type is about 1/6 of their total number. Therefore, error correction can be implemented in the proportion of combinations, which averages about 2/3 of their total number. For example, a sequence of binary characters

000011101010011101000110111100010

ternary code is represented as

02021210101021210102012012121202010.

The number and type of processed combinations, respectively:

(020), (021), (121), (101), (101), (102), (212), (210), (010), (020), (012), (201), (121 ), (120), (020), (010).

As you can see, out of 16 processed combinations, 6 combinations of the first type, 1 combination of the second type, 5 combinations of the third type and 4 combinations of the fourth type. The proportion of combinations in which the erased middle element can be corrected is (6 + 5) / 16 = 11/16, which differs from 2/3 by only 2% up. And for a sequence of binary characters

1000001011110110110010010011010010 conversion to ternary code gives

1020201012120120120210212010210. The number and type of processed combinations, respectively:

(102), (202), (201), (101), (121), (120), (012), (201), (120), (021), (102), (212), (201 ), (102), (210).

Moreover, out of 15 processed combinations, 11 combinations of the first type, 2 combinations of the second type, 1 combination of the third type and 1 combination of the fourth type. The proportion of combinations in which the erased middle element can be corrected is (11 + 1) / 15 = 12/15, which differs from 2/3 by 13% up.

Thus, the proposed method for transmitting discrete information has greater noise immunity than the prototype method, automatically eliminates the constant component in the signal, implements the restoration of the original binary information and error correction with a small delay of two clock cycles, and is also simple to implement.

An enlarged functional diagram of the adjusted device for implementing the proposed method is presented in figure 1, where it is indicated:

1 - block operation summation modulo two;

2 - block intermediate operations;

3 - block forming columns;

4 - modulator;

5 - demodulator;

6 - block correction of erroneous symbols of the ternary code;

7 is a block of operations for recovering characters from an initial binary sequence.

The device with which the proposed method is implemented comprises, on the transmitting side, a summation block modulo two 1, an intermediate block 2, a column forming block 3, the three outputs of which are connected to the corresponding inputs of the modulator 4, the output of which is the output of the transmitting side, the output of the intermediate operation unit 2 is connected to the first input of the column forming unit 3 and the second input of the summing operation unit modulo two 1, the first input of which is connected to the first input of the intermediate unit intramural operations 2 and the third input block forming columns 3 and is input to the transmitting side, and an output - to a second input of the intermediate operations 2 and the second input forming unit 3 columns.

On the receiving side, there is a demodulator 5, a symbol correction unit of the ternary code 6, and a block of symbol recovery operations of the source binary sequence 7, the output of which is the output of the receiving side of the device. Demodulator 5 has three outputs that are connected to the corresponding inputs of the ternary code symbol block 6, the first and second outputs of which are connected to the corresponding inputs of the symbol recovery block of the original binary sequence 7, and the fourth output is connected to the second input of block 5 and the third input of block 7 .

. При этом, если на вход устройства поступит двоичная единица и значение результата (6) равно единице, то с первого выхода блока 3 на соответствующий вход модулятора 4 поступит единица второй и третий входы модулятора 4 будут заперты. Если на вход устройства поступит двоичная единица и значение результата (6) равно нулю, то с третьего выхода блока 3 на соответствующий вход модулятора 4 поступит единица, а первый и второй входы модулятора 4 будут заперты. Если на вход устройства поступит двоичный нуль и значение результата (6) равно единице, то первый и третий входы модулятора 4 будут заперты, а со второго выхода блока 3 на соответствующий вход модулятора 4 поступит единица. Наконец, если на вход устройства поступит двоичный нуль и значение результата (6) равно нулю, то с третьего выхода блока 3 на соответствующий вход модулятора 4 поступит единица, а первый и второй входы модулятора 4 будут заперты. Таким образом, на каждом такте на входы модулятора 4 поступает один из столбцов (9), элементы которого формируются на выходах блока 3. Этот столбец несет информацию о позиции текущего символа исходной двоичной последовательности в блоке нулей или блоке единиц. В модуляторе 4 в соответствии с поступившим столбцом (9) модулируется несущее колебание и в канал связи поступает высокочастотный сигнал, несущий информацию о признаке соответствующего символа исходной двоичной последовательности.The device operates as follows. On the transmitting side, the symbol of the original binary sequence with a unit amplitude and duration T is fed to the first input of block 1, to the input of block 2 and to the third input of block 3. After a clock cycle from the output of block 2, the second input of block 1 and the first input of block 3 will receive the result ( 5), and from the output of block 1 to the second input of block 3 - the result (6). From the output of block 3 to the corresponding inputs of the modulator 4 receives the column (7)

. Moreover, if a binary one arrives at the input of the device and the value of the result (6) is equal to one, then from the first output of block 3, the unit receives the second and third inputs of modulator 4 from the first output of block 3. If the binary unit arrives at the input of the device and the value of the result (6) is zero, then from the third output of block 3, the unit will receive the corresponding input of modulator 4, and the first and second inputs of modulator 4 will be locked. If binary zero arrives at the input of the device and the value of the result (6) is equal to one, then the first and third inputs of modulator 4 will be locked, and one from the second output of block 3 will go to the corresponding input of modulator 4. Finally, if binary zero arrives at the input of the device and the value of the result (6) is zero, then one from the third output of block 3 will go to the corresponding input of modulator 4, and the first and second inputs of modulator 4 will be locked. Thus, at each clock cycle, one of the columns (9) arrives at the inputs of modulator 4, the elements of which are formed at the outputs of block 3. This column carries information about the position of the current symbol of the original binary sequence in a block of zeros or a block of units. In modulator 4, in accordance with the received column (9), the carrier oscillation is modulated and a high-frequency signal is received into the communication channel that carries information about the attribute of the corresponding symbol of the original binary sequence.

,

,…,

,…,

,

,…,

,…, а элементы комбинаций троичного кода

преобразуют в двоичные символы

. С первого и второго выходов блока 6 на соответствующие входы блока 7 поступают последовательности

,

,…,

,…, и

,

,…,

,…, где в соответствии с алгоритмом (16) осуществляется восстановление символов исходной двоичной последовательности, которая с выхода блока 7 поступает на оконечное устройство. В то же время с первого выхода блока 6 элементы третьей последовательности, преобразованные в двоичные символы

,

,…,

,… поступают на вход устройства синхронизации.At the receiving side, modulated signals are received at the input of demodulator 5, which are processed by standard methods corresponding to the type of modulation of the incoming signals. At the same time, the signal with the maximum level unlocks the corresponding output of the demodulator 5 and, at the same time, locks the two remaining outputs of the demodulator 5. At the output of the demodulator 5, the transmitted columns are restored, the elements of which are fed to the corresponding inputs of block 6, where the erroneous elements of the ternary code are erased and corrected. From the corresponding elements of correctly accepted combinations of the ternary code, sequences of characters are formed

,

, ...,

, ...,

,

, ...,

, ..., and elements of ternary code combinations

convert to binary characters

. From the first and second outputs of block 6, the corresponding inputs of block 7 receive the sequence

,

, ...,

, ..., and

,

, ...,

, ..., where, in accordance with the algorithm (16), the characters of the original binary sequence are restored, which, from the output of block 7, is sent to the terminal device. At the same time, from the first output of block 6, elements of the third sequence converted to binary characters

,

, ...,

, ... enter the input of the synchronization device.

The implementation of the device that implements the proposed method for transmitting discrete information does not cause difficulties, since the logical elements and functional units included in the device blocks are well known, widely used in domestic and foreign patents, and are also described in the technical literature.

The block diagram of the block of intermediate operations 2 is presented in figure 2, where it is indicated:

2.1 - delay unit per cycle;

2.2, 2.6 - the first and second blocks of summation modulo 2;

2.3, 2.7 - the first and second blocks of the inversion operation (logical negation);

2.4 - block of logical multiplication (conjunction);

2.5 - a block of dynamic memory for one element.

Block 2 contains a series-connected delay block per cycle 2.1, a summation block modulo 2.2, an inversion operation block 2.3, and a dynamic memory block for one element 2.5, the input of which is the second input of block 2 (Fig. 1), series-connected modulo summation block 2 2.6 and the inversion operation block 2.7, the output of which is the output of block 2 (Fig. 1), and the first input of the summing block modulo 2 2.6 is connected to the second input of the summing block modulo 2 2.2 and the input of the delay block to clock 2.1, which is the first block 2 input (f D.1).

Block 2 works as follows. The symbol of the original binary sequence d _i enters the input of block 2.1, the second input of block 2.2 and the first input of block 2.6, simultaneously with the output of block 2.5, its contents I _i-1 will go to the second input of block 2.4. After a time equal to the duration of the binary symbol (cycle) in blocks 2.2 ... 2.4 and 2.6, 2.7, the corresponding logical operations are implemented: in blocks 2.2 and 2.3, operation (3), in block 2.4 - (4), in blocks 2.6 and 2.7 - (5), which from the output of block 2.7 will go to the second input of block 1 (Fig. 1) and to the first input of block 3 (Fig. 1), while in block 1 (Fig. 1), operation (6) is implemented and with it output to the second input of block 3 (figure 1) and block 2.5 will receive a new result I _i replacing the previous result I _i-1 in block 2.5. Similarly, the operation of block 2 is described at any beat.

The block diagram of the block correction of erroneous symbols of the ternary code 6 is presented in figure 3, where it is indicated:

6.1, 6.5 - the first and second blocks of the operation of logical summation (disjunction);

6.2 is a block for converting columns to ternary code symbols;

6.3 - error control unit in the 1st and last columns of the message and the generation of the erase symbol;

6.4 - control unit for identical characters in the 1st and 3rd digits of a three-digit register and control of the erase character in the third digit of a three-digit shift register;

6.6 - three-digit shift register;

6.7 - block conversion of ternary code characters into binary characters;

6.8 - key;

6.9 - subtraction block;

6.10 - a block of read-only memory storing the significance of the code m;

6.11 - adder;

6.12 comparison block;

Block 6 contains a series-connected adder 6.11, a subtraction block 6.9, a key 6.8 and a three-digit shift register 6.6, a series-connected logical summation block 6.1 and an error control block in the 1st and last columns of the message and generate an erase symbol 6.3, in addition, block 6 contains a block for converting columns to symbols of the ternary code 6.2, a block of read-only memory storing the significance of the code m 6.10, a control unit for identical characters in the 1st and 3rd digits of a three-digit register, and a control for the erasure symbol in the third digit of a three-digit one shift register 6.4, a comparison block 6.12 and a block for converting ternary code symbols to binary characters 6.7, while the first input of the comparison block 6.12 is connected to the first input of the adder 6.11 and the third output of the three-bit shift register 6.6, the second input of the comparison block 6.12 is connected to the second input of the adder 6.11 and the fourth output of the three-digit shift register 6.6, the second input of the subtraction block 6.9 is connected to the output of the permanent memory block 6.10, the second control input of the key 6.8 is connected to the second output of the block 6.4, the output of the logic block summation 6.1 is connected to the fourth input of the block converting columns into symbols of the ternary code 6.2, three inputs of which are connected to the corresponding inputs of the logical summing block 6.1, which are inputs of block 6, the three outputs of the block converting columns to symbols of the ternary code 6.2 are connected to the corresponding inputs of the logical block summation 6.5, the output of which is connected to the first input of the shift register 6.6, and the fourth input is connected to the third output of the block 6.3, the output of the comparison unit 6.12 is connected to the fourth input m block 6.4, the first output of which is connected to the second input of block 6.3, and the first and second inputs are connected to the first and second outputs of the shift register 6.6, the first output of block 6.3 is connected to the third input of the block 6.4, and its second output is connected to the third, fourth and the fifth inputs of the shift register 6.6 and is the fourth output of block 6, the fifth output of the shift register 6.6 is connected to the input of the block converting the ternary code characters into binary characters 6.7, the three outputs of which are the corresponding outputs of block 6.

Block 6 works as follows. In the initial state, the shift register 6.6 is reset, the key 6.8 is closed. The first three clocks, when the bits of register 6.6 are filled, block 6.7 is passive. At each cycle, from the three outputs of the demodulator 5 (Fig. 1), the column (9), the elements of which are binary characters, is supplied to the corresponding inputs of block 6. At the same time, this column enters the corresponding inputs of block 6.2. If the column is accepted without error, then one will arrive from the output of block 6.1 to the first input of block 6.3 and the fourth input of block 6.2, the third output of block 6.3 will be locked. From one of the outputs of block 6.2, the symbol of the ternary code will come to the corresponding input of block 6.5, which from its output will go to the third digit of the shift register 6.6. From the first and second outputs of the shift register 6.6, the ternary code symbol and zero, respectively, will arrive at the first and second inputs of block 6.4. From the output of block 6.12, the fourth input of block 6.4 will receive information about the difference in the contents of the first and third bits of the shift register 6.6, then from the first output of block 6.4, the second input of block 6.3 will receive a ban on generating a reset pulse of the receiving device to its original state, the second output of block 6.3 will be locked, from the second output of block 6.4, the second control input of the key 6.8 will receive zero, confirming the closedness of the key 6.8. So, regardless of the operations performed in blocks 6.11 and 6.9, the contents of the second register will not change. Similarly, block 6 works on any clock cycle in the case of error-free columns, when the contents of the first and third bits of the shift register 6.6. different or the same. Starting from the fourth step, from the fifth output of the shift register 6.6, ternary code symbols will begin to arrive at the input of block 6.7, and binary symbols will be supplied from its outputs to the corresponding inputs of the recovery unit of the original binary sequence and to the input of the synchronization device.

If the first received column is erroneous, then zero will arrive from the output of block 6.1 to the first input of block 6.3. Further, regardless of the results of the work of all the other blocks on this clock, block 6.3 will generate a reset pulse, which will reset the contents of the shift register and bring the receiving device to its original state. If the last column is erroneous in the received information, block 6 works on the last measure in exactly the same way.

Consider the case when the input of block 6 receives a stream of columns in which the erroneous ones are distributed by the “ladder” through one or less often (except for the first and last erroneous). On the first bar, everything will happen as described above. Let the second column to the inputs of block 6 receives an erroneous column. At the same time, it arrives at the corresponding inputs of block 6.2. Then, from the output of block 6.1, the first input of block 6.3 and the fourth input of block 6.2 will receive zero. In this case, the outputs of block 6.2 will be locked, from the third output of block 6.3, the erase character will come to the fourth input of block 6.5, which from its output through the first input of the shift register 6.6 will go to the third digit, shifting the correctly received first symbol of the ternary code to the second digit. From the first and second outputs of the shift register 6.6, the corresponding inputs of block 6.4 will receive the contents of the first and second bits of the register 6.6, from the output of block 6.12 the fourth input of the block 6.4 will receive information about the difference in the contents of the first and third bits of the register 6.6. From the first output of block 6.4, a reset inhibit signal will be sent to the second input of block 6.3, and zero will come from the second output of block 6.4 to the second control input of key 6.8, confirming that key 6.8 is closed. This means that regardless of the operations performed in blocks 6.11 and 6.9, the contents of the second digit of register 6.6 will not change. On the third step, an error-free column enters the inputs of block 6. At the same time, it arrives at the corresponding inputs of block 6.2. Then, from the output of block 6.1, the unit receives the first input of block 6.3 and the fourth input of block 6.2, the third output of block 6.3 will be locked. From one of the outputs of block 6.2, the ternary code symbol will arrive at the corresponding input of block 6.5, which from its output will go to the third digit of the shift register 6.6, moving the erase symbol to the second digit, and the first symbol of the ternary code to the first digit. From the first and second outputs of the shift register 6.6, the ternary code symbol and the erase symbol, respectively, will arrive at the first and second inputs of block 6.4. From the output of block 6.12, the fourth input of block 6.4 will receive information either about the difference in the contents of the first and third bits of the shift register 6.6, or that their contents are the same. If the contents of the first and third digits of the shift register 6.6 are different, then from the first output of block 6.4 to the second input of block 6.3 there will be a ban on resetting the receiving device to its original state, the second output of block 6.3 will be locked, from the second output of block 6.4 to the second control input of key 6.8 the unit will arrive by opening the key 6.8. At the same time, the result of summing the contents of the first and third digits from the output of the summing block 6.11 will go to the first input of the subtraction block 6.9, the second input of which will receive the number m. From the output of the subtraction block 6.9, the first input of the key 6.8 will receive the result (12). Since the key 6.8 is open, this result will go to the second input of the shift register 6.6, replacing the erase symbol in its second digit. Thus, the erroneous symbol of the ternary code will be corrected. If the first and third digits of the shift register 6.6 contain the same ternary code symbols, then from the first output of block 6.4, the second input of block 6.3 will receive a ban on resetting the receiving device to its original state, the second output of block 6.3 will be locked, but from the second output of block 6.4 the second control input of the key 6.8 receives zero, closing the key 6.8. In this case, the erasure symbol can go to the input of block 6.7, where it is ignored. With an average probability of 0.5, the erase character can replace the ternary code symbol, which corresponds to the column of the sign of repetition of a binary symbol in a block of zeros or ones. But this symbol of the ternary code is not involved in restoring the original binary sequence, therefore, this is equivalent to correcting such a symbol with the same probability.

Note that blocks 6.3 and 6.4 consist of well-known logic elements. The error control block in the 1st and last columns of the message and the generation of the delete symbol 6.3 contains a counter, logical elements AND, OR, NOT, adders modulo 2, a key, as well as blocks of read-only memory.

The control unit for identical symbols in the 1st and 3rd digits of a three-digit register and the control of the erase symbol in the third digit of a three-digit shift register 6.4 also consists of known logical elements AND, NOT, and adders modulo 2.

Claims (1)

A method of transmitting discrete information, including, on the transmitting side, converting the binary symbols of the original sequence to a combination with three possible states, and on the receiving side, restoring the original binary sequence, characterized in that on the transmitting side, on each clock cycle, each current binary symbol of the original sequence is compared with the previous character is converted into a combination that characterizes one of the three possible states of the binary character, so that on Each measure simultaneously multiplies the binary symbol received on a given measure and the intermediate result of this measure, inverts the binary symbol received on a given measure and multiplies with the intermediate result of this measure, and also inverts the intermediate result of this measure, and at each measure one of the indicated symbols of the combination is a unit , and the other two with zeros, and each of the symbols of the combination goes to its own transmission channel, while the unit opens its own transmission channel, zeros define locked on this clock, the transmission channels, on each clock, each of the three possible combinations carries information about the position of the current binary symbol in the unit or zero block of the original information sequence and the transmission of binary information is presented as a sequence of combinations of possible combinations of the three states of the binary symbol, provided that the adjacent symbols are different combinations, at each cycle in an open transmission channel, a combination that carries information about the position of the current binary symbol modulate the carrier oscillation e and a high-frequency signal is received into the communication channel that carries information about the characteristic of the corresponding symbol of the original binary sequence, and for each transmission channel the modulation parameters differ from each other in value and are signs of unity, zero or binary symbol repetition, received on one of the channels on the receiving side the high-frequency signal is demodulated and, at each cycle, the transmitted combination of binary symbols is restored at the outputs of the three channels according to the value of the modulation parameter, form Allowing codewords ternary code whose elements are elements of the Galois field GF (3), provided adjacent differences combinations if there is no error, then generate the ternary code symbol corresponding current binary symbol basis; when an error is detected in the received combination, the erase character of the current ternary code symbol is generated, the middle erased character in the ternary code combination is corrected, where all three characters are different, provided that the two extreme characters are received correctly, the characters of the accepted ternary code combinations corresponding to the signs of ones and zeros , together with the corresponding information binary symbols restored on the previous measure, are used to restore the information symbols of the original binary n on the current measure sequence; symbols of ternary code combinations corresponding to the repetition sign are converted into binary symbols and used to synchronize the reception process.

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