RU2812335C1 - Code pattern synchronization device - Google Patents

Abstract

FIELD: telecommunications.

SUBSTANCE: invention can be used in receiving devices for synchronizing code combinations. The effect is achieved by eliminating the transmission together with the base information of the cyclic synchronization signal and with a corresponding decrease in the information transmission rate, by reducing the cycle duration to the duration of the code combination and optimizing the process of detecting the restoration of synchronization by erasing the previous accumulated synchronization information in the shift register block and in the decision memory block node after detecting a synchronization failure.

EFFECT: improved noise immunity of receiving code combinations, reduced synchronization search time, reduced probability of false detection of code combination synchronization, and also reduced loss of binary information in case of synchronization failures.

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Description

The invention relates to telecommunications and can be used in receiving devices for synchronizing code combinations of binary messages encoded with any uniform code with error detection or correction, which include, for example, block and systematic codes, as well as codes with parity or odd

Block codes differ in that with each sequence of a certain number of elementary messages (binary symbols) a block of n characters (n-character code combination) is composed. Moreover, if a certain number n is selected, then N _total = 2 ⁿ different combinations of n characters can be constructed, of which N _o < N _total are allowed code combinations. The remaining N _total - N _o combinations are prohibited and are not used to transmit messages [1, p. 84].

A systematic (n, k) code is a set of n-bit (n-character) code combinations in which k bits (binary characters) represent the result of primitive message encoding, which are called information bits (characters). The remaining n-k bits (characters) are called checking (correcting) and are used to detect and correct errors [1, p. 100].

A parity-check code is formed by adding to a group of information symbols (code combination) representing a simple (non-redundant) code of one redundant (check) symbol.

When forming a code combination, 0 or 1 is written as a control symbol so that the sum of the “ones” in the combination, including the redundant symbol, is even (for parity check) or odd (for odd parity check). If, when transmitting information, the receiving device detects that in the received code combination the value of the control symbol does not correspond, for example, to an even sum of “units,” then this is perceived as a sign of an error.

There is a known method for synchronizing code combinations using absolutely precise time when transmitting discrete messages over radio communication channels, which consists in the fact that clock synchronization and synchronization of code combinations (cycle synchronization) of the transmitter and receiver are carried out constantly, regardless of the transmission of the message, and a manipulation speed is used, which provides a duration of message elements that is many times greater than the signal propagation time or the possible difference in signal propagation times from the transmitter to the receiver. The beginning of the transmission of each next element of the message is carried out at predetermined moments of absolute universal and/or system exact time, and also in that the time of signal propagation from the transmitter to the receiver is determined and messages are generated at the transmitter in advance by the time of signal propagation or at the receiver they are delayed by time of signal propagation, moments of making decisions about the meaning of received elements and signs (code combinations) [2].

The disadvantage of this method is that it can only be used in communication systems with low operating speeds, in which the duration of the chips is much greater than the path difference of the rays in a multipath communication channel. In addition, additional radio equipment is required to bind to system time signals.

In [3] there is a known method for synchronizing code combinations in serial modems that use randomization of binary information by converting the original code combinations of information into a pseudo-random binary sequence in order to decorrelate the number of binary symbols for high-quality correction of inter-symbol distortions [4], according to which the synchronization of code combinations is carried out by time shifts of the received binary signal without introducing additional cycle synchronization information. In this case, information about the presence of codeword synchronism can be obtained from the demodulated signal itself after it has been “recovered” (after performing the inverse and synchronous randomization operation on the transmitting side). To do this, it is necessary that the original transmitted message be encoded with some kind of block correction code before randomization. If the synchronization of code combinations is violated, the output “recovered” signal arriving in the synchronization mode will be a pseudo-random binary sequence, by analyzing which it is possible to establish the fact of a synchronization violation. Knowing the maximum possible displacement value of the main (working) sample of the channel impulse response, it is possible to search for a synchronous state using the bit-shift method, i.e. by changing the delay of the demodulated signal (before its “restoration”) by a known number of information elements, both in the lagging and leading directions, analyzing the output code combinations of information at each fixed value of the signal delay.

The block diagram of a device that implements this method of synchronizing code combinations is given in [3].

However, this method of synchronizing code combinations, which does not require changes in the structure of the transmitted signal, has a long synchronization recovery time due to the sequential method of searching for a synchronous state by detecting the known code with which the transmitted message is encoded.

There are known methods for synchronizing code combinations and receiving synchronization devices for their implementation, which are also called frame synchronization devices designed to work with signals containing explicit synchronizing information [5]. Here it is assumed that additional synchronizing information - a cyclic synchronization signal (CS) - must be introduced into the original transmitted binary sequence, including one encoded with some uniform correction code. The DS can be either a single-character synchronization signal transmitted among the information symbols of a binary sequence, when at the same i-th position of each cycle of duration T _c = N binary symbols with serial numbers i = 1, 2, ..., N, synchronization symbol 1 is transmitted or sync symbol 0 (or alternating sync symbols 1 and 0). Or the CS can be a multi-symbol clock signal transmitted among the information symbols of a binary sequence, when at the same m positions of each cycle with a duration T _c = N binary symbols with serial numbers i = 1, 2, ..., N are transmitted concentrated or distributed over the cycle synchrogroup of m synchrosymbols.

In the transmitted information binary sequence of n-symbol code combinations of any uniform code, synchronization symbols or synchronization groups of the cyclic synchronization signal are placed between the n-symbol code combinations so that on the receiving side a known (synchronous) time relationship is observed between the time position of the synchronization position and the time position of the boundaries code combinations, i.e. the first or last nth character of each code combination in the received signal.

When searching in the received binary sequence for the temporal position of the i-th cycle position (i = 1, 2, ..., N), corresponding to the temporal position of the cyclic synchronization signal or synchronization position, the responses of the recognizer are used as the primary source of synchronization information to be processed in one way or another sync signal, which can be used, for example, as a sync group decoder [5]. By analyzing the responses of the sync signal recognizer from each position of a cycle with a duration T _c = N = m + Ln (in the number of symbols), where L is the number of code combinations in one cycle, n is the number of symbols in a code combination, m is the number of sync symbols in a sync group, determine the time the position of the synchronization position corresponding to the time position of the boundaries of code combinations at L = 1 or the boundaries of blocks of L>1 code combinations in accordance with the duration of the selected T _c in the number of binary symbols.

However, the methods for synchronizing code combinations given in [5] do not meet the requirements of the optimal algorithm for searching for the timing position of the synchronization signal or the timing position of the synchronization position. This does not allow achieving optimization of the main parameters, for example, minimizing the search time for the synchronization position while maintaining the probability of correctly detecting the synchronization position at the required level when communication conditions change. The quasi-optimal algorithm for searching the temporary position of the synchronism position or the phase of the synchronization given in [5] needs clarification, since it does not take into account such an important parameter of the digital system as the number of symbols N in the cycle. In addition, the above algorithm assumes a fixed search time for the CS, regardless of the probability of correct reception of the synchronization symbol.

In [6], based on the criterion of maximum a posteriori probability, an analytical expression was obtained that describes the optimal algorithm for searching for the phase of the synchrotron or the temporal position of the synchronism position among other positions of each cycle of the analyzed binary sequence. However, in contrast to similar expressions obtained in [5] and [7], here the dependence of all DS parameters on the DS search algorithm is taken into account. This expression, taking into account simple transformations, can be represented as [8]

Here K = P(H ₁ /G)/P(H ₂ /G) is the ratio of the posterior probabilities of the truth of the alternative hypotheses H ₁ and H ₂ , where the hypothesis H _i means that the analyzed i-th position of the cycle corresponds to the CS phase;

N is the number of binary symbols in a cycle or cycle interval (CI);

n _i is the number of registered responses of the synchronization signal identifier at the i-th position of the cycle during the duration G of the DI analysis;

m is the number of synchronization symbols in a concentrated or distributed synchronization group, the regular occurrence of which among information symbols represents a cycle synchronization signal (CS);

P _p - probability of correct reception of the synchronization symbol P _osh - the probability of an erroneous reception of a binary symbol or the probability of an error of any symbol of a received binary signal - a synchronization symbol or an information symbol; in addition, it is assumed here that P _p >0.5);

R _l - the probability of the appearance of a false sync symbol in a group of m symbols analyzed by the sync signal recognizer (in most cases it can be assumed that R _l ≈ 0.5);

In [8], it was established that the duration of the analysis interval G of the digital digital signal when searching for the digital synchronization phase cannot be arbitrary and independent of the cycle length N (in the number of binary symbols), and its minimum value to ensure detection of the central digital phase or the temporary position of the synchronism position should have a very specific meaning CI with the ratio of equal posterior probabilities K=1 plus one CI, where the symbol] [means rounding to the nearest integer:

To ensure a given ratio of posterior probabilities K, which determines the corresponding value of the probability of correct detection of the CS phase, it is necessary to analyze a greater or equal number of DIs than G _min , i.e. CI at K ≥ 1.

In this case, the optimal algorithm for searching for the CS phase, obtained in [6], can be briefly written as

with the duration of the analysis interval G = f(K, Р _p , Р _l , N, m) in cyclic intervals (CI). In this case, the value of G can be determined from the relation obtained in [8], without taking into account the time (in CI) required to detect a synchronism failure.

One of the methods for synchronizing code combinations that implements the given algorithm for searching for the temporary position of the CS or the synchronization position in accordance with (3) subject to condition (4) is described in [9].

In accordance with this method, a sequence of clock pulses and a binary sequence of n-symbol code combinations containing an m-symbol cyclic synchronization signal, which is a synchronization group of m < n sync symbols, which is repeated every L n-symbols, are supplied to the clock and information inputs of the sync signal recognizer, respectively. code combinations, with cycle duration N = m + n⋅L binary symbols. When a sync group, or an m-symbol combination similar to a sync group (false sync group) arrives in any clock interval (TI), the sync signal identifier in this TI generates an output response in the form of a “single” symbol 1, or the absence of symbol 1 (symbol 0), if the m-symbol sync group is distorted. The sequence of responses from the output of the synchronization signal identifier is supplied to the first input of the prohibition element, as well as the input of the least significant digit of the first input of the adder.

From the output of the adder, a binary signal in parallel code is supplied to the signal input of a shift register block, consisting of z N-bit shift registers, which separately combine clock inputs and reset inputs, which are respectively the clock input and reset input of the shift register block, and the signal inputs , the outputs of the first bits and the outputs of the last bits of all shift registers are, respectively, a signal input, an additional output and the output of a block of shift registers, which is supplied to the second input of the adder. The clock input of the shift register block is combined with the corresponding inputs of the synchronization signal identifier, the decision node and the cyclic pulse shaper, the output pulses of which are supplied to the second input of the prohibition element and the input of the cycle counter, and the output pulses of the prohibition element are supplied to the counting input of the counter of distorted synchronization signals, to the reset input of which a pulse signal is supplied from the output of the cycle counter.

The shift register block ensures that the results of counting responses are stored at each position of the cycle in the form of z-bit binary numbers during the duration of each cycle, while the value of z determines the memory capacity of the counting results. The results of counting responses at each position of the cycle from the additional output of the shift register block sequentially with the frequency of clock pulses are supplied to the signal input of the decision node, where the input binary number in the parallel code is simultaneously supplied to the first inputs of the subtraction block, memory block and the first comparison block, in which the input number is compared with a binary number stored in the memory block and, if it exceeds the number of the memory block, then at the output of the first comparison block a pulse is generated that ensures that a new (input) number is written to the memory block, into which the largest current counting result of responses to which one is rewritten -position of the cycle, which is then compared with the calculation results at subsequent positions of the cycle. The resulting difference between the number of the memory block and the input number at the output of the subtraction block in the form of a binary number in parallel code is fed to the first input of the second comparison block, in which it is compared with the pore number M arriving at its second input (which is the control input of the decision node) from the output the first threshold selection block. In this case, if the number from the output of the subtraction block is less than the threshold number M, then a “single” (inhibiting) level will be sent from the output of the second comparison block to the reset input of the comparison counter, setting and holding it in the “zero” state. Otherwise, if the largest number written into the memory block in any j-th clock interval and corresponding to the result of accumulation at the j-th position of the cycle, will exceed each of the subsequent numbers arriving one after another by an amount equal to or greater than the threshold number M other from the additional output of the shift register block, then the comparison counter will count consecutive N-1 clock pulses coming from the clock input of the decision node, after which a pulse synchronization signal is generated at the output of the comparison counter, which is supplied to the reset input of the memory block and from the output of the decision node - to the reset inputs of the shift register block and the cyclic pulse shaper. As a result, the memory block and the shift register block are reset, and the frame pulse shaper is phased in accordance with the timing position.

For a current assessment of the degree of distortion of the received signal, the number R of distorted sync groups is counted using a counter of distorted sync signals during the counting of a fairly large number of cyclic pulses Q, counted by the cycle counter, and the probability (frequency) of erroneous reception of a sync group is determined with a certain degree of accuracy using the formula After counting each Q cyclic pulses, a certain binary threshold number M is formed using a threshold selection block depending on the value of the binary number R instead of the previous number generated when counting the previous Q cyclic pulses. Thus, during the counting time of each Q cycles, a certain threshold number M is supplied to the decision node, which can take in each specific case one of discrete values (gradations) depending on the quality of the received signal.

The disadvantages of this method include the following.

1. This method of synchronizing code combinations requires the introduction of a cyclic synchronization signal (a periodically repeated m-symbol synchronization group among n-character code combinations) into the transmitted information binary sequence of n-character code combinations to ensure synchronization of code combinations on the receiving side. Accordingly, it is necessary to increase the transmission speed due to the introduction of redundant synchronization symbols into the original information sequence of code combinations in order to preserve the communication channel capacity [1] and to modify the transmitting equipment. In addition, an increase in transmission speed leads to a decrease in the duration of binary symbols and a decrease in the noise immunity of information reception [1].

2. This method of synchronizing code combinations, which implements with some approximation the optimal algorithm for searching for the temporary position of the synchronization position (3) taking into account (4), is suitable for working, for example, in a KB communication channel. In this channel, there are relatively frequent failures in the synchronization of code combinations when operating serial high-speed modems due to frequent switching of the radio receiver from one beam to a more powerful beam during deep signal fading. With frequent synchronization failures, the probability of detecting false synchronism during a relatively short time interval between adjacent synchronization failures is relatively small. In addition, when working under these conditions, it is advisable to continuously search for the synchronization position, since if at each synchronization failure the synchronization failure detection procedure is launched and only then search for a new synchronization position, this will lead to large losses of received information.

However, when working in communication channels where synchronization failures in code combinations occur relatively rarely, the method described in [9] will not ensure minimization of losses in the event of relatively rare synchronization failures during long-term communication sessions. Moreover, there will be relatively frequent false detections of synchronism, since in the established synchronization mode of code combinations it is not provided, as recommended in [6], blocking the output synchronization signal of the decision node arriving at the reset input of the frame pulse shaper after detecting a new temporary position of the boundaries code combinations or synchronization positions.

Of the known methods for synchronizing code combinations, the closest in essence to the problems being solved and the majority of the same essential features is the method for synchronizing code combinations, set out in [10], the prototype of which is the method discussed above, described in [9].

In accordance with this method, a sequence of clock pulses and a binary sequence of n-symbol code combinations containing an n-symbol cyclic synchronization signal, which is a synchronization group of m = n sync symbols, which is repeated every L n-symbols, are supplied to the clock and information inputs of the synchronization signal identifier, respectively. code combinations, with cycle duration N = n + n⋅L binary symbols. The sequence of responses from the output of the synchronization signal identifier is supplied to the first inputs of the prohibition element, the first “AND” element, as well as the input of the least significant digit of the first input of the adder.

The control input of the synchronization signal recognizer is supplied in binary code with the permissible number K of undistorted synchronization symbols from the output of the block for selecting the permissible number of undistorted synchronization symbols, the address input of which is combined with the address inputs of the first and second threshold selection blocks, as well as with the output of the counter of distorted synchronization signals, to the counting input and input to reset which, respectively, pulses are supplied from the output of the prohibition element and a pulse signal from the output of the cycle counter, to the counting input of which and the second inputs of the prohibition element and the first “AND” element, a sequence of cyclic pulses is supplied from the output of the cyclic pulse shaper.

Moreover, if in any n-symbol synchronization group the number of detected synchronization symbols without errors is greater than or equal to the permissible number K of undistorted synchronization symbols, then a “single” response is formed at the output of the synchronization signal identifier, which increases the number of responses when they are summed at the synchronization time position

From the output of the adder, a binary signal in parallel code is supplied to the signal input of a shift register block, consisting of z N-bit shift registers, which separately combine clock inputs and reset inputs, which are respectively the clock input and reset input of the shift register block, and the signal inputs , the outputs of the first bits and the outputs of the last bits of all shift registers are, respectively, a signal input, an additional output and the output of a block of shift registers, which is supplied to the second input of the adder. The clock input of the shift register block is combined with the corresponding inputs of the clock signal identifier, the decision node and the cyclic pulse shaper.

The shift register block ensures that the results of counting responses are stored at each position of the cycle in the form of z-bit binary numbers during the duration of each cycle, while the value of z determines the memory capacity of the counting results. The results of counting responses at each position of the cycle from the additional output of the shift register block sequentially with the frequency of clock pulses are supplied to the signal input of the decision node, where the input binary number in the parallel code is simultaneously supplied to the first inputs of the subtraction block, memory block and the first comparison block, in which the input number is compared with a binary number stored in the memory block and, if it exceeds the number of the memory block, then at the output of the first comparison block a pulse is generated that ensures that a new (input) number is written to the memory block, into which the largest current counting result of responses to which one is rewritten -position of the cycle, which is then compared with the calculation results at subsequent positions of the cycle. The resulting difference between the number of the memory block and the input number at the output of the subtraction block in the form of a binary number in parallel code is fed to the first input of the second comparison block, in which it is compared with the pore number M arriving at its second input (which is the control input of the decision node) from the output the first threshold selection block. In this case, if the number from the output of the subtraction block is less than the threshold number M, then a “single” (inhibiting) level will be sent from the output of the second comparison block to the reset input of the comparison counter, setting and holding it in the “zero” state. Otherwise, if the largest number written into the memory block in any j-th clock interval and corresponding to the result of accumulation at the j-th position of the cycle is not less than the threshold number M, each of the subsequent numbers arriving one after another from the additional output block of shift registers, then the comparison counter will count consecutive N-1 clock pulses coming from the clock input of the decision node, after which a pulse synchronization signal is generated at the output of the comparison counter, which is supplied to the first input of the second “AND” element, from the output of which a pulse a synchronization signal is supplied to the output of the decision node if a “single” level is supplied to the second input of the second “AND” element, which is an additional control input of the decision node. From the output of the decision node, a pulse synchronization signal is supplied to the reset inputs of the memory block, the shift register block, as well as to the reset inputs of the counter upon exiting synchronization through the “OR” element and the cyclic pulse shaper. As a result, the memory block, the shift register block and the synchronization output counter are reset to zero, and the frame pulse shaper is phased in accordance with the synchronization time position. In this case, from the output of the counter at the exit from synchronism, a “zero” level is supplied to the additional control input of the decision node, which is the second input of the second “AND” element, and the output pulse synchronization signal of the decision node is blocked, which means that synchronization of the code combinations is restored.

The blocking of the synchronization signal at the output of the decision node is removed only when a failure in the synchronization of the code combinations is detected and a “single” level is received from the counter output at the output from synchronization. Synchronization failure is detected when the synchronization output counter sums up the following pulses in a row from the output of the prohibition element, corresponding to the missing responses at the output of the synchronization signal identifier. The number of consecutive pulses from the output of the prohibition element is set by the threshold number of the counting coefficient α, supplied from the output of the second threshold selection block to the control input of the counter upon exiting synchronism, which limits the counting coefficient of the counter to the value α.

For a current assessment of the degree of distortion of the received signal, the number R of distorted sync groups is counted with a counter of distorted sync symbols during the counting of a fairly large number of cyclic pulses Q with a cycle counter and the probability (frequency) of erroneous reception of a sync group is determined with a certain degree of accuracy using the formula P _os ≈ R/Q.

The block for selecting the permissible number of undistorted synchronization symbols, the first block for selecting the threshold and the second block for selecting the threshold, depending on the value of the number R recorded in the counter of distorted synchronization symbols, select, respectively, a certain permissible number K of undistorted synchronization symbols for the sync signal recognizer, the threshold number M for the decision node and the threshold number of the counting coefficient α for the counter upon exiting synchronism. The selected numbers K, M, α from the outputs of the corresponding blocks in the parallel code are respectively supplied to the control input of the synchronization signal identifier, to the control input of the decision node and to the control input of the counter upon exiting synchronism.

However, this method of synchronizing code combinations has the following disadvantages.

1. This method requires the introduction of a cyclic synchronization signal into the transmitted information binary sequence of n-character code combinations (periodically repeated through L n-character code combinations of the n-character synchronization group) to determine the boundaries of the code combinations on the receiving side. Accordingly, it is necessary to increase the transmission speed due to the introduction of redundant synchronization symbols into the original information sequence of code combinations in order to maintain the capacity of the communication channel and to modify the transmitting equipment. In addition, an increase in transmission speed leads to a decrease in the duration of binary symbols and a decrease in the noise immunity of information reception [1].

2. The responses of the sync signal identifier to sync groups of n sync symbols are used as a source of synchronization information extracted from the received binary signal. In this case, distortion of n – K sync symbols is allowed, where K is the number of undistorted sync symbols, and their correction by inverting or generating a response of the sync signal recognizer only to K undistorted sync symbols to obtain a larger number of sync recognizer responses at the synchronization positions. However, this increases the likelihood of false detection of synchronism, since false synchronization symbols are also subject to correction. Moreover, the smaller the number of sync symbols m in a sync group, the less likely it is to reduce the synchronization recovery time in relation to the method without correction of sync groups. For example, when m < 3, this correction method does not make sense. Therefore, the number of sync symbols in a sync group is chosen to be quite large; for example, when simulating the operation of a device that implements this method, a 9-symbol sync group (000111011) was used [10]. However, the more sync symbols m in a sync group, the longer the cycle duration T _c = N (in the number of binary symbols) must be so that the increase in information transmission speed due to the introduction of a cyclic sync signal is relatively small. In [10], when modeling the operation of a device that implements this method, the cycle duration or the number of binary symbols (positions) in one cycle is chosen to be N=1200.

The time to restore synchronism is measured in cycles or cycle intervals (CI) [5], therefore the duration of the CI mainly determines the time to restore synchronism. Accordingly, when implementing this method, a large amount of time is required in the number of binary symbols R=NG _BC to restore synchronism, where G _BC - time to restore synchronism in the DI, due to which a large block of information symbols is lost with each synchronization failure.

3. To reduce the time to restore synchronization of code combinations, it is necessary to determine synchronization failure with high reliability and in the shortest possible time. In addition, after synchronism is restored, it is necessary to block the output of the decision node of the device in order to increase the noise immunity of the device by eliminating false detection of synchronism (false activation of the decision node) [6].

In a device that implements this method, synchronization failure is determined in a far from optimal way. If synchronization fails, the counter at the exit from synchronization sums up the following pulses in a row from the output of the prohibition element, corresponding to the missing responses to prohibited code combinations. However, any falsely received synchronization group, the response from which coincides in time with the cyclic pulse of the cyclic pulse shaper, a single symbol 1 from the output of the first “AND” element through the first input of the “OR” element is supplied to the reset input of the specified counter, resetting its contents. As a result, the counting of successive pulses from the output of the prohibition element begins anew. This can be repeated until the counter, upon exiting synchronism, counts the specified number of consecutive pulses from the output of the prohibition element. And only after that, from the output of this counter to the additional control input of the decision node, a “single” logical level - log - will be received. 1, allowing the search for a new cyclic phase of the input signal (new synchronization time position). This can significantly increase the synchronization recovery time.

On the other hand, such an algorithm for the operation of the counter upon exiting synchronism does not lead to an increase in the reliability of establishing synchronization of code combinations, since the pulse synchronization signal from the output of the decisive node phases the cyclic pulse shaper and simultaneously enters through the “OR” element to the input of the counter, resetting it to zero, and the inhibiting “zero” level from its output blocks the output of the decision node, which may mean that synchronism has been restored (false).

4. When a synchronization failure of code combinations is detected, the memory block of the decision node and the shift register block are not reset, which creates conditions for false detection of synchronism. Because a false synchronization detection may occur on one of the synchronization failures in the most likely initial search time interval after the detection of a synchronization failure. During this time interval, the residual information corresponding to the previous synchronization position is stored in the shift register block and the decision node memory block. New information corresponding to the new synchronism position is superimposed on the previous information, which violates the optimal search algorithm [6], and during this time interval a false detection of synchronism is most likely.

The problems to be solved by the present invention - a method for synchronizing code combinations - are:

1. Increasing the noise immunity of receiving code combinations by eliminating the transmission together with the basic information of the cyclic synchronization signal and with a corresponding decrease in the information transmission rate.

2. Reducing the synchronization search time by reducing the cycle duration to the duration of the code combination and optimizing the process of detecting synchronization restoration with the required reliability, taking into account the probability of erroneous reception of the code combination of the input binary sequence.

3. Reducing the probability of false detection of synchronization of code combinations by erasing the previous accumulated synchronization information in the block of shift registers and in the memory block of the decision node after detecting a synchronization failure.

4. Reducing the loss of binary information during synchronization failures by optimizing the processes of failure detection and restoration of synchronization of code combinations.

The solution to the problems is achieved by the fact that in the known method of synchronizing code combinations, according to which a binary sequence of n-symbol code combinations of a uniform code with error detection or correction is supplied to the information input of a synchronization signal recognizer, the output signal of which is supplied to the first inputs of the prohibition element and the first element “AND”, as well as to the input of the least significant digit of the first input of the adder, the output signal of which in parallel z-bit binary code is supplied to the signal input of the shift register block, the main and additional outputs of which are connected, respectively, to the second input of the adder and the signal input of the decision node, clock the input of which is combined with the corresponding inputs of the shift register block and the cyclic pulse shaper, the output sequence of cyclic pulses of which is supplied to the second inputs of the first prohibition element and the first “AND” element, as well as to the input of the cycle counter intended for periodic counting of Q cyclic pulses, while the shift register block includes z n-bit shift registers, which separately combine clock inputs and reset inputs, which are respectively the clock input and reset input of the shift register block, and the input and output bits, as well as the outputs of the input bits of all z n- bit shift registers of the shift register block are respectively the signal input, output and additional output of the shift register block, and when each clock pulse arrives at the clock input of the shift register block, the input bits z of the n-bit shift registers of this block are rewritten from the output of the adder in parallel z- bit binary code, the result of the summation of symbols 1 at the corresponding one of the n positions of the cycle with the corresponding serial number i = 1, 2, ..., n, in addition, the results of the summation of symbols at each of the n positions of the cycle from the additional output of the shift register block are fed sequentially to time with the frequency of clock pulses to the signal input of the decision node, the signal input of which is the first input of the first subtraction block, combined with the first input of the first comparison block and the data input of the first memory block, the output of which is combined with the second inputs of the first subtraction block and the first comparison block, in which two numbers are compared at its inputs, and if in the corresponding clock interval the number at the first input of the first comparison block exceeds the number at its second input, then a pulse signal is generated at the output of the first comparison block, which is sent to the control input of the first memory block, providing rewriting into it of the largest number arriving at its data input and the first inputs of the first comparison block and the first subtraction block, from the output of which binary numbers follow with the frequency of clock pulses and corresponding to the difference in numbers between the largest number from the output of the first memory block and each number, arriving at the first input of the first subtraction block is fed to the first input of the second comparison block, in which the binary numbers corresponding to the difference in numbers are compared with the threshold number M arriving at its second input, which is the control input of the decision node, from the output of the first threshold selection block, the address input of which is combined with the address input of the second threshold selection block, while the logical level from the output of the second comparison block is supplied to the reset input of the comparison counter, the clock input of which is the clock input of the decision node, and if at one of the n positions of the cycle the result of the summation of symbols 1 exceeds the result of the summation of symbols 1 at any other position of the cycle by at least the threshold number M in the parallel binary code, then a permissive “zero” level is applied to the reset input of the comparison counter, and using the comparison counter, n-1 clock pulses are counted and its output generates a pulse synchronization signal, which is supplied to the first input of the second “AND” element, the second input and output of which are, respectively, the first additional control input and output of the decision node, and if the first additional control input of the decision node receives a “single” logical level, then the pulse synchronization signal from the output of the decision node is supplied to the first input of the first “OR” element and to the reset input of the cyclic pulse shaper, confirming or correcting the phase of the output sequence of cyclic pulses, additionally introducing the second “OR” element, the first trigger and the first series connected an accumulating adder, a third comparison unit and a first pulse shaper, in addition. additionally, a second subtraction block, a second accumulating adder, a fourth comparison block and a second pulse shaper are introduced in series, as well as the first and second delay elements and the third accumulating adder, the output of which is connected to the data input of the second memory block, while in the code combination synchronization mode the a certain time relationship between the sequence of responses from the output of the sync signal identifier to the allowed code combinations and regularly following cyclic pulses from the output of the cyclic pulse shaper, which is called synchronous, in which each response of the sync signal identifier, duration Δτ ₁ ≤ T, where T is the duration of the cyclic pulse or clock interval, must coincide in time with the corresponding cyclic pulse of the cyclic pulse shaper in an interval of duration Δτ ₂ ≤ Δτ ₁ , while at the output of the first element “AND” either a single binary symbol 1 with a duration of Δτ ₂ will appear in the presence of a response from the synchronization signal identifier, when the corresponding enabled the code combination of the input binary sequence is not distorted, or a single symbol 0 with a duration of Δτ ₂ in the absence of a response from the sync signal identifier, when the corresponding allowed code combination is distorted, and at the output of the first prohibition element a single symbol 1 will appear with a duration of Δτ ₂ in the absence of a response from the sync signal identifier, when the corresponding the allowed code combination is distorted, or a single symbol 0 with a duration of Δτ ₂ in the presence of a response from the synchronization signal identifier, when the corresponding allowed code combination is not distorted, while from the output of the first prohibition element a sequence of single symbols 1 and 0 is supplied to the inputs of the low-order bits of the signal inputs of the first and third accumulating adders, symbols 0 are supplied to the remaining bit inputs of the signal inputs of these accumulating adders by connecting them to the source of the “zero” level, therefore, at the signal input of each of these accumulating adders, the incoming symbols 1 or 0 form the binary number one or the binary number zero in a parallel code with symbols “1” and “0”, each with a duration of Δτ ₂ , respectively, while using the third accumulating adder, the summation of sequentially arriving single binary numbers “1” is carried out, corresponding to the distorted allowed code combinations during Q cycles, counted by the cycle counter, at the end counts of which a pulse is formed at its output, which is fed to the control input of the second memory block, ensuring rewriting and storing the new counting result R of distorted allowed code combinations, from the output of the third accumulating adder, after which the third accumulating adder is reset by applying a pulse with to its reset input the output of the cycle counter, delayed in the first delay element, and the counting of distorted code combinations by the third accumulating adder is repeated over the next Q cycles, while to ensure the summation of single binary numbers “1” of duration Δτ ₂ each, arriving at the signal inputs of the accumulating adders, to the inputs synchronization of each of the three accumulating adders, pulses delayed in the second delay element are supplied from the output of the cyclic pulse shaper, coinciding in time with pulses from the outputs of the first “AND” and prohibition elements, the current result of counting distorted code combinations from the output of the second memory block in parallel binary code additionally is supplied to the address input of the second threshold selection block, combined with the address input of the first threshold selection block, and based on the measured value, estimates the error probability of the allowed code combination the value of which is within the corresponding one of intervals of permissible values of the P _ORK value, the corresponding threshold numbers Mr and W _r are formed for the first and second threshold selection blocks in parallel binary code with the corresponding gradation number of each threshold number wherein the threshold number Mr from the output of the first threshold selection block is supplied to the control input of the decision node, the pulse synchronization signal of which, through the first input of the first “OR” element, is supplied to the reset input of the first memory block, which is the second additional control input of the decision node and the reset input of the shift register block , resetting them, at the same time, a pulse synchronization signal is additionally supplied through the third input of the second “OR” element to the reset inputs of the first and second accumulating adders, resetting them to zero, after which the reliability of restoring the synchronization of code combinations is determined, for this purpose a sequence of single symbols 1 and 0 from the output of the first element “AND” is supplied to the input of the least significant digit of the first input of the second subtraction block, and another sequence of single symbols 0 and 1 from the output of the first prohibition element is supplied to the input of the least significant digit of the second input of the subtraction block, and the remaining bit inputs of the first and second inputs of the second subtraction block are supplied symbols 0 by connecting them to the source of the “zero” level, while at each of the inputs of the second subtraction block, the incoming symbols 1 or 0 together with the remaining 0 symbols at other bit inputs form, as at the signal inputs of the first and third accumulating adders, a binary number “1” or binary number “0” in a parallel code with duration Δτ ₂ , while the binary number “1” or “0” with duration An at the first input of the second subtraction block is subtrahendable, and the binary number “0” or “1” with duration Δτ ₂ at the second input of the subtraction block is minible, while at the output of the second subtraction block either the first result of the subtraction will appear: “1” - “0” = “1” - plus one in the parallel binary code, if the corresponding allowed code combination is not distorted, or the second result of subtraction: “0” - “1” = - “1” - minus one in the parallel binary code, if the corresponding allowed code combination is distorted, and if, after detecting a synchronization failure and searching for a new synchronization position, the pulse synchronization signal from the output decision node sets the phase of the output sequence of pulses of the cyclic pulse shaper to the required synchronous state corresponding to the new synchronism position, then from this point in time the probability of the appearance at the output of the first element “AND” of a single symbol 1, corresponding to an undistorted or correctly accepted allowed code combination P _PRK becomes greater than the probability of the appearance at the output of the first prohibition element of a single symbol 1, corresponding to a distorted or accepted with errors allowed code combination P _ORK with the probability of error of a binary symbol of a sequence of code combinations P _OS > 0.5, while using the second accumulating adder, single positive numbers are summed “1”, corresponding to the number of undistorted allowed code combinations that arrive at its signal input and subtracting from them the sum of single negative numbers - minus “1”, corresponding to the number of distorted allowed code combinations, and using the first accumulating adder, the summation of single positive numbers “ 1", corresponding to the number of distorted allowed code combinations that arrive at its signal input, the counting results from the outputs of the first and second accumulating adders are supplied to the first inputs of the third and fourth comparison blocks, respectively, to the second inputs of which the threshold number W _r is supplied from the output of the second block choosing a threshold, while the second accumulating adder, in comparison with the first accumulating adder, will reach the result of counting the set threshold number W _r first, since , as a result, the fourth comparison block will be the first to operate, the voltage drop from the output of which is supplied to the input of the second pulse shaper, the output pulse signal of which is supplied through the second input of the second “OR” element to the reset inputs of the first and second accumulating adders, resetting them to zero, and the process of counting single binary numbers “1” are repeated, at the same time the pulse signal of the second pulse shaper is supplied to the second input of the first trigger, setting it to the “zero” state, from the output of which the prohibiting “zero” level is supplied to the first additional control input of the decision node, blocking the output synchronization signal and thereby confirming the reliability of restoring the synchronization of code combinations, if the synchronization of code combinations fails, the synchronous time relationship between the sequence of responses at the output of the synchronization signal recognizer to the allowed code combinations and regularly following cyclic pulses from the output of the cyclic pulse shaper is disrupted, in this state the probability of the appearance of the first element at the output “And” of each single symbol 1 with duration Δτ ₂ corresponding to a false allowed code combination is equal to Where accordingly, the number of allowed code combinations and the total number of allowed and prohibited code combinations is less than the probability of the appearance at the output of the first prohibition element of each single symbol 1 of duration Δτ ₂ corresponding to the prohibited code combination, which is equal to and since then the first accumulating adder, in comparison with the second accumulating adder, will reach the counting result of the set threshold number W _r , first, as a result, the third comparison unit will be the first to operate, the voltage drop from the output of which is supplied to the input of the first pulse shaper, the output pulse signal of which is supplied through the first input of the second element "OR" to the reset inputs of the first and second accumulating adders, resetting them to zero, and the process and process of counting single binary numbers "1" are repeated, at the same time the pulse signal from the output of the first pulse shaper is fed through the second input of the first element "OR" to the second additional control the input of the decision node and the reset input of the shift register block to reset the first memory block of the decision node and the shift register block, after which the search for a new temporary position of the synchronization position begins, the pulse signal from the output of the first pulse shaper is also supplied to the first input of the first trigger, setting it to "single" state, thereby confirming the detection of a synchronization failure of code combinations, from the output of the first trigger the enabling "single" level is supplied to the first additional control input of the decision node, removing the blocking from the output of the second element "AND" and from its output the pulse synchronization signal can be supplied to output of the decision node after detecting a new synchronicity time position.

In addition, the synchronization signal recognizer contains a third delay element, a control pulse shaper, a control counter, a decoder, a third “OR” element and a second trigger connected in series, the first output of which is supplied to the control counter reset input, the other input of the second trigger is connected to the input of the fourth delay element , the output of which is connected to the first input of the third trigger, the output of which is the output of the synchronization signal identifier, the clock input and additional output of which are, respectively, the input and output of the third delay element, the output of which is additionally connected to another input of the second trigger, in addition, the sync signal identifier contains n- bit shift register with serial numbers of bits i = 1, 2, ..., n, corresponding to the order of their sequence - from the most significant output bit - for i = 1, to the least significant input bit, which is the information input of the clock signal recognizer - for i = n, block memory of allowed code combinations (BPRCK) with similar serial numbers n outputs corresponding to the order of binary symbols with serial numbers i = 1, 2, ..., n in each code combination of the input signal, the address input of which is additionally connected to the output of the control counter, as well as n elements of equivalence with the same serial numbers i = 1, 2, ..., n, and the third element “AND”, the output of which is connected to the first input of the second prohibition element, the second input of which is additionally connected to the output of the control pulse shaper, and the output of the second element prohibition is combined with another input of the third element "OR" and the second input of the third trigger, the first and second inputs of each element of equivalence with the corresponding serial number i are connected, respectively, to the bit output with the same serial number i of the n-bit shift register and the output of the BPRKK with the same serial number i, and the outputs of all n elements of equivalence are connected to the corresponding n inputs of the third element “AND”, the (n + 1)th input of which is connected to the second output of the second trigger.

A comparative analysis with the prototype shows that the introduction of significant distinctive features constitutes a novelty and allows, as will be shown below, to solve the assigned problems.

Let us consider the effectiveness of the proposed invention using the example of the functioning of a code combination synchronization device for receiving a binary sequence encoded with a hypothetical uniform code (5,2), the electrical structural diagram of which is shown in Fig. 1. Figure 2 shows timing diagrams of the device operation.

The code combination synchronization device contains a synchronization signal identifier 1, a first prohibition element 2 ₁ , a first “AND” element 3 ₁ , an adder 4, a block of shift registers 5, a decision node 6, a cyclic pulse shaper 7, a cycle counter 8, a first “OR” element 9 ₁ , the first threshold selection block 10 ₁ and the second threshold selection block 10 ₂ .

The clock and information inputs of the device, which are the clock and information inputs of the synchronization signal identifier 1, receive, respectively, a sequence of clock pulses and a binary sequence of n-character code combinations of a uniform hypothetical code (5,2). The output of the synchronization signal identifier 1 is combined with the first inputs of the first prohibition element 2 ₁ and the first “AND” element 3 ₁ , as well as the first input of the adder 4, the output of which is connected to the signal input of the shift register block 5, the main and additional outputs of which are connected, respectively, to the second input adder 4 and the signal input of the decision node 6, the clock input of which is combined with the corresponding inputs of the shift register block 5 and the cyclic pulse shaper 7, the output of which, which is the output of the device, is combined with the second inputs of the first prohibition element 2 ₁ , the first “AND” element 3 ₁ and with the input of the cycle counter 8. The reset input of the cyclic pulse shaper 7 is combined with the first input of the first “OR” element 9 ₁ and the output of the decision node 6, the control input of which is connected to the output of the first threshold selection block 10 ₁ , the address input of which is combined with the address input the second block for selecting the threshold 10 ₂ .

The decision node 6 consists of the first comparison block Hi, the first memory block 12 ₁ , the first subtraction block 13 ₁ , the second comparison block 11 ₂ , the comparison counter 14 and the second element “AND” 3 ₂ , and the signal input of the decision node is the first input of the first block subtraction 13 ₁ , combined with the data input of the first memory block 12 ₁ and the first input of the first comparison block 11 ₁ , the output of which is connected to the control input of the first memory block 12 ₁ , the output of which is combined with the second inputs of the first comparison block 11 ₁ and the first subtraction block 13 ₁ , the output of which is connected to the input of the second comparison block 11 ₂ , the output of which is connected to the reset input of the comparison counter 14, the output of which is connected to the first input of the second element “AND” 3 ₂ , the output of which is the output of the decision node 6, control, clock and first the additional control inputs of which are, respectively, the second input of the second comparison block 11 ₂ , the clock input of the comparison counter 14 and the second input of the second element “AND” 3 ₂ .

The device also contains a second “OR” element 9 ₂ , a first trigger 15 ₁ and a series-connected first accumulating adder 16 ₁ , a third comparison unit 11 ₃ and a first pulse shaper 17 ₁ , the output of which is combined with the second input of the first “OR” element 9 ₁ and the first inputs of the second element "OR" 9 ₂ and the first trigger 15 ₁ , the output of which is connected to the first additional control input of the decision node 6, the second additional control input of which, which is the reset input of the first memory block 12 ₁ of the decision node 6, is combined with the reset input of the block shift registers 5 and the output of the first element “OR” 9 ₁ .

In addition, the device contains a second subtraction block 13 ₂ , a second accumulating adder 16 ₂ , a fourth comparison block 11 ₄ and a second pulse shaper 17 ₂ connected in series, the output of which is combined with the second inputs of the first trigger 15 ₁ and the second “OR” element 9 ₂ . the output of which is combined with the reset inputs of the first and second accumulating adders (16 ₁ , 16 ₂ ).

The device also contains the first and second delay elements (18 ₁ , 18 ₂ ), as well as a third accumulating adder 16 ₃ , the output of which is connected to the data input of the second memory block 12 ₂ , the control input of which is combined with the output of the cycle counter 8 and the input of the first delay element 18 ₁ , the output of which is connected to the reset input of the third accumulating adder 16 ₃ , and the output of the second memory block 12 ₂ , is additionally connected to the address input of the second threshold selection block 10 ₂ , the output of which is combined with other inputs of the third and fourth comparison blocks (11 ₃ , 11 ₄ ), the synchronization inputs of the first, second and third accumulating adders (16 ₁ , 16 ₂ , 16 ₃ ) are combined with the output of the second delay element 18 ₂ , the input of which is additionally connected to the output of the cyclic pulse shaper 7, the clock input of which is additionally connected to additional output of the synchronization signal identifier 1, the output of the first element “AND” 3 ₁ is connected to the first input of the second subtraction block 13 ₂ , the second input of which is combined with the output of the prohibition element 2 ₁ and the signal inputs of the first and third accumulating adders (16 ₁ , 16 ₂ ).

The clock signal recognizer 1 contains a series-connected third delay element 18 ₃ , a control pulse shaper 19, a control counter 20, a decoder 21, a third “OR” element 9 ₃ and a second trigger 15 ₂ , the first output of which is connected to the reset input of the control counter 20, and the other the input of the second trigger 15 ₂ is connected to the input of the fourth delay element 18 ₄ , the output of which is connected to the first input of the third trigger 15 ₃ , the output of which is the output of the synchronization signal identifier 1, the clock input and additional output of which are, respectively, the input and output of the third delay element 18 ₃ , the output of which is additionally connected to another input of the second trigger 15 ₂ ,

In addition, the sync signal identifier 1 contains an (n = 5)-bit shift register 22 with the serial numbers of the bits i = 1, 2, ..., 5, corresponding to the order of their sequence - from the most significant output bit - with i = 1, to the least significant input bit , which is the information input of the synchronization signal recognizer - with i = 5, a memory block of allowed code combinations (BPRCK) 23 with similar serial numbers of outputs corresponding to the order of binary symbols with serial numbers i = 1, 2, ..., 5 in each code combination of the input signal, the address input of the BPRKK is additionally connected to the output of the control counter 20, as well as n = 5 elements of equivalence (24 ₁ , ..., 24 ₅ ) with the same serial numbers i = 1, 2, ..., 5, and the third element “AND” 3 ₃ , the output of which is connected to the first input of the second prohibition element 2 ₂ , the second input of which is additionally connected to the output of the control pulse shaper 19, and the output of the second prohibition element 2 ₂ is combined with another input of the third “OR” element 9 ₃ and the second input of the third trigger 15 ₂ , the first and second inputs of each element of equivalence (24 ₁ , ..., 24 ₅ ) with the corresponding serial number i are connected, respectively, to the bit output of the 5-bit shift register 22 with the same serial number i and the output of the BPRKK 23 with the same serial number i, and the outputs of all 5 elements of equivalence (24 ₁ , ..., 24 ₅ ) are connected to the corresponding 5 inputs of the third element “AND” 3 ₃ , the 6th input of which is connected to the second output of the second trigger 15 ₂ .

The code combination synchronization device operates as follows.

The received binary sequence, encoded with a hypothetical uniform 5-symbol code (5,2), selected for a more visual representation of the operation of the device, is fed to the information input of the 5-bit shift register 22, which is the information input of the sync signal identifier 1 and the device (Fig. 1) generally. Here, each code combination contains n=5 binary symbols with serial numbers i = 1, 2, ..., 5, of which k = 2 information symbols and n - k = 3 check (correction) symbols.

Figure 2 shows timing diagrams of the device operation when receiving a segment of a binary sequence consisting of two consecutive allowed code combinations of a hypothetical code (5,2) of the form: 11011 and 01011 (Figure 2, b) from N _o =2 ^k =4 possible allowed code combinations, for example, with conditional sequence numbers j=1,2,3,4: 1) 00110, 2) 10011, 3) 11011, 4) 01011. Here, out of the total number N _total - 2 ⁿ =32 possible code combinations N _total - N _o - 28 are prohibited. In this case, a sequence of N ₀ <N _generally allowed code combinations is used as a source of cyclic synchronizing information, and the duration of each cycle T _c is equal to the duration of one code combination, i.e. T _c =n (binary characters).

Under the influence of clock pulses (TI) arriving at the clock input of the clock signal identifier 1 (Fig. 2, a), the input binary sequence (Fig. 2, b) advances through the bits of the 5-bit shift register 22 with the serial numbers of the bits i = 1, 2,5,4,5. In Fig. 2, the synchronous state of the first cycle T _c1 of the input binary sequence is recorded in the bits of the 5-bit shift register 22 after the arrival of the corresponding 1st clock pulse (Fig. 2, a), when the 1st binary symbol of the first code The combination is placed in the 1st bit of the shift register 22, the 2nd symbol is in the 2nd bit of this shift register, etc. Thus, the code combination of the first cycle T _c1 with a conditional sequence number j = 3, i.e. . 3) 11011, is completely located in the bits of the 5-bit shift register 22. After the arrival of the next TI of this cycle, the following code combination of the second cycle T _c2 will be in the synchronous state (in the 5-bit shift register 22). - 4) 01011, etc. Moreover, in each of the elements of equivalence 24 ₁ , ..., 245 with serial number i = 1,2,5,4,5, in which the bit output of the 5-bit shift register 22 with the same serial number and output of the memory block of allowed code combinations (BPRKK) 23 with the same serial number, the values of the logical levels (voltages) of the i-th character (0 or 1) of the code combination of the shift register 22 and the i-th character of each of the N _o allowed code combinations are compared , sequentially switched in BPRKK 23 within the corresponding clock interval of duration T (Fig. 2, a).

BPRKK can consist, for example, of N _o n-bit storage registers [11], each of which is assigned a conditional serial number j=1,2,..., N _o with a corresponding address in digital form, and the bits of each of which with serial numbers numbers similar to the serial numbers of the bits of the n-bit shift register 22, the corresponding allowed code combination with a conditional serial number j and serial numbers of symbols coinciding with the serial numbers of the bits in which they are written are written character by character. When the selected address j is received at the address input of the BPRKK in digital form, the n bit outputs of the corresponding j-th storage register are connected using switching devices to the corresponding n outputs of the BPRKK, the serial numbers of which coincide with the serial numbers of the bits of each of the n-bit storage registers.

A reprogrammable read-only memory (PROM) can also be used as a BPRKK, in the n-bit memory cells of which the permitted code combinations are written (flashed), taking into account the order in which the code combination symbols are written, as set out above. Various modifications of PROMs are widely produced by industry in many countries around the world in the form of integrated circuits.

Under the control of the control counter 20, sequential switching of the logical levels of the corresponding symbols of allowed code combinations in a parallel code is carried out to the outputs of the BPRKK, each of which is recorded in the corresponding n-bit memory cells of the BPRKK at the corresponding address. To do this, when each clock pulse (TI) arrives from the output of the third delay element 18 ₂ (Fig. 2, d), delayed by a certain amount τ relative to the TI of the input sequence of clock pulses (Fig. 2, a), at the output of the control pulse shaper 19 a sequence of N _o +1=5 control pulses is formed (Fig. 2, d) within each clock interval of duration T (Fig. 2, a).

The formation of a sequence of control pulses in the control pulse shaper 19 can be carried out, for example, using D=2N _o +1 identical series-connected single pulse shapers with serial numbers d=1,2,3,...,D. Moreover, each subsequent single pulse shaper of selected duration 2τ (Fig. 2, d) is launched from the trailing edge of the pulse generated by the previous single pulse shaper, the first of which with serial number d=1, is launched from the corresponding TI from the output of the third delay element 18 ₃ (Fig. 2, d). In this case, the output of each single pulse shaper with an odd serial number must be connected to the corresponding input of the “OR” element, the output of which must be the output of the control pulse shaper 19, forming a sequence of N _o +1-5 control pulses. Each single pulse shaper can be made, for example, based on a multivibrator. Other options for implementing the driver 19 are also possible.

In the initial state (before the arrival of the next TI from the output of the third delay element 18 ₃ ), the second trigger 15 ₂ is set to the “single” state, in which from its first output the “single” logical level - log - is supplied to the reset input of the control counter 20. 1. In this case, the control counter 20 is set to the “zero” state, in which a “zero” logical level is fixed at each of its bit outputs, the totality of which forms the digital control output. 0. This “zero” control digital signal (“000”) in parallel code, formed in this case from the three bit outputs of the control counter 20, is supplied to the address input of the decoder 21 and BPRKK 23, which connects the logical levels of the 5-character code combination in parallel code, which turned out to be written into an n-bit memory cell at the “zero” address. In this case, the third element “I” 3 ₃ does not work for any code combination written in BPRKK 22 at the “zero” address - a log is stored at its output. 0, since it is blocked by the “zero” logical level (log.0), at the 6th input of this element (blocking input), coming from the second output of the second trigger 15 ₂ .

Each regular clock pulse from the output of the third delay element 18 ₃ sets the second trigger 15 ₂ to the “zero” state - log.0, at its first output (Fig. 2, g) and log. 1 - on the second output. As a result, a log will be sent to the reset input of control counter 20. 0, allowing the counting of control pulses arriving at its clock input. At the same time, log.1 will be received at the 6th input (blocking input) of the third element “AND” 3 ₃ , allowing its operation - the formation of a log. 1 at its output in the presence of log.1 at each of its other 5 inputs from the outputs of the corresponding elements of equivalence 24 ₁ ,...,24 ₅ . In addition, each regular clock pulse triggers, in the corresponding clock interval, the formation of a sequence of N _o +1=5 control pulses from the output of the control pulse shaper 19 (Fig. 2, e). Control counter 20 in each clock interval with the arrival of the first control pulse counts one pulse - at its three bit outputs a control digital signal “001” is generated in binary code, according to which BPRKK 23 provides switching to its 5 outputs of logical levels of the corresponding symbols of the allowed code combination , stored in an n-bit memory cell with a conditional serial number j=1, i.e. 1) 00110 (Fig. 2, h, i, j, l, m). The logical levels of the symbols of this combination are compared in the elements of equivalence 24 ₁ , ..., 24 ₅ with the logical levels of the corresponding symbols of the code combination located in a given clock interval in the corresponding bits of the 5-bit shift register 22, i.e. 11011 (Fig. 2, c). If in at least one of the elements of equivalence 24 ₁ ,…,24s there is a mismatch of logical levels at its inputs, then a log will appear at the output of this element. 0, which blocks the operation of the third element “AND” 3 ₃ . Accordingly, a log will be recorded at the output of this element “AND” 3 ₃ . 0, arriving at the first input of the second prohibition element 2 ₂ , at which a log will also be recorded at its output. 0 for any value of the logical level at its other input. In this case, the state of the second trigger 15 ₂ will not change, since the output of the third “OR” element 9 ₃ will also be log.0.

When the 2nd control pulse (Fig. 2,.d) arrives at the input of the control counter 20, the number 2 in the binary code “010” will appear at its bit outputs, according to which the BPRKK 23 will provide switching to its outputs of the logical levels of the corresponding symbols of the allowed code combination recorded in its memory with a conditional serial number j=2, i.e. 2) 10011 (Fig. 2, h, i, j, l, m). Some symbol levels of this code combination, as well as the previous code combination, do not coincide with the symbol levels of the compared code combination (11011), as a result, “zero” logical levels (log.0) are fixed at the outputs of the corresponding equivalence elements 24 ₁ ,…, 24 ₅ , any of them blocks the operation of the third element “AND” 3 ₃ , and the state of the second trigger 15 ₂ will also not change.

When the 3rd control pulse arrives from the output of the control pulse shaper 19, the number 3 in the binary code “011” will appear at the output of the control counter 20, according to which the BPRKK 23 will provide switching to its outputs of the logical levels of the corresponding symbols of the allowed code combination with a conditional sequence number j =3, i.e. 3) 11011 (Fig. 2, h, d, j, l, m). The logical levels of the symbols of this code combination completely coincide with the levels of the symbols of the synchronous enabled code combination (11011), which is completely located in the bits of the 5-bit shift register 22. As a result, at the output of each element of equivalence 24 ₁ ,..., 24 ₅ , logical 1 will appear, in As a result, the third element “AND” 3 ₃ is triggered - log.1 appears at its output, which is fed to the input of the second prohibition element 2 ₂ . At the output of this prohibition element and at the output of the third element “OR” 9 ₃ (Fig. 2, e) a log will be stored. 0 until the end of the 3rd control pulse with a duration of 2τ. With the arrival of log. 0 to the second input of the second prohibition element 2 ₂ from the output of the pulse shaper 19 after the end of the 3rd control pulse, logic 1 will appear at the output of the second prohibition element 2 ₂ and at the output of the third “OR” element 93. This logic 1 sets the second trigger 15 ₂ to its initial state, resetting the control counter 20 and blocking the third element “AND” 3 ₃ , due to which logic 1 at the output of the second prohibition element 2 ₂ and the third element “OR” 9 ₃ is interrupted , and at the output of the third element “OR” 9 ₃ a narrow pulse is formed (Fig. 2, e). At the same time, at the leading edge of this pulse, the third trigger 15 ₃ is set to the “single” state, and logic 1 from its output goes to the output of the synchronization signal identifier 1. At this point, the process of detecting the allowed code combination in this (first) clock interval is considered completed, i.e. To. allowed code combination 11011 detected.

Before the arrival of the next, 2nd TI from the output of the third delay element 18 ₃ , the binary sequence in the 5-bit shift register 22 under the action of the 2nd TI at the input of the synchronization signal identifier 1 (Fig. 2, a) is shifted by one bit - to the temporary diagram (Fig. 2, d) such a shift means a shift to the left. In this case, in the bits of the 5-bit shift register 22 there will be a forbidden code combination 10110. With the arrival of the 2nd TI from the output of the third delay element 18 _3, flip-flops 15 ₂ (Fig. 2, g) and 15 ₃ are set to zero, and , the third trigger 15 ₃ (Fig. 2, o) is set to the “zero” state with a delay 4 ₂ determined by the fourth delay element 184 (Fig. 2, n). In this case, the output of the synchronization signal identifier 1 receives a pulse response generated by the third trigger 153 (Fig. 2, o), corresponding in time to the first allowed code combination of the 1st cycle T _c1 .

Simultaneously with the arrival of the 2nd TI, a process similar to the process in the previous 1st clock interval begins from the output of the third delay element 18 ₃ in the 2nd clock interval. However, since the forbidden code combination 10110, located in this clock interval in the bits of the 5-bit shift register 22, does not coincide with any allowed code combination BPRKK, then the third element “AND” 3 ₃ . does not work after each of the four control pulses (Fig. 2, d) arrives at the input of the control counter 20. Therefore, this counter begins counting the next (maximum possible) 5th control pulse. In this case, as soon as the control digital signal “101” (number 5 in binary code) appears at the output of control counter 20, to which decoder 21 reacts, a log will appear at the output of this decoder. 1. This “single” logical level, passing through the third “OR” element 9 ₃ , sets the second trigger 15 ₂ to its initial state, resetting the control counter 20, which is why logic 1 is at the outputs of the decoder 21 and the third “OR” element 9 ₃ is interrupted, and a narrow pulse is formed at the output of the third element “OR” 9 ₃ (Fig. 2, e). This means that when the 2nd TI arrives at the input of the synchronization signal identifier 1 (Fig. 2, a), a forbidden code combination is placed in the 5-bit shift register 22 during the 2nd clock interval, in this case - 10110.

Similar actions occur when the 3rd, 4th and 5th TI of the first cycle T _c1 arrives at the input of the sync signal identifier 1, except that there is no pulse response at the output of the sync signal identifier 1 (Fig. 2, o). In these cases, the following prohibited code combinations will be placed sequentially in shift register 22: 01101, 11010, 10101,

When the next TI arrives, which is the 1st clock pulse of the 2nd cycle T _Ts2 (Fig. 2, a), the allowed code combination 01011 will be placed in the 5-bit shift register 22, a copy of which is stored in the BPRKK with a conditional sequence number j =4. The detection process within the 1st clock interval of the 2nd cycle T _Ts2 in the bits of the shift register 22 of another allowed code combination 01011 is similar to the previously described process of detecting the allowed code combination 11011 within the 1st clock interval of the 1st cycle _Ts1 . The only difference is that the detection of the allowed combination 01011 occurs when the 4th control pulse arrives from the output of pulse shaper 19 (Fig. 2, d). In this case, at the output of the control counter 20 the number 4 will appear in binary code (100), according to which the BPRKK 23 provides connection to its outputs of the logical levels of the corresponding symbols of the allowed code combination with a conditional sequence number j=4, i.e. 4) 01011 (Fig. 2, h, i, j, l, m). The logical levels of the symbols of this code combination completely coincide with the levels of the symbols of the synchronous code combination (01011), which is located entirely in the bits of the 5-bit shift register 22. Further actions are similar to those described above when describing the detection of the allowed code combination 11011 upon receipt of the 3rd control pulse. In this case, the output of the synchronization signal recognizer 1 receives a pulse response generated by the third trigger 153 to the allowed code combination (Fig. 2, o), as a result, a sequence of responses to the permitted code combinations is formed at the output of the synchronization signal recognizer 1 (including possible false responses to false allowed combinations).

The sequence of responses from the output of the synchronization signal identifier 1 is fed to the first input of the adder 4. At the second input of the adder 4, from the output of the shift register block 5, binary z-bit numbers in a parallel code are supplied with a repetition clock frequency.

Adder 4 is a parallel combinational adder [11], in which the low-order bit input of the first summand and z bit inputs of the second summand are the first and second inputs of adder 4, respectively, while the other (z - 1) bit inputs of the first input are connected to the “zero” source » level.

Block 5 shift registers includes z n-bit (n is the number of positions in one cycle or the number of characters in one code combination) shift registers, which have separately combined clock inputs and reset inputs. In this case, the combined clock inputs and the combined reset inputs of the shift registers as part of the shift register block 5 are, respectively, the clock input and the reset input of the shift register block 5, and the signal inputs, outputs of the last bits and outputs of the first bits of all z shift registers are respectively the signal input, output and an additional output of shift register block 5.

Thus, the response of the clock signal identifier 1, which takes place in the i-th clock interval, is added in the adder 4 with the result of the previous response count at the i-th position of the cycle, coming from the output of the shift register block 5, and the new response count result, greater by one the former, is written as a z-bit binary number in the first digits of the z shift registers of shift register block 5.

In this case, the binary number previously written in the first bits of the shift register block 5, as well as all other numbers stored in subsequent bits of the same type, are shifted in parallel by one bit, and the following result is received from the output of the shift register block 5 to the second input of the adder 4 response counts - at the (i+1)th position of the cycle, which is rewritten to the first bits of shift register block 5, and the remaining numbers stored in the same type of bits of shift register block 5 are shifted by one bit, etc. those. shift register block 5 provides storage of the response count results at each cycle position during the cycle duration. In this case, the value of z determines the memory capacity of the calculation results.

At the same time, the results of counting responses at each position of the cycle from the additional output of the shift register block 5 are sequentially supplied to the signal input of the decision node 6. In the decision node 6, for example, at the i-th clock interval, a binary number in parallel code representing the current result of counting the responses at the i-th position of the cycle, it is simultaneously supplied to the corresponding inputs of the first comparison block 11 ₁ , the first memory block 12 ₁ and the first subtraction block 13 ₁ . In the first comparison block 11 ₁ , the input number is compared with a binary number stored in the first memory block 12 ₁ and, if it exceeds the number of the first memory block 12 ₁ , then a pulse is generated at the output of the first comparison block 11 ₁ , which is sent to the control input of the first block 12 ₁ memory, ensures erasing the previous and recording a new (input) number. After this, the inputs of the first comparison block 11 ₁ are equal binary numbers. If the input number is equal to or less than the number stored in the first memory block 12 ₁ , then the contents of the latter do not change.

Thus, the largest current counting result of responses at any position of the cycle is rewritten into the first block 12 ₁ of memory, which is then compared with the counting results at subsequent positions of the cycle.

The resulting difference (between the number of the first block 12 ₁ of memory and the input number) at the output of the first block 13 ₁ of subtraction 13 ₁ in the form of a binary number in parallel code is compared in the second comparison block 11 ₂ with the threshold number M _r arriving at its second input (which is control input of the decision node 6) from the output of the first threshold selection block 10 ₁ . Moreover, if the number from the output of the first subtraction block 13 ₁ is less than the threshold number M _r , then from the output of the second comparison block 11 ₂ a “single” (inhibiting) potential is supplied to the reset input of the comparison counter 14, which sets and holds it at “zero” condition. In the opposite case, when in the i-th clock interval the number from the output of the first subtraction block 13 ₁ is equal to or greater than the number M _r , then a “zero” (resolving) potential is received from the output of the second comparison block 11 ₂ , and the comparison counter 14 counts one clock pulse arriving at its clock input, which is the clock input of the decision node 6. Moreover, if the largest binary number written into the first memory block 12 ₁ in any j-th clock interval and corresponding to the result of accumulation at the j-th position cycle, will exceed by an amount equal to or greater than the threshold number M _r coming from the control input of the decision node, each of the n-1 subsequent numbers arriving one after another from the additional output of the shift register block 5, then the comparison counter 14 will count the next n in a row -1 clock pulses coming from the clock input of the decision node, after which a pulse synchronization signal is generated at its output. This signal arrives through the first input of the second element “AND” 3 ₂ to the output of the decision node, if its first additional decisive input, which is the second input of the second element “AND” 3 ₂ , receives a “single” logical level from the output of the first trigger 15 ₁ . From the output of the decision node 6, a pulse synchronization signal is supplied through the first input of the first OR element 9 ₁ to the reset input of the first memory block 12 ₁ , which is the second additional control input of the decision node 6, and the reset input of the shift register block 5, resetting them to zero and to the reset input of the shaper cyclic pulses 7, setting the phase of the output sequence of cyclic pulses 7 in a synchronous state with the sequence of code combinations of the input signal. Simultaneously, from the output of the decision node, the synchronization signal arrives through the third input of the second “OR” element to the reset inputs of the first and second accumulating adders, resetting them to zero. The above process of searching for the cyclic phase or the temporal position of the synchronization position of the received binary sequence with phase correction of the output cyclic pulses is carried out only when a pattern synchronization failure is detected. The processes for identifying a failure and restoring synchronization in this device will be discussed below.

The process of generating threshold numbers for the decision node 6 is carried out as follows.

The first inputs of the first prohibition elements 2 ₁ and “AND” 3 ₁ receive pulses (responses) of the synchronization signal identifier 1 (Fig. 2, o), and their second inputs receive pulses from the cyclic pulse shaper 7 (Fig. 2, p). In the synchronization mode, the joint interaction of each of these pulses occurs over a time interval of 4 tons, counted relative to the trailing edge of the pulse from the output of the synchronization signal identifier 1 (Fig. 2, o). Therefore, the duration of the output pulses of the prohibition elements 2 ₁ and “I” 3 ₁ , which must subsequently be taken into account in each cycle interval of the input signal, should not exceed a time interval of 4τ (Fig. 2, o, p, p, s, t).

In this case, at the output of the first element “AND” 3 ₁ , a single binary symbol 1 with a duration of 4τ is formed (Fig. 2, p), if the response of the synchronization signal identifier 1 is not distorted, this means that the corresponding allowed code combination is accepted correctly. Otherwise, at the output of the first element “AND” 3 ₁ instead of symbol 1 with a duration of 4τ, a symbol 0 with a duration of 4τ will appear if the response is distorted, i.e. there is no response during the action of the corresponding cyclic pulse.

At the output of the first prohibition element 2 _1, symbol 1 with a duration of 4τ is formed if the response is distorted. Otherwise, at the output of the first prohibition element 2 ₁ instead of symbol 1 with a duration of 4τ, a symbol 0 with a duration of 4τ will appear (Fig. 2, c) if the response is not distorted.

By counting the number R of distorted responses during the counting time of a fairly large number Q of the number of cyclic pulses, it is possible, with a certain degree of accuracy, to periodically determine the probability (frequency) of erroneous reception of an allowed code combination using the formula P _ORK ≈ R/Q, i.e. make a current assessment of the degree of distortion of n-element code combinations.

To do this, at the input of the least significant bit of the signal input of each of the accumulating adders 16 ₁ and 16 ₃ , either a binary symbol 0 (Fig. 2c) or a binary symbol 1, each with a duration of 4τ, is supplied from the output of the second prohibition element 2 ₂ . The remaining bit inputs of the signal inputs of the accumulating adders 16 ₁ and 16 ₃ are connected to the “zero” level source. Accordingly, the binary symbol 1 or binary symbol 0 arriving at the inputs of these devices, each with a duration of 4τ, together with the symbols 0 at the remaining bit inputs of the signal inputs, should be considered as the number one, or the number zero, each parallel in the binary code, acting on a time interval of 4τ s symbolized by “1” and “0” respectively. Each of the accumulating adders 16 ₁ and 16 ₃ , including the second accumulating adder 16 ₂ , has selective properties, i.e. allows operations of addition of numbers in binary code, supplied sequentially to their signal inputs only within an interval not exceeding the duration (in this case) 4τ in each cycle interval of duration T _c (Fig. 2, c), since they are clocked delayed for a time of 2τ in the second element 18 there _{are 2} delays by cyclic pulses (Fig. 2, t) from the output of the driver 7.

This is explained by the fact that each accumulating adder (16 _{1,16 2,16 3} ) consists of an addition device (combination adder, or arithmetic device - AU), the output bits of which are connected to the corresponding bit inputs of the storage register, the bit outputs of which are connected to the corresponding bit inputs of the digital input of the addition device [11]. The summed number, for example, “1” (one) in binary code, is fed to another digital input (signal input) of the addition device. The result of an addition that is one greater than the previous number stored in the corresponding storage register appears at the output of the corresponding addition device. This result is rewritten into the storage register instead of the previous number in each accumulating adder, only when the leading edge of a cyclic pulse, delayed in the second delay element 18 ₂ for a time of 2τ (Fig. 2, t) and coinciding with an interval of 4τ, arrives at the synchronization input of each accumulating adder . Other levels acting at the input of the least significant bit of the signal input of each accumulating adder before or after the specified time interval 4τ (Fig. 2, c) do not affect the summation results.

It should be noted that when using AC as an addition device, accumulating adders provide both addition and subtraction of numbers in binary code supplied to the signal input, i.e. algebraic addition of positive and negative numbers [11].

Thus, using the third accumulating adder 16 ₃ , the distorted allowed code combinations R are counted, and the total number Q of cyclic pulses (CI) or code combinations is calculated using the cycle counter 8. The capacity of the cycle counter 8 is selected equal to the value of Q, therefore, after counting each Q DI, a single pulse is formed at its output, arriving at the control input of the second memory block 12 ₂ and to the reset input of the third accumulating adder 16 ₃ through the first delay element 18 ₁ for a time of 2τ. As a result, a new result of counting R distorted allowed code combinations from the output of the third accumulating adder 16 ₃ is written to the second memory block 12 ₂ , after which this accumulating adder is reset and the process of counting the number R of distorted allowed code combinations and Q cyclic pulses is repeated.

The first threshold selection block 10 ₁ , depending on the binary number R recorded in the second memory block 12 ₂ , selects a certain binary threshold number M _r , which from its output in a parallel code is fed to the control input of the decision node 6.

Thus, during the counting time of each Q cycles, a certain threshold number Mr is supplied to the decision node 6, which can take one of discrete values (gradations) depending on the quality of reception of code combinations. Required number of gradations threshold number Mr is selected based on maintaining the probability of a false operation of the device (false detection of synchronism) within the required limits for various changes in the value In this case, the law of formation of specific values of threshold numbers Mr by the first block 10 ₁ of threshold selection can be symbolically written in the form

de F is a pre-selected rule for the first block of threshold selection 10 ₁ , according to which the value P _ORK ≈ R/Q, taking a value within the r-th measurement interval, is assigned to a very specific value of the threshold number M _r ;

A _r and B _r are, respectively, the lower and upper limits of the value for P _ORK of the r-th interval.

Accordingly, the required noise immunity of the device, which is determined by the probability of a false alarm, is ensured by the choice of the law for the formation of threshold numbers Mr for the first block of threshold selection 10 ₁ according to the corresponding measured values of the P _ORK value falling within the limits of any r-th interval with boundaries A _r and B _r , according to the principle: the larger the value of P _ORK , the larger the threshold number M _r should be.

The value of Q, which determines the counting coefficient of the 8-cycle counter, must be selected, on the one hand, large enough to ensure the required accuracy of estimating the error probability P _ORK of the allowed code combination, on the other hand, small enough to ensure the measurement of the value P _ORK in limits between two code combination synchronization failures and monitoring changes in communication conditions. If we assume that code combination synchronization failures occur relatively rarely, i.e. through time intervals much longer than the counting time Q of cyclic pulses (which occurs in practice), then the value of Q can be chosen in the following form [9]:

where B ₁ is the upper limit of the value within the first measurement interval, which corresponds to the smallest threshold number M _r ;

] [ - means rounding to a whole number.

As stated above, the search for the cyclic phase or time position of the synchronization of the input signal and the adjustment of the cyclic phase of the output signal of the device by the output synchronization signal of the decision node 6 is carried out when the log begins to arrive from the output of the first trigger 15 ₁ . 1 to the first additional control input of the decision node 6. Accordingly, the blocking of the output synchronization signal of the decision node 6 is carried out in a different state of the first trigger 15 ₁ , when a log is received from its output. 0, signaling the establishment of code combination synchronization.

Let us consider in more detail the installation of the logical level at the output of the first trigger 15 ₁ in each of the two states that determine the operating mode of the device:

1) log. 0 - the fact of restoring the synchronism of code combinations has been established after adjusting the phase of the sequence of output pulses of the cyclic pulse shaper 7 by the synchronization signal of the decision node 6, after which the output of the decision node 6 is blocked;

2) log. 1 - the fact of failure of synchronization of code combinations has been established, as a result, the output of the decision node 6 is unblocked and a search for a new temporary position of synchronization is performed.

The process of setting the first trigger 15 ₁ to the first state (log. 0) occurs as follows.

After completing the process of searching for a new cyclic phase of the signal or the temporary position of the boundaries of the code combinations and adjusting the phase of the output cyclic pulses (Fig. 2, p), as noted above, a synchronous time relationship is established between the sequence of responses at the output of the sync signal identifier 1 to the allowed code combinations (Fig. .2, o) and regularly with the following cyclic pulses. In this case, each response of the synchronization signal identifier 1 to an authorized code combination must coincide in time with the corresponding output pulse of the cyclic pulse shaper 7 (Fig. 2, p) in each cycle over an interval of 4τ.

In this case, it is necessary to determine the reliability of synchronism restoration and block the output of the decisive node in order to exclude its false operation. To do this, a sequence of single symbols 1 and 0 from the output of the first element “AND” 3 ₁ is supplied to the input of the low-order digit of the first input of the second subtraction block 13 ₂ , and another sequence of single characters 0 and 1 from the output of the first is supplied to the input of the low-order digit of the second input of the subtraction block prohibition element 2 ₁ , 0 symbols are supplied to the remaining bit inputs of the first and second inputs of the second subtraction block 13 ₂ by connecting them to a “zero” level source. In this case, at each of the inputs of the second subtraction block 13 ₂ , the incoming symbols 1 or 0, together with the remaining 0 symbols at other bit inputs, form, as at the signal inputs of the first and third accumulating adders, a binary number “1” or a binary number “0” in parallel code with a duration of 4τ. The binary number “1” or “0” with a duration of 4τ at the first input of the second subtraction block 13 ₂ is minuendable, and the binary number “0” or “1” with a duration of 4τ at the second input of the subtraction block is subtrahendable, while the output of the second subtraction block is 13 _2, either the first subtraction result will appear: "1" - "0" = "1" - plus one in parallel binary code, if the corresponding allowed codeword is not corrupted, or the second subtraction result: "0" - "1" = - "1" - minus one in parallel binary code if the corresponding allowed code combination is distorted. Accordingly, from the moment the pulse synchronization signal appears at the output of the decision node 6, the probability of the appearance at the output of the first element “AND” 3 ₁ of a single symbol 1 or the binary number “1” at the signal input of the second accumulating adder 16 ₂ corresponding to an undistorted or correctly accepted permitted code combination the probability of the appearance at the output of the first prohibition element 2 ₁ of a single symbol 1 or a binary number minus “1” at the signal input of this adder 16 ₂ corresponding to a distorted or erroneously accepted allowed code combination becomes greater when the probability of error of a binary symbol of a sequence of code combinations P _os >0.5. In this case, using the second accumulating adder 16 ₂ , the summation of single positive numbers “1” is performed, corresponding to the number of undistorted allowed code combinations that arrive at its signal input and subtracting from them the sum of single negative numbers - minus “1”, corresponding to the number of distorted allowed code combinations combinations. Using the first accumulating adder 16 ₁ , single positive numbers “1” are summed, corresponding to the number of distorted allowed code combinations that arrive at its signal input. The counting results from the outputs of the first and second accumulating adders (16 ₁ , 16 ₂ ) are fed to the first inputs of the third and fourth comparison blocks (11 ₃ , 11 ₄ ), respectively, to the second inputs of which the threshold number W _r is supplied from the output of the second threshold selection block 10 ₂ . In this case, the second accumulating adder 16 ₂ , in comparison with the first accumulating adder 16 ₁ , will reach the result of counting the established threshold number W _r first, since , as a result, the fourth comparison block 1 ₁ will work first, the voltage drop from the output of which is supplied to the input of the second pulse shaper 17 ₂ , the output pulse signal of which is supplied through the second input of the second element “OR” 9 ₂ to the reset inputs of the first and second accumulating adders (16 ₁ , 16 ₂ ), resetting them to zero, and the process of counting single binary numbers “1” is repeated. At the same time, the pulse signal of the second pulse shaper 17 ₂ is fed to the second input of the first trigger 15 ₁ , setting it to the “zero” state, from the output of which the prohibiting “zero” level is supplied to the first additional control input of the decision node 6, blocking the output synchronization signal and thereby confirming the reliability of restoring the synchronism of code combinations. Let's look at the process of detecting synchronization failure. If the synchronization of code combinations fails under any communication conditions, it can be assumed that the n-character combinations of the binary sequence are placed in the n-bit shift register (Fig. 1) at the moment each DI arrives from the output of the DI driver 7 with equal probability. Then the probability of placing a false allowed code combination in an n-bit shift register at the moment of digital arrival is equal to The probability of placing any other (forbidden) combination in this shift register is It's obvious that those. The first accumulating adder 16 _1, in comparison with the second accumulating adder 16 ₂ , will be the first to achieve the counting result of the set threshold number W _r . In this case, the more information symbols k are contained in one allowed code combination, i.e. the less code redundancy, defined as the longer the time (in cycle intervals, each with a duration of T _c ) it is possible to determine with a given degree of reliability the failure of synchronization of code combinations, using the proposed algorithm for the comparative accumulation of responses of the synchronization signal identifier 1 to false allowed and prohibited code combinations up to the selected threshold number W _r . For example, when using a minimum redundancy code (n,n-1) with k=n-1 (code with even or odd parity check), the probability And those. . It is almost impossible to determine synchronization failure in this case without using the proposed algorithm for the comparative accumulation of responses of the synchronization signal identifier 1 at the outputs of the first prohibition element 2 ₁ and the first “AND” element 3 ₁ , converted into single binary numbers for counting by the first and second accumulating adders (16 ₁ , 16 ₂ ). In this case, taking into account the equal probabilities of the appearance of pulses at the outputs of the first prohibition element 2 ₁ and the first element “AND” 3 ₁ , on average, the result of the algebraic addition of positive and negative single binary numbers “1” and minus “1” by the second accumulating adder 16 ₂ will be near zero for the selected time interval. In this case, the mathematical expectation of the number of CIs that need to be spent so that the result of accumulating responses to prohibited code combinations in the form of single binary numbers “1”, calculated by the first accumulating adder 16 ₁ , reaches the threshold number W _r will be equal to When increasing code redundancy by reducing the number of information symbols (k<n-1) in the allowed code combination, the probability increases in case of synchronization failures. Accordingly, the above value will decrease those. first accumulating adder 16 ₁ for each specific value will be the first to reach the counting result of the set threshold number W _r for any code redundancy. As a result, the third comparison block 11 ₃ will operate first, the voltage drop from the output of which is supplied to the input of the first pulse shaper, the output pulse signal of which is supplied through the first input of the second element “OR” 9 ₂ to the reset inputs of the first and second accumulating adders 16 ₁ , 16 ₂ , resetting them to zero, and the process of counting single binary numbers “1” is repeated. At the same time, the pulse signal of the first pulse shaper 11 ₇ is fed to the first input of the first trigger 15 ₁ , setting it to the “single” state, confirming the reliability of the code combination synchronization failure. From the output of the first trigger 15 ₁ , the resolving “single” level (log.1) is supplied to the first additional control input of the decision node 6, unblocking the pulse synchronization signal at the output of the decision node 6. In addition, the pulse signal of the first pulse shaper 17 ₁ is supplied through the second input of the first “OR” element 9 ₁ to the reset inputs, shift register block 5 and the first memory block 12 ₁ decider node 6, zeroing them out. After this, the search for a new temporary position of the synchronism position begins.

The law for the formation of specific values of threshold numbers W _r by the second threshold selection block 10 ₂ , as for the first threshold selection block 101, can be symbolically written in the form

where F1 is a pre-selected rule for the second block for selecting the threshold 10 ₂ , according to which the value taking values within the r-th measurement interval, a well-defined value of the threshold number W _r is brought into compliance;

- respectively, the lower and upper limits of the P _ORK value for the r-th interval.

Accordingly, the required performance of the device when establishing the fact of synchronization failure and reliably establishing the fact of synchronism restoration is ensured by the choice of the law for the formation of threshold numbers W _r for the second block of threshold selection 10 ₂ according to the corresponding measured values falling within any r-th interval with boundaries according to the principle: the larger the value the larger the threshold number W _r should be.

To determine the effectiveness of the proposed method for synchronizing code combinations in relation to the known method for synchronizing code combinations - the prototype, it is necessary to compare two devices for synchronizing code combinations, the electrical structural diagrams of which are shown in Fig. 1 and in [10], respectively, which implement the corresponding compared methods . The comparison must be carried out when the compared devices operate under equal communication conditions

In [10] the results of modeling the operation of a known device that implements a known method of prototype code combinations are presented, the initial data and obtained characteristics of which are as follows:

- the number of binary symbols in one cycle containing a sync group of m=9 sync symbols (000111011) is N=1200;

- duration of one cycle or cycle interval (CI) T _c =2.5 ms;

- time to restore synchronism T _BC - 14.7 ms or the number of digits required to restore synchronism G _BC = 14.7 ms/2.5 ms = 6 digits;

- probability of false establishment of synchronism Р _ls =2.5⋅10 ^-3 ;

- probability of error of the binary symbol P _osh = 5⋅10 ^-2 .

Let us assume that the main information is transmitted by a uniform correction code (9.5), and it is necessary to ensure synchronization of code combinations when receiving information. To perform this task, using a known device [10], on the transmitting side, in the original transmitted signal, which is a binary sequence of 9-character code combinations of the code (9,5), it is necessary to introduce a cyclic 9-character (m=n) cyclic synchronization signal (a synchronization group (000111011) periodically repeated among 9-character information code combinations with a corresponding increase in the transmission rate of the binary sequence. In this case, the transmitted signal used to compare the parameters of the compared devices must correspond as closely as possible to the transmitted signal given above.

Since the cycle length of the binary sequence containing the frame sync signal must be N=1200 binary symbols, the number of 9-character combinations contained in one cycle (one 9-character sync group and (L-1) 9-character information code combinations) is the value L=N/m=1200/9=133.333 ≈ 133 QI (or 9-character combinations). In this case, each cycle or DI must consist of a 9-character synchronization group (111000011) and 132 9-character permitted information code combinations. In this case, the cycle length of the transmitted signal is N'=m⋅133=9⋅133=1197 (binary symbols), which is approximately equal to N=1200 (binary symbols). With the error probability of a binary symbol P _osh = 5⋅10 ^-2, this structure of the test signal corresponds with a sufficient degree of accuracy to the binary signal used in simulating the operation of the prototype [10].

Let us compare the results of modeling the operation of the prototype obtained in [10], for example, in terms of synchronism recovery time T _sun =14.5 ms = 6 CI with the results that can be obtained theoretically. In [6], based on the maximum a posteriori probability criterion, an analytical expression was obtained that describes the optimal algorithm for searching for the temporal position of the synchronism position (cycle phase) of a single-symbol cyclic synchronization signal (CS) as part of a stream of information binary symbols with parallel analysis of all cycle positions. In this case, the search time for the synchronism position G _PS (in DI) or the duration of the analysis interval, at the end of which the desired cycle position should be selected with the probability of the correct choice determined by the value of K, can be determined from the relation [6]:

where the symbol] [means round to the nearest whole number;

K is the ratio of the posterior probabilities of the truth of alternative hypotheses H ₁ and H ₂ , where hypothesis H ₁ means that the analyzed i-th position of the cycle corresponds to the CS phase;

N is the number of positions (binary characters) in the cycle;

P _p - probability of correct reception of a single synchronization symbol (P _p >0.5);

R _l - the probability of the appearance of an information symbol similar to a sync symbol (false sync symbol) at any of the N-1 information positions of the DI, in most cases it can be assumed that R _l ≈ 0.5; a=(1-Р _l )/(1-Р _p ).

It should be noted that all clock signal identifiers have the same functional elements for all, such as an input m-bit shift register, m equivalence elements, a storage register, an “AND” element, for example, as shown in Fig.2. Accordingly, the output signals of various sync signal identifiers, including the proposed device and the known device, are binary sequences of responses (symbols) with a single-character cyclic sync signal (a “single” sync symbol periodically repeated among other symbols (responses). In this sequence, each sync symbol located at the synchronization time position represents the response of the sync signal identifier to a sync group (allowed code combination) of m=n sync symbols (information symbols) with the corresponding probability of correct reception of the sync group (allowed code combination). Any other symbol in the response sequence, the temporal position of which in the cycle does not correspond to the synchronization position, represents a response of the sync signal recognizer to a false synchronization group of m=n symbols with a corresponding probability of detecting a false synchronization group.

Therefore, expression (1) is also valid for determining the search time G _PS (in DI) for the synchronization position in the binary sequence at the output of the corresponding synchronization signal identifier for both the known and the proposed device. For the output signals of the sync signal identifiers of these devices, the probability of a response to a sync group or an allowed code combination should be determined as the probability of correct reception of a sync group of m sync symbols R _PSG , taking into account the correction of distorted sync symbols, or the probability of correct reception of an allowed m-symbol code combination R _prk . Accordingly, in expression (1) it is necessary to replace the probability of correct reception of a single synchronization symbol P _p with P _psg or P _prk to calculate the value of G _ps for the prototype and for the proposed device, respectively. To determine G _ps of the proposed device, the probability of correct reception of the allowed m-symbol code combination is equal to

This does not take into account a slight increase in the probability P _{of the PRK} due to the possible appearance in the shift register 22 in a synchronous state of any distorted allowed code combination that completely coincides with one of the allowed combinations recorded in the memory block 23 (Fig. 1), i.e. the transformation of one allowed code combination under the influence of interference into another allowed code combination is not taken into account. This simplification obviously slightly worsens the design characteristics of the proposed device when comparing it with the prototype.

However, the prototype provides for correction of erroneously received sync symbols in each sync group of 9 sync symbols. In [10], the number of corrected erroneous synchronization symbols in the synchrogroup 000111011 is not indicated with the error probability of a binary symbol P _OSH = 5⋅10 ^-2 , therefore we will accept the maximum possible number of 2 (symbols) for a 9-symbol synchrogroup, i.e. it is possible to correct from 1 to 2 sync symbols in a sync group and in a false sync group. A response to a sync group may appear at the output of the sync signal identifier, for example, in the 1st clock interval of each cycle with a certain probability for a 9-symbol combination, taking into account possible correction from 1 to 2 sync symbols, in the following cases:

1. When the 9 sync symbols of the sync group located in the sync identifier (9-bit shift register) coincide with the corresponding 9 sync symbols of the compared sync group (000111011) of the sync identifier (9-bit storage register), there are no errors and correction of erroneous symbols is not performed. The probability of such an event

2. When out of 9 sync symbols of a sync group located in the sync signal recognizer coincide with the corresponding 8 sync symbols of the compared sync group, and one erroneous symbol is subject to correction. The probability of such an event

3. When out of 9 sync symbols of a sync group located in the sync signal recognizer coincide with the corresponding 7 sync symbols of the compared sync group, and two erroneous symbols are subject to correction. The probability of such an event

The probability of correct detection of a sync group, taking into account the possible correction of 1 to 2 erroneously received sync symbols in one sync group, will be equal to

With each shift of the input signal in the shift register of the clock signal ID relative to the synchronous state, in the bits of the shift register of both the prototype and the proposed device, a random set of symbols 1 and 0 will be placed with a high probability. The maximum possible number of 9-character combinations, each of which can be placed in a 9-bit shift register is The probability of a false response to a false synchronization group appearing at the output of the prototype synchronization signal identifier is . However, taking into account the correction of up to 2 characters in a 9-character combination, a false response may appear in any clock interval to one of the random 9-character combinations located in the j-th TI in the 9-bit shift register of the sync signal ID in the following cases :

1. When the 9-bit shift register in the j-th TI contains a 9-character combination, 9 symbols of which coincide with the corresponding 9 synchro-symbols of the synchro-group (000111011) from the outputs of the storage register, correction of “erroneous” symbols is not performed. The probability of such an event

2. When in the 9-bit shift register in the j-th TI there is a 9-character combination, 8 symbols of which coincide with 8 of the 9 synchronizing symbols of the synchrogroup from the outputs of the storage register, and one “erroneous” symbol is subject to false correction. The probability of such an event

3. When in the 9-bit shift register in the j-th TI there is a 9-symbol combination, 7 symbols of which coincide with 7 of the 9 synchro symbols of the storage register synchro group, and two “erroneous” symbols are subject to false correction. The probability of such an event storage register

The probability of false detection of a false sync group, taking into account the possible correction of 1 to 2 false erroneous sync symbols in one false sync group, will be equal to

Since the proposed device uses a correction code (9.5), to detect a false code combination located in each clock interval in the shift register 22 of the sync signal identifier 1, a sequential comparison is made with it in each clock interval allowed code combinations from the outputs of memory block 23 (Fig. 1). In this case, the probability of a false response to a false allowed code combination appearing at the output of synchronization signal identifier 1 of the proposed device will be equal to

To calculate the number of G _ps CI during the operation of a known device in expression (1) in the base of the logarithm a = (1 - R _l )/(1 - R _p ), the probabilities R _l and R _p should be replaced by accordingly, i.e.

In this case, expression (1) should be written in the following form

Where

For synchronization devices that implement the optimal DS search algorithm [6], which includes the devices being compared, the minimum value of the search time (in DI) of the value G _pc from (6) in accordance with work [8] must be selected as follows In accordance with the calculation results, the value of G _pc at K=1 is determined in (7), therefore

At the calculated value the ratio of the posterior probabilities of the truth of the alternative hypotheses H ₁ and H ₂ , where the hypothesis Hi means that the analyzed i-th position of the cycle corresponds to the CS phase, is equal to K = 1, and make a decision on the time position of synchronism at a given value of the error probability of the binary symbol P _osh = 0.05 is impossible, since the probability of correctly detecting the time position of synchronism _PPO = 0.5. Therefore, at a minimum, it is necessary to add another cycle interval (CI) to continue analyzing the cycle positions in order to determine the synchronism position. Since an increase in the duration of the search procedure for the CS by one CI leads to an increase in the ratio K of alternative hypotheses H ₁ and H ₂ , which becomes greater than one. After rounding to the nearest integer in accordance with (6), the value of K can take in each specific case one of the values K=2(3,4,...). However, when the duration of the search procedure for the CS increases by one CI, it is necessary to know how much the value of K has increased. This calculation is presented in (8), according to which, with a search duration of 4 CI, the ratio of posterior probabilities is achieved up to K = 10, which is quite acceptable.

Thus, in accordance with (6), (7), (8) and taking into account [8], we finally select the value

This calculated result of the quantity comparable with the result of the value , obtained by simulating the operation of a well-known device [10] with an appropriate choice of the threshold number Mr for the decisive node without taking into account the time (in CI) required to detect synchronism failure across cycles.

Let us determine the period of time or the amount of digital data that must be spent to detect a failure in the synchronization of code combinations. If synchronization fails, pulses may appear at the output of the prohibition element corresponding to the missing responses of the synchronization signal recognizer to 9-character combinations at cycle positions that do not correspond to the synchronization position, i.e. at the moments of receipt of pulses from the output of the DI driver. In accordance with [10], a synchronism failure is detected when α pulses follow in a row from the output of the prohibition element. The probability of false detection of a synchrogroup, taking into account the possible correction of 1 to 2 false erroneous synchrosymbols in one false synchrogroup in accordance with (4), is equal to P _lsg = 0.08788. Accordingly, the probability of the appearance of one pulse at the output of the prohibition element or the probability of detecting a failure in the response of the sync signal identifier to a false sync group will be equal to

From (4) it follows that correcting “distorted” symbols of false synchrogroups increases the probability of responses to false synchrogroups appearing at cycle positions other than the synchronism position. In this case, in accordance with (10), the probability of a pulse appearing at the output of the prohibition element decreases, and, accordingly, the correct decision is made in less time (in the DI) about synchronization failure. For example, without character correction the value in (4) takes the value wherein

To detect a failure of synchronization of one pulse from the output of the prohibition element with the probability determined by (10) is clearly not enough; a minimum of 2 pulses is required. In [10], the authors propose to detect synchronism failure by counting α times the following pulses from the output of the prohibition element with a counter upon exiting synchronism. In this case, we accept the threshold counting coefficient for the counter upon exiting synchronism α = 2. In this case, the probability of detecting a synchronization failure will be equal to [12] and the time (in DI) for detecting a synchronism failure at equals

Synchronization recovery time (in DI) is added up from the time of detection of synchronism failure in accordance with (11) and the search time for the synchronism position in accordance with (9):

The obtained calculated data for determining the time (in DI) restoration of synchronism by cycles completely coincides with the results of modeling the operation of a known device [10].

However, the magnitude may turn out to be insufficient, and in the event of one of the synchronization failures, the next α = 2 pulses in a row may not be counted by the counter upon exiting synchronization. In this case, a pulse from the output of the synchronization signal identifier resets this counter to zero [10], and the process of detecting a synchronization failure is repeated. The probability of such an event or the probability that in case of one of the synchronization failures the synchronization failure may not be detected when counting successive pulses from the output of the prohibition element will be equal to

The mathematical expectation of the number of synchronization failures, one of which will require repeating the synchronization failure detection procedure, will be equal to [12]

In this case, more time may be spent on the process of detecting a synchronism failure, and accordingly on the process of restoring synchronism from (12):

Let's consider another characteristic of the prototype - This parameter for a known device cannot be determined theoretically; it can only be determined by testing the device or by simulating its operation. A false timing detection may occur when one of the timing failures occurs in the initial time interval after the timing failure is detected. During this time interval, the residual information corresponding to the previous cyclic phase during its search is stored in the shift register block and the decision node memory block. New information corresponding to the new cyclic phase is superimposed on the previous information, which violates the optimal search algorithm [6], and during this time interval a false detection of synchronism is most likely.

Similarly to the known device, we will determine for the proposed device the search time for the synchronism position or the duration of the analysis interval G' _PS (in DI) to select the desired synchronism position. In this case, expression (1) should be written in the following form

where in accordance with (2) and (5)

In order to minimize search time (in DI), the value from (16) in accordance with work [8] should be chosen as follows According to the calculation results, the value is defined in (7), therefore With an increase in the duration of the search procedure for the CS by one DI, the value of K increased in accordance with (18) to K=2. Accordingly, the minimum value of the quantity in accordance with (16), (17), (18) and taking into account [8] is

However, when the ratio of posterior probabilities K=2 in accordance with (18) is not enough to ensure noise immunity of the proposed device, commensurate with the noise immunity of the prototype at K=10. Therefore, for the proposed device, when comparing it with a known device, you should choose at which the value K ≈ 10 in accordance with (19).

The final choice of timing for searching the synchronism position at and K ≈ 10, which is ensured by choosing the appropriate threshold number Mr for the decision node and, in accordance with (19), should ensure equal operating conditions for the compared devices

Let us determine the length of time or the amount of digital data that must be spent to detect a failure in the synchronization of code combinations for the proposed device. If synchronization fails, pulses may appear at the output of the first prohibition element 2 ₁ , corresponding to the missing responses of the synchronization signal identifier to 9-character combinations at cycle positions that do not correspond to the synchronization position, i.e. at the moments of receipt of pulses from the output of the digital generator 7. The probability of a false response to a false code combination appearing at the output of the synchronization signal identifier 1 of the proposed device in accordance with (5) is equal to Accordingly, the probability of one pulse appearing at the output of prohibition element 2 ₁ or detecting a failure in the response of synchronization signal identifier 1 to a false allowed combination will be equal to

Detection of synchronism failure in the proposed device is determined by the first accumulating adder 16 ₁ , summing the pulses from the output of the first prohibition element 2 ₁ to the value of the threshold number W _r from the output of the second threshold selection block 17 ₂ . We select the threshold number W _r =4 at P _osh =0.05. The probability of detecting a synchronization failure will be equal to

However, the magnitude In contrast, the similar value of _RSB from (11) is not insufficient, since the proposed device does not reset the unachieved results of the summation of pulses in the accumulating adder 16 ₁ from the output of the first prohibition element 2 ₁ if a given number of successive pulses is not detected. In this case, with probability in the subsequent 5th DI, the last 4th pulse will appear, and the required summation result will be achieved - W _r = 4 pulses.

Thus, to detect a failure in the synchronization of code combinations, it is enough to record W _r = 4 consecutive pulses at the output of the first prohibition element with the probability those. time (in DI) detection of synchronism failure

The time to restore synchronism (in DI) of the proposed device is similar to (12) and taking into account the time of detection of synchronism failure R _SB (19) and the time to search for the synchronism position G _PS (21) will be equal to:

Unlike the known device, which may have false detections of synchronism with a probability In the proposed device, false detections are practically eliminated for the following reasons.

Firstly, in the proposed device, when a synchronization failure is detected by a pulse from the output of the first pulse shaper 17 _1, the block of shift registers 5 and the first memory block 12 ₁ are reset, and only after this the search for a new synchronism position begins. Thus, the situation is eliminated at the beginning of the search at each synchronization failure, when new information is superimposed on the previous information accumulated in the shift register block 5 and the first memory block 12 ₁ at the previous synchronization position when searching for a new synchronization position. This situation leads to a violation of the optimal algorithm for searching for the synchronism position [6], and, accordingly, to a false detection of synchronism, for which such a situation is favorable.

Secondly, false detections of synchronism are practically eliminated by the selection of threshold numbers Mr by the first threshold selection block 10 ₁ for the decision node 6 and the selection of threshold numbers W _r by the second threshold selection block 10 ₂ for the third and fourth comparison blocks 11 ₃ , 11 ₄ , providing failure detection synchronism and its restoration with the required probability at different values of P _osh .

Let us compare the two devices based on the calculation data obtained above using a unified calculation method [6], according to which the simulation results of a known device for determining the search time for the synchronism position G _PS given in [10] are confirmed.

The original information transmitted signal for each of the compared devices is a binary sequence of 9-character permitted code combinations (9,5).

To operate on the receiving side of the proposed code combination synchronization device, it is not necessary to enter any synchronizing synchronization information into the transmitted binary sequence. The synchronizing information is contained in the allowed code combinations themselves, the number of which is N ₀ =2 ⁵ =32 out of N _total 2 ⁹ =512 possible 9-character combinations. In this case, the duration of one cycle (CI) for the operation of the proposed device is equal to the duration of a 9-character combination, i.e. N=9 binary characters.

To operate on the receiving side of a code combination synchronization device - a known device - it is necessary to introduce a synchronizing synchronization group (000111011) into the transmitted signal every 132 9-character permitted information code combinations, similar to the transmitted signal used in modeling the operation of a known device [10]. In this case, the duration of one cycle (in CI) for the operation of a known device is equal to the duration of 133 9-character combinations, of which the first combination is a synchronization group, the remaining 132 combinations are information permitted code combinations, i.e. T _c =N=133⋅9=1197 binary symbols Therefore, for the operation of the known device, it is necessary to modify the transmitting equipment in order to introduce a cyclic synchronization signal into the original information signal with a corresponding increase in the transmission speed of the binary sequence. Increasing the transmission rate is necessary to maintain the original capacity of the communication channel without introducing a frame synchronization signal.

The time (in DI) for restoring synchronism of a known device in accordance with (12) is

code combinations or 9⋅798=7182 binary characters, and for a known IDN device=133 code combinations or 1197 binary characters.

The time (in CI) to restore synchronism by the proposed device in accordance with (25) is

binary characters, and for the proposed device IDI = 1 code combination or 9 binary characters.

The gain in time to restore synchronism of the proposed device in relation to the known device is

The proposed device, in relation to the known device, is more resistant to false alarms of the decision device or false synchronization by eliminating conditions favorable to the occurrence of false synchronization and optimizing the processes of detecting and restoring synchronism. In a known device, false acquisition of synchronism occurs with the probability and can occur in most cases with one of the synchronization failures in the initial time interval of searching for a new synchronization time position after detecting a synchronization failure. During this time interval, favorable conditions are created for false detection of synchronism with probability P _LS , as explained in detail above. In the proposed device, favorable conditions for false detection of synchronism are eliminated by resetting the block of shift registers 5 and the first memory block 12 ₁ of the decision node 6 before searching for a new time position of synchronism with a pulse signal from the output of the first pulse shaper 17 ₁ .

In conclusion, it should be noted that the implementation of the proposed invention - a method of code synchronization, when comparing it with the implementation of a known method - a prototype, allows one to achieve the following advantages when working under the same communication conditions:

1. Increasing the noise immunity of receiving code combinations by eliminating the transmission of a cyclic synchronization signal together with the basic information and correspondingly reducing the information transmission rate. Accordingly, there is no need to modify the transmitting equipment; it is enough that the transmitted binary sequence is encoded with some uniform code with error detection or correction.

2. Reducing the synchronization search time by reducing the cycle duration to the duration of the code combination and optimizing the process of detecting synchronization restoration with the required reliability, taking into account the probability of erroneous reception of the code combination of the input binary sequence.

3. Reducing the probability of false detection of code synchronism by erasing the previous accumulated synchronization information in the shift register block and in the memory block of the decision node after detecting a synchronization failure.

4. Reducing the loss of binary information during synchronization failures by optimizing the processes of failure detection and synchronization restoration of code combinations, based on the comparative accumulation of synchronization signal identifier responses corresponding to the failure and restoration of synchronization, which makes it possible to practically eliminate false detections of failure and restoration of synchronization by selecting the required threshold values numbers for the first and second threshold selection blocks depending on the probability of erroneous reception of the allowed code combination of the input binary sequence and with the probability of error of the binary symbol P _osh <0.3.

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Claims (2)

1. A method for synchronizing code combinations, according to which a binary sequence of n-character code combinations of a uniform code with error detection or correction is supplied to the information input of a synchronization signal identifier, the output signal of which is supplied to the first inputs of the prohibition element and the first “AND” element, as well as to the least significant input of the first input of the adder, the output signal of which in parallel z-bit binary code is supplied to the signal input of the shift register block, the main and additional outputs of which are connected, respectively, to the second input of the adder and the signal input of the decision node, the clock input of which is combined with the corresponding inputs of the block shift registers and a cyclic pulse shaper, the output sequence of cyclic pulses of which is supplied to the second inputs of the first prohibition element and the first “AND” element, as well as to the input of a cycle counter intended for periodic counting of Q cyclic pulses, while the block of shift registers includes z n-bit shift registers, which separately combine clock inputs and reset inputs, which are respectively the clock input and reset input of the shift register block, and the input and output bits, as well as the outputs of the input bits of all z n-bit shift registers of the shift register block are respectively, the signal input, output and additional output of the shift register block, and when each clock pulse arrives at the clock input of the shift register block, the input bits z of the n-bit shift registers of this block are rewritten from the output of the adder in a parallel z-bit binary code, the result of the summation of symbols 1 at the corresponding one of the n positions of the cycle with the corresponding serial number i = 1, 2, ..., n, in addition, the results of the summation of symbols at each of the n positions of the cycle in the form of binary numbers in parallel code from the additional output of the shift register block are fed sequentially to time with the frequency of clock pulses to the signal input of the decision node, the signal input of which is the first input of the first subtraction block, combined with the first input of the first comparison block and the data input of the first memory block, the output of which is combined with the second inputs of the first subtraction block and the first comparison block, in which two numbers are compared at its inputs, and if in the corresponding clock interval the number at the first input of the first comparison block exceeds the number at its second input, then a pulse signal is generated at the output of the first comparison block, which is sent to the control input of the first memory block, providing rewriting into it of the largest number arriving at its data input and the first inputs of the first comparison block and the first subtraction block, from the output of which binary numbers follow with the frequency of clock pulses and corresponding to the difference in numbers between the largest number from the output of the first memory block and each number, arriving at the first input of the first subtraction block, fed to the first input of the second comparison block, in which binary numbers are compared with the threshold number M, arriving at its second input, which is the control input of the decision node, from the output of the first threshold selection block, the address input of which is combined with the address input of the second threshold selection block, while the logical level from the output of the second comparison block is supplied to the reset input of the comparison counter, the clock input of which is the clock input of the decision node, and if at one of the n positions of the cycle the result of the summation of symbols 1 exceeds the summation result symbols 1 at any other position of the cycle by no less than the threshold number M in the parallel binary code, then a permissive “zero” level is supplied to the reset input of the comparison counter, and using the comparison counter, n-1 clock pulses are counted, and at its output a pulse synchronization signal, which is supplied to the first input of the second “AND” element, the second input and output of which are, respectively, the first additional control input and output of the decision node, and if a “single” logical level is supplied to the first additional control input of the decision node, then a pulse synchronization signal from the output of the decision node is supplied to the first input of the first “OR” element and to the reset input of the cyclic pulse shaper, confirming or adjusting the phase of the output sequence of cyclic pulses, characterized in that the second “OR” element, the first trigger and series-connected the first accumulating adder, the third comparison block and the first pulse shaper; in addition, a second subtraction block, a second accumulating adder, a fourth comparison block and a second pulse shaper are additionally introduced in series, as well as the first and second delay elements and a third accumulating adder, the output of which is connected to the data input of the second memory block, while in the code combination synchronization mode, a synchronous time relationship is established between the sequence of responses from the output of the synchronization signal identifier to the allowed code combinations and regularly following cyclic pulses from the output of the cyclic pulse shaper, the clock input of which is additionally connected to the additional output of the sync signal identifier , in which each response of the synchronization signal recognizer to an allowed code combination with a duration of Δτ ₁ ≤ T, where T is the duration of a cyclic pulse or clock interval, must coincide in time with the corresponding output pulse of the cyclic pulse shaper in an interval of duration Δτ ₂ ≤ Δτ ₁ , while at the output of the first element “AND”, either a single binary symbol 1 with a duration of Δτ ₂ will appear in the presence of a response from the sync signal identifier, when the corresponding allowed code combination of the input binary sequence is not distorted, or a single symbol 0 with a duration of Δτ ₂ in the absence of a response from the sync signal identifier, when the corresponding allowed the code combination is distorted, and at the output of the first prohibition element a single symbol 1 with a duration of Δτ ₂ will appear in the absence of a response from the sync signal identifier, when the corresponding allowed code combination is distorted, or a single symbol 0 with a duration of Δτ ₂ in the presence of a response from the sync signal identifier, when the corresponding allowed code combination is not is distorted, while from the output of the first prohibition element a sequence of single symbols 1 and 0 is supplied to the inputs of the low-order bits of the signal inputs of the first and third accumulating adders, symbols 0 are supplied to the remaining bit inputs of the signal inputs of these accumulating adders by connecting them to a “zero” level source, therefore, at the signal input of each of these accumulating adders, the incoming symbols 1 or 0 form the binary number one or the binary number zero in parallel binary code with the symbols "1" and "0", each with a duration of Δτ ₂ , respectively, with the help of a third accumulating adder produce the summation of sequentially arriving single binary numbers “1”, corresponding to the distorted allowed code combinations for Q cycles, counted by a cycle counter, at the end of which a pulse is generated at its output, which is fed to the control input of the second memory block, ensuring rewriting and storing the new result counting R of distorted allowed code combinations from the output of the third accumulating adder, after which the third accumulating adder is reset by applying to its reset input a pulse from the output of the cycle counter, delayed in the first delay element, and the counting of distorted code combinations by the third accumulating adder is repeated over the next Q cycles , while to ensure the summation of single binary numbers “1” arriving at the signal inputs of the accumulating adders for a duration of Δτ ₂ each, pulses delayed in the second delay element from the output of the cyclic pulse shaper, coinciding in time, are supplied to the synchronization inputs of each of the three accumulating adders with pulses from the outputs of the first “AND” and prohibition elements, the current result of counting distorted code combinations from the output of the second memory block in parallel binary code is additionally fed to the address input of the second threshold selection block, combined with the address input of the first threshold selection block, while according to the measured the value of the error probability estimate of the allowed code combination P _ORK = R/Q, the value of which is within the corresponding one of the ℓ intervals of permissible values of the value P _ORK , the corresponding threshold numbers M _r and W _r are formed for the first and second threshold selection blocks in parallel binary code with the corresponding ordinal gradation number of each threshold number r = 1, 2, …, ℓ, and the threshold number M _r from the output of the first threshold selection block is supplied to the control input of the decision node, the pulse synchronization signal of which is supplied to the input through the first input of the first “OR” element reset of the first memory block, which is the second additional control input of the decision node and the reset input of the shift register block, resetting them to zero, at the same time, a pulse synchronization signal is additionally supplied through the third input of the second “OR” element to the reset inputs of the first and second accumulating adders, resetting them to zero, after which determine the reliability of restoring the synchronization of code combinations, for this, a sequence of single symbols 1 and 0 from the output of the first element “AND” is supplied to the input of the least significant digit of the first input of the second subtraction block, and another sequence of single symbols 0 and is supplied to the input of the least significant digit of the second input of the second subtraction block 1 from the output of the first prohibition element, 0 symbols are supplied to the remaining bit inputs of the first and second inputs of the second subtraction block by connecting them to the source of the “zero” level, while at each of the inputs of the second subtraction block incoming symbols 1 or 0 together with the remaining 0 symbols on other bit inputs they form, as on the signal inputs of the first and third accumulating adders, a binary number “1” or a binary number “0” in a parallel code with a duration of Δτ ₂ , while a binary number “1” or “0” with a duration of Δτ ₂ for the first input of the second subtraction block is minuendable, and the binary number “0” or “1” with duration Δτ ₂ at the second input of the second subtraction block is subtrahendable, respectively, at the output of the second subtraction block either the first subtraction result will appear: “1” - “0” = “1” - plus one in the parallel binary code, if the corresponding allowed code combination is not distorted, or the second result of subtraction: “0” - “1” = - “1” - minus one in the parallel binary code, if the corresponding allowed code combination is distorted, and if, after detecting a synchronism failure and searching for a new synchronism position, the pulse synchronization signal from the output of the decisive node sets the phase of the output sequence of pulses of the cyclic pulse shaper to the required synchronous state corresponding to the new synchronism position, then from this moment in time the probability of the appearance of the first element "AND" of a single symbol 1, corresponding to a non-distorted or correctly received allowed code combination P _PRK becomes greater than the probability of the appearance at the output of the first element of the prohibition of a single symbol 1, corresponding to a distorted or accepted with errors allowed code combination P _ORK with the probability of an error in the binary symbol of the code sequence combinations Р _ос > 0.5, while using the second accumulating adder, single positive numbers “1” are summed, corresponding to the number of undistorted allowed code combinations that arrive at its signal input and the sum of single negative numbers is subtracted from them - minus “1” , corresponding to the number of distorted allowed code combinations, and with the help of the first accumulating adder, single binary numbers “1” are summed, corresponding to the number of distorted allowed code combinations that are received at its signal input, the counting results from the outputs of the first and second accumulating adders are fed to the first inputs the third and fourth comparison blocks, respectively, to the second inputs of which the threshold number W _r is supplied from the output of the second threshold selection block, while the second accumulating adder, in comparison with the first accumulating adder, will reach the result of counting the set threshold number W _r first, since R _PRK > R _ORK , as a result, the fourth comparison block will be the first to operate, the voltage drop from the output of which is supplied to the input of the second pulse shaper, the output pulse signal of which is supplied through the second input of the second “OR” element to the reset inputs of the first and second accumulating adders, resetting them to zero, and the process of algebraic summation single binary numbers are repeated, at the same time the pulse signal of the second pulse shaper is supplied to the second input of the first trigger, setting it to the “zero” state, prohibiting the “zero” level from the output of the first trigger, and is supplied to the first additional control input of the decision node, blocking the output synchronization signal and thereby confirming the reliability of restoring the synchronization of code combinations, if the synchronization of code combinations fails, the synchronous time relationship between the sequence of responses at the output of the synchronization signal recognizer to the allowed code combinations and regularly following cyclic pulses from the output of the cyclic pulse shaper is disrupted, in this state the probability of the appearance of the first element at the output is "And" of each single symbol 1 with a duration Δτ ₂ corresponding to a false allowed code combination is equal to P _LRK = N _o /N _total , where N _o and N _total , respectively, are the number of allowed code combinations and the total number of allowed and prohibited code combinations of the uniform code used, less or is equal to the probability of the appearance at the output of the first prohibition element of each single symbol 1 of duration Δτ ₂ , corresponding to the prohibited code combination, which is equal to R _ZK = 1 - R _LRK , and since R _ZK ≥ R _LRK , then the first accumulating adder compared to the second accumulating adder will reach the result of counting the set threshold number W _r first, as a result, the third comparison block will be the first to operate, the voltage drop from the output of which is supplied to the input of the first pulse shaper, the output pulse signal of which is supplied through the first input of the second “OR” element to the reset inputs of the first and second accumulating adders, resetting them to zero, and the process of algebraic summation of single binary numbers is repeated, at the same time the pulse signal from the output of the first pulse shaper is fed through the second input of the first “OR” element to the second additional control input of the decision node and the reset input of the shift register block to reset the first memory block of the decision node and block of shift registers, after which they begin to search for a new temporary position of the synchronization position, the pulse signal from the output of the first pulse shaper is also supplied to the first input of the first trigger, setting it to the “single” state, thereby confirming the detection of a failure in synchronization of code combinations from the output of the first trigger, the enabling “unit” level is supplied to the first additional control input of the decision node, removing the blocking from the output of the second “AND” element and from its output, a pulse synchronization signal can be sent to the output of the decision node after detecting a new time position of synchronism. 2. The method according to claim 1, characterized in that the synchronization signal identifier contains a third delay element, a control pulse former, a control counter, a decoder, a third “OR” element and a second trigger connected in series, the first output of which is supplied to the reset input of the control counter, the other the input of the second trigger is connected to the input of the fourth delay element, the output of which is connected to the first input of the third trigger, the output of which is the output of the synchronization signal recognizer, the clock input and additional output of which are, respectively, the input and output of the third delay element, the output of which is additionally connected to another input of the second trigger , in addition, the clock signal identifier contains an n-bit shift register with the serial numbers of the bits i = 1, 2, ..., n, corresponding to the order of their sequence - from the most significant output bit - at i = 1, to the least significant input bit, which is the information input synchronization signal recognizer - with i = n, a memory block of allowed code combinations (BPRCK) with similar serial numbers of outputs corresponding to the order of binary symbols with serial numbers i = 1, 2, ..., n in each code combination of the input signal, the address input of which is connected in addition to the output of the control counter, as well as n elements of equivalence with the same serial numbers i = 1, 2, ..., n, and the third element “AND”, the output of which is connected to the first input of the second prohibition element, the second input of which is connected in addition to the output control pulse generator, and the output of the second prohibition element is combined with another input of the third “OR” element and the second input of the third trigger, the first and second inputs of each element of equivalence with the corresponding serial number i are connected, respectively, to the bit output with the same serial number i of the n-bit a shift register and the output of the BPRKK with the same serial number i, and the outputs of all n elements of equivalence are connected to the corresponding n inputs of the third element “AND”, the (n+1)th input of which is connected to the second output of the second trigger.

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