RU2348117C1 - Device for cyclic synchronisation - Google Patents

Abstract

FIELD: physics, communication.

SUBSTANCE: invention is related to telecommunications and may be used in receiving devices of synchronisation by cycles of discrete messages transmission system. Device comprises identifier of sync pulse, adder, unit of shift registers, resolver, shaper of sync pulses, counter of cycles, comparator, finder of synchronism loss threshold, unit of undistorted sync pulses permissible number selection, counter of distorted sync pulses, counter of total number of sync pulses, trigger, counter of clock pulses, element AND, unit of threshold selection, signal input, clock input and device output. Identifier of sync signal comprises shift register, detector of errors in sync group, shaper of response weight for sync signal. Resolver comprises the first comparator, memory unit, subtraction unit, the second comparator, counter of comparison, the second element AND, the third element AND, element OR. At that exit from synchronism condition is determined, when number of accumulated responses at position of true sync signal in another test cycle will be less than threshold of synchronism loss. At that in case of true distortion of synchronism in cells that correspond to position of true sync signal, there is drastic reduction of sync signal identifier responses accumulation density observed, which makes it possible to faster determine condition of system exit from synchronism, which in its turn makes it possible to reduce time required for synchronism restoration.

EFFECT: improved quick-action of device for cyclic synchronisation at high probability of erroneous reception of sync pulses.

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Description

The invention relates to telecommunications and can be used in synchronization receivers on cycles of discrete message transmission systems.

A device for synchronization in cycles by AS USSR No. 1085006, class H04L 7/08, publ. 04/07/84, Bull. No. 13, containing, like the proposed device, a clock identifier, a shift register, an OR element, a first, second and third AND element, as well as a cyclic pulse shaper, a signal input, a clock input and an output. The clock input of the cyclic pulse shaper is combined with the clock input of the shift register and the clock input of the clock identifier and is the clock input of the device, and the information input of the device is connected to the signal input of the clock identifier, and the output of the pulse shaper, which is the device output, is connected to the second input of the third element And, as well as to the second input of the trigger, the output of which is connected to the second input of the first element I. In addition, the known device contains Encoder predetermined condition and an additional shift register. In this case, the output of the cyclic pulse shaper is also jointly connected to the clock input of the additional shift register. An additional output of the shift register is connected to the input of the decoder of a given state, the output of which is jointly connected to the first input of the trigger and the first input of the second element And, and the output of the third element And is connected to the signal input of the additional shift register, the outputs of which are connected to the second group of inputs of the second element I. In addition, the output of the clock identifier is also combined with the first input of the AND element, as well as with the first input of the OR element, the output of which is connected to the signal input of the shift register, basically whose output is connected to a first input of a first AND gate whose output is connected to the second input of the OR gate and the output of the second AND gate is connected to the input of reset pulse generator cyclic. A disadvantage of the known device is the low speed with a high probability of erroneous reception of synchro groups, determined by the recovery time of the cyclic synchronism, caused by the fixation of the test cycles to exit the device from synchronism. The state of synchronism recovery is determined if the number of consecutively distorted sync groups reaches a certain fixed number, which, with poor channel quality, can reach large values. A fixed task of a certain number of test cycles for the device to go out of synchronism can lead to an increase in the test time to exit the synchronism if the cyclic clock signal fails, which in turn will lead to an increase in the synchronization recovery time.

Closest to the proposed device for cyclic synchronization according to the patent of the Russian Federation No. 2284665, class. H04L 7/08, publ. 09/27/2006, Bull. No. 27, a prototype containing, like the proposed device, a clock identifier, an adder, a block of shift registers, a decisive node, a cyclic pulse shaper, a cycle counter, a third comparison unit, a counter of distorted clock pulses, a counter of the total number of clock pulses, a trigger, a clock counter, first element AND, threshold selection block, signal input, clock input and output. In this case, the clock identifier contains a shift register, an error detector in the clock group and a shaper of the response weight to the clock signal. The decision node contains a first comparison unit, a memory unit, a subtraction unit, a second comparison unit, a comparison counter, a second AND element, a third AND element, an OR element. Moreover, the signal input of the device is connected to the signal input of the identifier of the clock signal. The signal input of the clock identifier is the information input of the shift register, the output of which is connected to the input of the error detector in the clock group. The clock input of the clock identifier is connected to the clock inputs of the shift register and the shaper of the response weight to the clock signal. The first output of the error detector in the sync group is connected to the input of the shaper of the response weight to the clock signal. In this case, the second output of the error detector in the sync group is an additional output of the sync signal identifier and is connected to the data input of the counter of distorted clock pulses. The output of the driver of the response weight to the clock signal is connected to the first input of the adder, the output of which is jointly connected to the signal input of the shift register block and to the first input of the third comparison unit. The main output of the block of shift registers is connected to the second input of the adder, and the additional output is connected to the signal input of the decision node. The output of the first comparison unit is connected to the control input of the memory unit, the output of which is jointly connected to the second input of the first comparison unit and the first input of the subtraction unit. The second input of the subtraction block is combined with the data input of the memory block, the first input of the first comparison block and is the signal input of the decision node. The output of the subtraction unit is connected to the second input of the second comparison unit, the output of which is connected to the reset input of the comparison counter. The output of the comparison counter is jointly connected to the second input of the second element And, as well as to the first input of the third element I. The output of the second element And, as well as the third element And are connected respectively to the first and second inputs of the OR element, the output of which is connected to the reset input of the memory unit and is the output of the decisive node. In this case, the control input, the first and second additional control inputs and the clock input of the decisive node are, respectively, the first input of the first comparison unit, the first input of the second element And, the second input of the third element And, as well as the clock input of the comparison counter. The output of the decisive node is jointly connected to the reset inputs of the cyclic pulse shaper, the block of shift registers, the cycle counter and the third comparison unit. The control input, the first and second additional control inputs of the decision node are connected respectively to the output of the threshold selection unit, the output of the third comparison unit and the output of the device. The clock input of the cyclic pulse shaper is combined with the first input of the AND element, the clock inputs of the clock identifier, the decision node, the block of shift registers, the counter of distorted clock pulses and the clock counter. The output of the counter of distorted clock pulses is connected to the address input of the threshold selection block. The output of the cyclic pulse shaper is jointly connected to the control input of the counter of distorted clock pulses, the counting input of the cycle counter and the trigger installation input, and the trigger reset input is connected to the output of the clock pulse counter. The trigger output is connected to the reset input of the clock counter and the second input of the first AND element, the output of which is connected to the clock input of the counter of the total number of clock pulses. The output of the counter of the total number of clock pulses is connected to the reset input of the counter of distorted clock pulses and the control input of the threshold selection unit. In this case, the signal input of the clock identifier, the clock input of the cyclic pulse shaper and the output of the cyclic pulse shaper are respectively the signal input, clock input and output of the device. In addition, the known device also comprises a unit for selecting a maximum response weight, a second threshold selection unit, and an account coefficient selection unit. In this case, the output of the counter of distorted clock pulses is also jointly connected to the address inputs of the maximum response weight selection unit, the second threshold selection unit and the account coefficient selection unit, and the output of the total number of clock counter is also connected to the control inputs of the maximum response weight selection unit, the second threshold selection unit and an account ratio selection unit. The output of the maximum response weight selection unit is connected to the second input of the response weight generator for the clock signal, the third input of which is also connected to the second output of the error detector in the sync group. The output of the second threshold selection unit is connected to the second input of the third comparison unit, the output of the account coefficient selection unit is connected to the data input of the cycle counter, the output of which is connected to the control input of the third comparison unit. A disadvantage of the known device is the low speed with a high probability of erroneous reception of clock pulses, determined by the recovery time of the cyclic synchronism, caused by the fixedness of the test cycles to exit the device from synchronism. The exit state of synchronism is determined if the sum of accumulation of responses of the identifier of the clock signal at the position of the true clock signal for k test cycles is below the threshold value of accumulation of responses q. In this case, the number of test cycles k for the output of the device out of synchronism and the threshold value q of accumulation are selected depending on the probability of erroneous reception of clock pulses. However, the fixed setting of a certain number of test cycles k to exit the device out of synchronism can lead to an increase in the check time to exit synchronism if the cyclic clock signal fails (if the channel k quality is poor, it can reach large values), which in turn will lead to an increase in the synchronization recovery time .

A feature of the transmission of a deterministic cyclic clock signal is the frequency of its repetition at the same positions of the group signal transmission cycle. In this case, the clock identifier can recognize in the received group signal not only true clock groups, but also false ones randomly generated at the information positions of the cycle. Depending on the number of undistorted clock pulses, responses are generated at the output of the identifier of the clock signal in the form of weighting coefficients (for the admissible number of distorted clock symbols) and zeros (for exceeding the allowable number of distorted clock symbols). The required reliability of decision making by the decisive node is achieved by accumulating the responses of the synchronization identifier in the block of shift registers. In the synchronism mode, when the decisive node determines the position of the cyclic clock signal, the block of shift registers and the phasing of the cyclic pulse shaper are reset. If a true clock signal is detected, the initial phase of the cyclic pulse former will not change and the device for cyclic synchronization will remain in a synchronized state. If the quality of the communication channel is poor, reception of synchronization groups with distorted synchronization pulses is possible. In this case, the generated weighting coefficients at the output of the identifier decrease their values. In the block of shift registers in the cells (bits) corresponding to the position of the true clock signal, a decrease in the accumulation density of responses of the clock identifier will be observed. When receiving a synchronization group with the number of distorted synchronization symbols greater than the allowable number, a “zero” response is generated at the output of the synchronization identifier and the accumulation of synchronization information in the cells of the block of shift registers corresponding to the true synchronization groups is not carried out. In this case, with a true failure of the cyclic clock signal, a sharper decrease in the accumulation density of the responses of the sync signal identifier (in the block of shift registers in the cells corresponding to the position of the true clock signal) is observed compared to the case of receiving sync groups with distorted clock pulses. Recognition by the identifier of the clock signal of the code groups at the information positions of the cycle leads to the accumulation of responses in the cells of the block of shift registers corresponding to the false sync groups. In this case, with a regular repetition of a cycle of a false synchro group at a certain informational position and a random distortion of the true synchro-group, a cyclic pulse shaper can be installed in the false phase, i.e. cyclic synchronism may fail, although true sync groups will arrive at a given position in the loop. Improving the noise immunity of the device is achieved by determining the state of exit from cyclic synchronism. The state of synchronism recovery is determined if the sum of accumulation of responses of the identifier of the clock signal at the position of the true clock signal for k cycles is below the threshold value of accumulation of responses q. In this case, the number of test cycles k for the output of the device out of synchronism and the threshold value q of accumulation are selected depending on the probability of erroneous reception of sync symbols. Moreover, with poor channel quality, the number k can reach large values. Therefore, the fixed assignment of a certain number of test cycles k to exit the device from synchronism leads to a delay in the verification time for the device to exit synchronism (up to k cycles) if the cyclic clock signal fails, although the device can determine the loss of synchronism earlier. Since the recovery of synchronism after its failure occurs when two events occur simultaneously: the decisive node decides the new position of the cyclic clock signal and detects the loss of cyclic synchronism, an increase in the time to determine the output of the device from synchronism leads to an increase in the synchronization restoration time, which degrades the quality of discrete message transmission systems . These factors make increased demands on increasing the speed of the device for synchronization in cycles with a high probability of erroneous reception of clock pulses.

The device for cyclic synchronization contains a clock identifier, an adder, a block of shift registers, a decision node, a cyclic pulse shaper, a cycle counter, a third comparison unit, a counter of distorted clock pulses, a counter of the total number of clock pulses, a trigger, a clock counter, the first element And, a threshold selection block , signal input, clock input and output. In this case, the clock identifier contains a shift register, an error detector in the clock group and a shaper of the response weight to the clock signal. The decision node contains a first comparison unit, a memory unit, a subtraction unit, a second comparison unit, a comparison counter, a second AND element, a third AND element, an OR element. Moreover, the signal input of the device is connected to the signal input of the identifier of the clock signal. The signal input of the clock identifier is the information input of the shift register, the output of which is connected to the input of the error detector in the clock group. The clock input of the clock identifier is connected to the clock inputs of the shift register and the shaper of the response weight to the clock signal. The first output of the error detector in the sync group is connected to the input of the shaper of the response weight to the clock signal. In this case, the second output of the error detector in the sync group is an additional output of the sync signal identifier and is connected to the data input of the counter of distorted clock pulses. The output of the driver of the response weight to the clock signal is the main output of the clock identifier and is connected to the first input of the adder, the output of which is jointly connected to the signal input of the shift register block and to the first input of the third comparison unit. The main output of the block of shift registers is connected to the second input of the adder, and the additional output is connected to the signal input of the decision node. The output of the first comparison unit is connected to the control input of the memory unit, the output of which is jointly connected to the second input of the first comparison unit and the first input of the subtraction unit. The second input of the subtraction block is combined with the data input of the memory block, the first input of the first comparison block and is the signal input of the decision node. The output of the subtraction unit is connected to the second input of the second comparison unit, the output of which is connected to the reset input of the comparison counter. The output of the comparison counter is jointly connected to the second input of the second element And, as well as to the first input of the third element I. The output of the second element And, as well as the third element And are connected respectively to the first and second inputs of the OR element, the output of which is connected to the reset input of the memory unit and is the output of the decisive node. In this case, the control input, the first and second additional control inputs and the clock input of the decisive node are, respectively, the first input of the first comparison unit, the first input of the second element And, the second input of the third element And, as well as the clock input of the comparison counter. The output of the decisive node is jointly connected to the reset inputs of the cyclic pulse shaper, the block of shift registers, the cycle counter and the third comparison unit. The control input, the first and second additional control inputs of the decision node are connected respectively to the output of the threshold selection unit, the output of the third comparison unit and the output of the device. The clock input of the cyclic pulse shaper is combined with the first input of the AND element, the clock inputs of the clock identifier, the decision node, the block of shift registers, the counter of distorted clock pulses and the clock counter. The output of the counter of distorted clock pulses is connected to the address input of the threshold selection block. The output of the cyclic pulse shaper is jointly connected to the control input of the counter of distorted clock pulses, the counting input of the cycle counter and the trigger installation input, and the trigger reset input is connected to the output of the clock pulse counter. The trigger output is connected to the reset input of the clock counter and the second input of the first AND element, the output of which is connected to the clock input of the counter of the total number of clock pulses. The output of the counter of the total number of clock pulses is connected to the reset input of the counter of distorted clock pulses and the control input of the threshold selection unit. In this case, the signal input of the clock identifier, the clock input of the cyclic pulse shaper and the output of the cyclic pulse shaper are respectively the signal input, clock input and output of the device.

The technical result in the implementation of the invention is to increase the speed of the device for cyclic synchronization with a high probability of erroneous reception of clock pulses is achieved by introducing a block for selecting the allowable number of undistorted clock pulses and a determinant of the synchronism loss threshold. At the same time, the output of the counter of distorted clock pulses is also connected to the address input of the block for selecting the allowable number of undistorted clock pulses, and the output of the cyclic pulse shaper is also connected to the control input of the determinant of the loss of synchronism threshold and the control input of the third comparison unit. The output of the counter of the total number of clock pulses is also connected to the control input of the block for selecting the permissible number of undistorted clock pulses, the output of which is connected to the first input of the synchronization loss threshold determinant, the loop counter output is connected to the second input, and the output of the synchronization loss threshold determiner is connected to the second input of the third comparison unit .

Thanks to the introduction of a block for selecting the permissible number of undistorted clock pulses and a determinant of the threshold for loss of synchronism, the time for determining by the device for cyclic synchronization the state of exit from synchronism is reduced, since checking that the device exits the synchronism state is carried out not through a fixed number k of test cycles, selected depending on the quality of the channel, but after each test cycle. In this case, the exit from the state of synchronism will be determined if the number of accumulated responses to the position of the true clock signal for the next i-th test cycle is less than a certain threshold for loss of synchronism. The threshold number of loss of synchronism is formed in the determinant of the threshold of loss of synchronism, depending on the quality of the communication channel. In this case, the allowable number of undistorted clock pulses, which is selected depending on the measured probability of incorrect reception of clock pulses, is supplied to the determinant of the threshold of loss of synchronism from the block for selecting the allowable number of undistorted clock pulses. In this case, with a true failure of cyclic synchronism in the cells of the block of shift registers corresponding to the position of the true synchronization signal, there will be a sharp decrease in the accumulation density of responses of the synchronization signal identifier, which will lead to a faster determination of the output from synchronism (fewer test cycles than k will be required), which in turn, will lead to a reduction in synchronization recovery time.

The analysis of the prior art by the applicant, including a search by patent and scientific and technical sources of information, and the identification of sources containing information about analogues of the claimed invention, allowed to establish that the applicant did not find an analogue characterized by features identical to all the essential features of the claimed invention. The selection from the list of identified analogues of the prototype, as the closest in the set of essential features of the analogue, allowed us to identify the set of essential distinctive features perceived by the applicant in the claimed device set forth in the claims. Therefore, the claimed invention meets the criterion of "novelty."

To verify compliance of the claimed invention with the criterion of "inventive step", the applicant conducted an additional search for known solutions in order to identify signs that match the distinctive features of the claimed device from the prototype. The search results showed that the claimed invention does not follow for a specialist explicitly from the prior art determined by the applicant. The effect of the transformations provided for by the essential features of the claimed invention on the achievement of a technical result is not revealed. In particular, the claimed invention does not provide for the following transformations: the addition of a known product with any known part, attached to it according to known rules, to achieve a technical result in respect of which the effect of such additions is established; the replacement of any part of a known product with another known part to achieve a technical result in respect of which the effect of such a replacement is established; the exclusion of any part of the funds with the simultaneous exclusion of the function due to its presence and the achievement of the usual result for such exclusion; the increase in the same type of elements to enhance the technical result due to the presence in the tool of just such elements; the implementation of a known tool or part of a known material to achieve a technical result due to the known properties of the material; the creation of a tool consisting of known parts, the choice of which and the connection between them are based on known rules, recommendations and the technical result achieved in this case is due only to the known properties of the parts of this object and the relationships between them; a change in the quantitative features or the relationship of the features, if the fact of the influence of each of them on the technical result is known and new values of the features or their relationship could be obtained from known dependencies. Therefore, the claimed invention meets the criterion of "inventive step".

The invention is illustrated in the drawing, which shows a structural diagram of a device for cyclic synchronization. Information confirming the possibility of carrying out the invention with obtaining the above technical result are as follows.

The device for cyclic synchronization comprises a clock identifier 1, an adder 2, a shift register block 3, a decision unit 4, a cyclic pulse shaper 5, a 6-cycle counter, a comparison unit 7, a synchronization loss threshold determiner 8, a block 9 for selecting the allowable number of undistorted clock pulses, a counter 10 distorted clock pulses, counter 11 of the total number of clock pulses, trigger 12, clock counter 13, element 14 AND, threshold selection block 15, input 16 signal, input 17 clock and output 18 of the device. The identifier 1 of the clock contains a shift register 19, a detector 20 errors in the clock group, the shaper 21 of the weight of the response to the clock. The decision node 4 comprises a comparison unit 22, a memory unit 23, a subtraction unit 24, a comparison unit 25, a comparison counter 26, an AND element 27, an AND element 28, an OR element 29. In this case, the signal input 16 is connected to the signal input of the identifier 1 of the clock signal. The signal input of the identifier 1 of the clock signal is the information input of the shift register 19, the output of which is connected to the input of the detector 20 errors in the sync group. The clock input of the identifier 1 of the clock signal is connected to the clock inputs of the register 19 of the shift and the shaper 21 of the weight of the response to the clock signal. The first output of the error detector 20 in the sync group is connected to the input of the shaper 21 of the response weight to the clock signal. The second output of the error detector 20 in the sync group is an additional output of the sync signal identifier and is connected to the data input of the counter 10 distorted clock pulses. The output of the shaper of the response weight to the clock signal is the main output of the clock identifier and is connected to the first input of the adder 2, the output of which is connected together with the signal input of the shift register unit 3 and the first input of the comparison unit 7. The main output of the shift register block 3 is connected to the second input of the adder 2, and the additional output is connected to the signal input of the decision node 4. The output of the comparison unit 22 is connected to the control input of the memory unit 23, the output of which is connected to the second input of the comparison unit 22 and the first input block 24 subtraction. The second input of the subtraction unit 24 is combined with the data input of the memory unit 23, the first input of the comparison unit 22 and is the signal input of the decision unit 4. The output of the subtraction unit 24 is connected to the second input of the comparison unit 25, the output of which is connected to the reset input of the comparison counter 26. The output of the comparison counter 26 is jointly connected to the second input of the element 27 AND, as well as to the first input of the element 28 I. The output of the element 27 AND, as well as the element 28 And are connected respectively to the first and second inputs of the element 29 OR, the output of which is connected to the reset input of the block 23 memory and is the output of the decision node 4. In this case, the control input, clock input, as well as the first and second additional control inputs of the decision node 4 are, respectively, the first input of the comparison unit 25, the clock input of the comparison counter 26, the first input that 27 And, the second input of element 28 I. The output of the decision node 4 is connected to the reset inputs of block 3 of the shift register, shaper 5 cyclic pulses, counter 6 cycles and block 7 comparison. The clock input of the generator 5 cyclic pulses is combined with the first input of the element 14 And, the clock input of the identifier 1 of the clock signal, the decision node 4, block 3 of the shift registers, counter 10 distorted clock pulses and the counter 13 clock pulses. The control input, the first and second additional control inputs of the decision node 4 are connected respectively to the output of the threshold selection unit 15, the output of the comparison unit 7 and the output of the device. The output of the counter 10 distorted clock pulses is jointly connected to the address inputs of the threshold selection block 15 and the block 9 of the selection of the allowable number of undistorted clock pulses. The output of the counter 11 of the total number of clock pulses is jointly connected to the reset input of the counter 10 distorted clock pulses and the control inputs of the threshold selection unit 15 and the block 9 for selecting the allowable number of undistorted clock pulses. The output of the shaper of 5 cyclic pulses is jointly connected to the control input of the counter 10 distorted clock pulses, the control input of the trigger 12, to the control input of the determinant 8 of the synchronization loss threshold, to the counting input of the counter 6 cycles and the control input of the comparison unit 7. The reset input of the trigger 12 is connected to the output of the counter 13 clock pulses. The output of the trigger 12 is jointly connected to the reset input of the counter 13 clock pulses and the second input of the element 14, the output of which is connected to the clock input of the counter 11 of the total number of clock pulses. The output of block 9 for selecting the permissible number of undistorted clock pulses is connected to the first input of the determinant 8 of the synchronization loss threshold, the second input of which is connected to the output of the counter 6 cycles, and the output of the determinant 8 of the synchronization loss threshold is connected to the second input of the comparison unit 7. In this case, the signal input of the identifier 1, the clock input of the shaper 5 cyclic pulses and the output of the shaper 5 cyclic pulses is the signal input 16, the clock input 17 and the output 18 of the device.

A device for cyclic synchronization operates as follows. The signal input of the identifier 1 of the clock signal receives a group digital signal containing deterministic groups of the clock signal repeating with the frequency of the cycles. At the information positions of the group signal, code groups of information symbols identical to the sync group are formed randomly. During each clock interval, one symbol of the received signal is recorded in the shift register 19, and with the arrival of the next symbol, the previous one moves to the next cell of the shift register. Thus, for m clock intervals (where m is the number of characters in the sync group), an m-character code pattern is written to the register. At the same time, during each clock interval, the structure of each received sequence of m symbols is compared with the “copy” of the sync group recorded in the error detector 20 in the sync group, and the comparison result in the detector 20 is converted to s-bit (where s = [log ₂ m] 1, where [] - integer part of) binary number Synchrosymbols accurately detected in the synchronization and _{non-distorting} m binary number of errors detected in the synchronization m _err. At the same time, the number m _inisk is formed at the first output of the error detector 20 in the _{sync group} and is fed to the data input of the former 21 of the response weight to the clock signal. The number m _Osh is generated at the second output of the error detector 20 in the sync group and is fed to the additional output of the sync signal identifier 1. The detector 20 errors in the sync group can be implemented as described in the patent of the Russian Federation No. 2284665, class. H04L 7/08, publ. 09/27/2006, Bull. No. 27, figure 2.

In the driver 21 of the weight of the response to the sync signal, depending on the magnitude of the correctly detected sync _symbols in the sync _group m _inisc , the response w is generated (in the form of a binary number). Shaper 21 of the weight of the response to the clock signal can be made in the form of a register with a parallel input, and the parallel output of the register is connected to the address input of a storage device (for example, implemented using a permanent storage device on a chip K573RF13), in the memory elements of which the weight coefficients calculated depending on the magnitude of the undistorted sync _symbols m _not, according to the following rule:

запоминающего устройства) переднего фронта сигнала тактовой синхронизации.where m is the length of the sync group; m _nonisk - the number of undistorted sync _symbols ; ]•[ - the integer part of number. The selection of the weight w of the response to the clock signal from the storage device is carried out upon receipt of the weight of the response to the clock signal (which is the read control input) to the clock input of the driver 21

memory) leading edge of the clock signal.

The response w from the main output of the driver 21 of the response weight to the clock signal is supplied to the first input of adder 2. Adder 2 is a parallel combiner in which the s-bit input of the first term (the least significant bits of the n-bit input) and the n-bit inputs of the second term are respectively, the first and second input of the adder, while the other (ns) bit inputs of the first term are connected to the source of the "zero" level.

Block 3 of shift registers includes n N-bit (n = [log ₂ N · m] +1, N is the number of positions in one cycle) shift registers. In this case, the combined clock inputs and the combined reset inputs of the shift registers are respectively the clock input and the reset input of the block 3 of shift registers, and the signal inputs, outputs of the last bits and the outputs of the first bits of all shift registers are respectively the signal input, the main output and the additional output of the side of 3 registers shear. Thus, the response of the identifier 1 of the clock signal, which occurs in the i-th clock interval, is added to the adder 2 with the result of the previous count of responses at the i-th position of the cycle coming from the main output of the block 3 shift registers. A new response count result greater than w of the previous one is written as an n-bit binary number in the corresponding first cells (bits) of the shift registers of the block 3 of shift registers. In this case, the binary number previously recorded in the first cells of block 3 of shift registers, as well as all other numbers stored in subsequent cells of the same type, are simultaneously shifted by one bit, and from the output of block 3 of shift registers to the second input of adder 2, the result of the response count is received - on the (i + 1) -th clock interval. If there is no response of the clock identifier on the (i + 1) -th clock interval, then the previous result of counting responses at the (i + 1) -th position of the cycle is written to the first cells of block 3 of shift registers, and the remaining numbers stored in the same cells of block 3 shift registers, are shifted by one bit, etc. Block 3 shift registers provides storage of the results of counting responses at each position of the cycle for the duration of the cycle. The value of n determines the memory capacity of the counting results. At the same time, the results of the response count at each position of the cycle from the additional output of the block 3 of the shift registers are sequentially fed to the signal input of the decision node 4. In the decision node 4, for example, in the i-th clock interval, the input binary number in parallel code representing the current result of the response count at the i-th position of the cycle, simultaneously fed to the first input of the comparison unit 22, the data input of the memory unit 23 and the second input of the subtraction unit 24. In the comparison block 22, the input number is compared with the binary number stored in the memory block 23 and, if it exceeds the number of the memory block 23, a pulse is generated at the output of the comparison block 22, which, when fed to the control input of the memory block 23, erases the previous one and writes new (input) number. After that, the inputs of block 22 comparison are equal binary numbers. If the input number is equal to or less than the number stored in the memory unit 23, then the contents of the latter does not change. Thus, the largest current result of the response counting at any position of the cycle is copied to the memory block 23, which is then compared with the counting results at subsequent positions of the cycle. The resulting difference (between the number of the memory block 23 and the input number) at the output of the subtraction block 24 as a binary number in the parallel code is compared in the comparison block 25 with the threshold number d received at its first input (which is the control input of the decision node 4) from the output of the block 15 threshold choices. Moreover, if the number from the output of the subtraction unit 24 is less than the threshold number d, then from the output of the second comparison unit 25, a “single” (inhibitory) potential is applied to the reset input of the comparison counter 26, which sets and holds it in the “zero” state. When in the i-th clock interval the number from the output of the subtraction unit 24 is equal to or greater than the number d, the “zero” (resolving) potential comes from the output of the second comparison block 25, and the comparison counter 26 counts one clock pulse supplied to its clock input, which is the clock input of the decision node 4. If the largest binary number recorded in the block 23 of the memory will exceed each of the N-1 subsequent numbers coming one after another from the additional output of the block 3 shift registers, an amount equal to or greater than the threshold number d, then the comparison counter 26 will count the next consecutive N clock pulses. Then, a “single” pulse signal is generated at its output, which is fed to the second input of the 27 And element, as well as to the first input of the 28 And element. The passage of the “single” pulse signal from the output of the comparison counter 26 to the output of the 27 And element is single "pulse signal to the first input of element 27 And from the output of block 7 comparison. The passage of the "single" pulse signal from the output of the comparison counter 26 to the output of the element 28 And is carried out upon receipt of the cyclic synchronization signal from the output of the shaper 5 cyclic pulses to the second input of the element 28 I. The element 29 OR provides the passage of the "single" pulse signal to the output of the decision node 4 or from the output of element 27 AND, or from the output of element 28 I. The signal at the output of the decision node 4 is a synchronization signal (phasing) of the device. In this case, in the first case, the synchronization signal at the output of the decision node 4 is formed when the synchronism state is lost. In the second case, the synchronization output signal is generated in synchronous operation mode.

The synchronization signal from the output of the decisive node 4 is fed to the reset inputs of the memory block 23, the block 3 of the shift registers and the shaper 5 cyclic pulses, the counter 6 cycles and block 7 comparison. As a result, the block 23 of the memory and the block 3 of the shift registers, the counter 6 cycles and the trigger of the block 7 are reset to "zero". After that, the inhibitory “single” potential starts to arrive from the output of the comparison unit 25 and the comparison counter 26 is also reset to “zero”. The output synchronization signal of the decisive node 4 is the phasing of the shaper 5 cyclic pulses in such a way that the following cyclic pulses begin to arrive at the device output 18 regularly, coinciding in time with the responses of the synchronization identifier 1 to the true sync groups. Further, the process of searching for the temporary position of the cyclic clock signal in the binary stream of the group signal starts again. In this case, the next synchronization signal of the decision node 4 will be generated under the condition that the synchronization signal is detected after the loss of the synchronism state (“single” pulse at the output of the 27 And element) or in the synchronous state (“single” pulse at the output of the 28 And element). In the first case, the synchronization signal of the decision node 4 will change the phase of the initial installation of the shaper 5 cyclic pulses. In the second case, the phase of the initial installation of the shaper 5 cyclic pulses does not change. Blocks 22 and 25 of the comparison can be performed, for example, in the form of an n-bit binary code comparator, forming the sign “more”, “less” with the corresponding sign of the difference in the values of the input operands, as well as a sign of their equality, applied to the first input P and second input Q blocks. The outputs of the first and second comparison units are the output P> Q of the comparator. The memory block 23 can be made in the form of an n-bit register with a parallel input. In this case, the data input, control input, reset input, and output of the memory unit 23 is, respectively, a data input, a clock input, a reset input, and an n-bit register data output. The subtraction unit 24 may be made in the form of a full n-bit parallel adder. The adder capacity is ensured by the serial connection of the transfer output of the low-order adder to the transfer input of the high-order adder. In order for the adder to perform the subtraction operation, the number from the memory block 23 entering the first input of the subtraction block is inverted, and the number coming from the additional output of the shift register block 3 to the second input of the subtraction block is not inverted (for example, it can be implemented as described in the patent of the Russian Federation No. 2284665, class H04L 7/08, publ. 09/27/2006, Bull. No. 27, figure 2, elements DD6, DD1.3-DD1). Counter 26 comparison and generator 5 cyclic pulses can be made in the form of series-connected binary decimal synchronous counter and decoder. In this case, the reset inputs of the comparison counter 26 and the shaper 5 of the cyclic pulses are the reset inputs of the binary-decimal counter. Accordingly, the clock inputs of the counter 26 comparison and generator 5 cyclic pulses are clock inputs of the binary decimal counter. The outputs of the counter 26 comparison and shaper 5 cyclic pulses is the output of the decoder, which determines the state of the binary decimal counters. In this case, the phasing of the shaper 5 cyclic pulses can be carried out by setting the counter to zero.

The failure of the synchronism state by the device for cyclic synchronization is determined using the counter 6 cycles, block 7 comparison, determinant 8 of the threshold for loss of synchronism and block 9 select the allowable number of undistorted clock pulses. The failure of the synchronism state will be determined using the comparison unit 7, if the number of accumulated responses in the adder 2 at the position of the true clock signal for the next observation cycle L is less than the threshold number q (the loss of synchronism threshold) generated in the determinant 8 of the synchronism loss threshold. The threshold number q is formed depending on the quality of the communication channel. At the same time, the selected admissible number of undistorted clock pulses m _{additional non-distortion} is supplied to the first input of the determinism threshold 8 of the synchronism loss threshold from the output of the block 9 for selecting the allowable number of undistorted clock pulses. At the second input of the determinant 8 of the loss of synchronism threshold from the output of the counter of 6 cycles, the binary number of the current clock search cycle L is fed. From the output of the determinant 8 of the threshold for loss of synchronism, the threshold number q is supplied to the second input of the comparison unit, and the number is supplied to its first input from the output of adder 2 accumulated responses to the true clock position.

The 6-cycle counter is a binary-decimal synchronous pulse counter, the cyclical synchronization pulses are supplied to the counting input of which from the output of the 5-cycle pulse generator, and the synchronization signal is supplied to the reset input of the counter 6 from the output of the deciding node 4.

Block 7 comparison consists of a comparison device and a storage device. In the comparison device, the operation of comparing the number P arriving at the first input of the comparing unit 7 with the number Q arriving at the second input of the unit 7 is performed. The result of the comparison from the output of the comparing device is briefly stored in the storage device when a control signal is received at the control input of the comparing unit 7. When P <Q, a logical "unit" signal is written to the memory. At P≥Q, a logical “zero” signal is written to the memory device. In the first case (P <Q), in the comparison unit 7, the failure of the synchronism state of the device for cyclic synchronization is determined, and in the second (P≥Q), the failure of the synchronism state is absent. The memory device is reset to zero when the synchronization signal comparing unit 7 is output from the output of the deciding node 4. The block 7 comparing can be implemented as described in RF patent No. 2284665, class. H04L 7/08, publ. 09/27/2006, Bull. No. 27, figure 4, while the comparison device uses only one output P <Q.

запоминающего устройства подается сигнал цикловой синхронизации. В элементы памяти запоминающего устройства записаны значения порога потери синхронизма q, рассчитанные в зависимости от величины допустимого числа неискаженных синхросимволов m_{доп неиск} и числа текущего цикла поиска синхросигнала L по следующему правилу:The determinant 8 threshold synchronization loss is a storage device. At the same time, the first input of the determinant of the synchronization loss threshold 8 is supplied with the permissible number of undistorted clock pulses m _{additional non-distortion} , which is fed to the lower bits of the address input of the memory device, and the binary bits of the current cycle are fed to the _higher digits (which are the second input of the determinant of the synchronism loss threshold 8) Search L. To the read control input

the storage device is fed a cyclic synchronization signal. The values of the threshold of loss of synchronism q, calculated depending on the value of the allowable number of undistorted synchronization _symbols m _{additional not search} and the number of the current search cycle of the synchronization signal L according to the following rule, are recorded in the memory elements of the storage device:

where] • [is the integer part of the number.

запоминающего устройства сигнала цикловой синхронизации. Запоминающее устройство, например, может быть реализованного с помощью постоянного запоминающего устройства на микросхеме К573РФ13.The sampling threshold value of the loss of synchronism q from the storage device is carried out upon receipt of the read control input

storage device signal cyclic synchronization. A storage device, for example, can be implemented using read-only memory on a K573RF13 chip.

The process of generating the threshold numbers d for the decision node 4 and the permissible number of undistorted clock pulses m _{additional not} in the sync _group for the determinant 8 of the synchronism loss threshold is as follows. At the s-bit data input of the counter 10 distorted clock pulses receives a binary number m _OSH equal to the number of errors in the clock group. Counter 10 distorted clock pulses calculates the total number of errors in the clock groups, and counter 11 the total number of clock pulses transmitted for a certain period of time Y. The cycle synchronization signal from the output of the shaper 5 cyclic pulses sets the trigger 12 to a "single" state, and a "single" signal (signal permission) from the output of the trigger 12 goes to the reset inputs of the counter 13 clock pulses and the second input of the element 14 I. In this case, the counter 13 clock pulses is transferred to the "count" mode and the passage of the clock is allowed x pulses from the output of element 14 And to the clock input of the counter 11 of the total number of clock pulses. The counter 13 ensures the passage through element 14 And in one cycle a certain number of clock pulses equal to the number of pulses in the sync group m, after which it resets the trigger 12 to zero. The counter 13 clock pulses of the logical "zero" signal from the output of the trigger 12 is reset to "zero" and is transferred to the "stop" mode. By counting the number X of distorted clock pulses during the counting time of a rather large number of cyclic clock pulses Y, one can periodically determine the probability (frequency) of erroneous reception of clock pulses by the formula P _OSH = X / Y, i.e. make a current assessment of the degree of distortion of the received digital signal. The counters 11 and 13 can be performed as well as the generator 5 cyclic pulses in the form of series-connected binary decimal synchronous counter and decoder. Resetting both counters is synchronous. At the same time, the decoder of the counter of 13 clock pulses is configured to recognize the state of the binary-decimal counter equal to the number of pulses in the sync group m, and the decoder of the counter 11 of the total number of clock pulses is configured to recognize the state of the binary-decimal counter equal to the number of observation pulses Y. The trigger 12 can be executed as an RS trigger. The input S is connected to the output of the shaper 5 cyclic pulses, and the input R to the output of the counter 13 clock pulses. The capacity of the counter 11 of the total number of clock pulses is selected to be equal to Y, therefore, after counting every Y clock pulses, a single pulse is generated at its output, with which, in the threshold selection block 15 and in the block for selecting the allowable number of errors in the sync group, instead of the binary number stored in them, the contents of the counter 10 distorted clock pulses are copied. After that, the counter 10 of distorted clock pulses is reset to "zero" and the process of analyzing the quality of the received signal during the subsequent subsequent Y clock pulses is repeated.

Counter 10 distorted clock consists of an adder and a storage device. In this case, the data input of the counter 10 distorted clock pulses, which is the input of the summing device, is fed the number of erroneously received clock pulses m _Osh from the second output of the detector 20 errors in the clock groups. This number is added to the number of errors in the sync groups accumulated over the previous observation period. At the control input of the counter 10 distorted clock pulses from the output of the shaper 5 cyclic pulses received cyclic pulses. This ensures that the counter 10 only counts the distorted clock pulses X belonging to the true clock groups. Counter 10 distorted clock can be implemented, for example, as described in the description of the invention to the patent of the Russian Federation No. 2239953, class. H04L 7/08, publ. 11/26/2004, Bull. No. 31, Fig. 4.

запоминающих устройств сигнала окончания измерения вероятности ошибочного приема синхроимпульсов Р_ош с выхода счетчика 11 общего числа синхроимпульсов. Таким образом, в течение времени счета Y в решающий узел 4 подается пороговое число d, а в определитель 8 порога потери синхронизма - допустимое число неискаженных синхроимпульсов m_{доп неиск} в синхрогруппе, которые могут принимать в каждом конкретном случае одно из h дискретных значений (градаций) в зависимости от качества принимаемого сигнала. Необходимое число градаций h порогового числа d, а также допустимого числа неискаженных синхроимпульсов m_{доп неиск} в синхрогруппе выбирается из расчета поддержания вероятности обнаружения ложного синхросигнала в требуемых пределах при различных изменениях величины Р_ош. При этом законы формирования конкретных значений порогового числа d_r блоком 15 выбора порога, допустимого числа неискаженных синхроимпульсов m_{доп неиск r} блоком 9 выбора допустимого числа ошибок в синхрогруппе можно записать в виде:The threshold selection block 15 and the block 9 for selecting the allowable number of undistorted clock pulses in the sync group, depending on the value of the binary number X recorded in them, select a certain threshold number d and the allowable number of undistorted clock pulses m _{additional not select} . The selected numbers d and m _{additional not} from the outputs of blocks 15 and 9 in the parallel code are respectively supplied to the control input of the decision node 4 and the first input of the determinant 8 of the synchronism loss threshold. The threshold selection block 15 and the block 9 for selecting the permissible number of undistorted clock pulses can be made in the form of read-only memory devices, in the memory elements of which are written the results of calculating the threshold numbers d and the permissible number of undistorted clock pulses m _{additional non-clock} depending on the probability of erroneous reception of clock pulses (see Kalnikov VV, Tashlinsky AG Methods for finding the internal parameters of cyclic synchronization systems with parallel and recircular search - Ulyanovsk: UFVUS, 2002, 35 pp. - Dep. At TsVNI MO RF 23.09.02. No. B4898, publ. SRDR, ser. B, issue 61, 2002). The value of the measured probability of erroneous reception of clock pulses Р _Ош from the output of the counter 10 of distorted clock pulses is supplied to the address inputs of memory devices of blocks 15 and 9. The output of numbers d and m _{additional not} from blocks 15 and 9 is carried out upon receipt of read control inputs

memory devices signal the end of the measurement of the probability of erroneous reception of clock pulses R _OSH from the output of the counter 11 of the total number of clock pulses. Thus, during the counting time Y, the threshold number d is supplied to the deciding node 4, and the permissible number of undistorted clock pulses m _{additional unsearch} in the sync _group that can take one of h discrete values (gradations) depending on the quality of the received signal. The required number of gradations h of the threshold number d, as well as the permissible number of undistorted clock pulses m, _{additional not-} in-sync in the sync _group is selected from the calculation of maintaining the probability of detecting a false clock within the required limits for various changes in the value of _Posh . In this case, the laws of the formation of specific values of the threshold number d _{r by the} block 15 of the threshold selection, the admissible number of undistorted clock pulses m _{additional non-r} block _{r by the} block 9 of the selection of the permissible number of errors in the sync _group can be written in the form:

d _r = F ₁ (A _r ≤P _Osh <B _r ),

m _{additional non-r r} = F ₂ (A _r ≤P _Osh <B _r ),

where F ₁ , F ₂ are pre-selected rules, respectively, for block 15 for selecting a threshold and block 9 for selecting an allowable number of undistorted clock pulses, according to which the value of _Psh = X / Y, taking on a value within the rth interval (r can vary from 1 to h) of measurements, it is brought into correspondence with the well-defined value of the threshold number d _r , as well as the allowable number of undistorted clock pulses m _{Ош notisk r} ; And _r and B _r - respectively, the lower and upper boundaries of the value of R _OSH for the r-th interval.

Thanks to the introduction of a block for selecting the permissible number of undistorted clock pulses and a determinant of the threshold for loss of synchronism, the time for determining by the device for cyclic synchronization the state of exit from synchronism is reduced since checking that the device exits the synchronism state is carried out not through a fixed number k of test cycles, selected depending on the quality of the channel, but after each test cycle. In this case, the exit from the state of synchronism will be determined if the number of accumulated responses to the position of the true clock signal for the next i-th test cycle is not less than a certain threshold for loss of synchronism. In this case, with a true failure of cyclic synchronism in the block of shift registers in the cells corresponding to the position of the true clock signal, there will be a sharp decrease in the accumulation density of responses of the clock identifier, which will lead to a faster determination of the synchronism output (fewer test cycles than k will be required), which in turn, will lead to a reduction in synchronization recovery time. The threshold number of loss of synchronism is formed in the determinant of the threshold of loss of synchronism, depending on the quality of the communication channel. In this case, the allowable number of undistorted clock pulses, which is selected depending on the measured probability of incorrect reception of clock pulses, is supplied to the determinant of the threshold of loss of synchronism from the block for selecting the allowable number of undistorted clock pulses.

The required speed of the device for synchronization in cycles (with a high probability of erroneous reception of clock pulses), which is determined by the recovery time of cyclic synchronism, is achieved by restoring synchronism after its failure and phasing the device to a new position of the cyclic synchronization signal when two events occur simultaneously: determination by the decision node 4 new positions of the cyclic clock signal and detection of a failure (loss) of cyclic synchronism using the determinant 8 threshold sweat The synchronism series and block 9 select the permissible number of undistorted clock pulses, as well as a counter of 6 cycles and block 7 of comparison. In this case, the check to exit the synchronism state in the comparison unit 7 is carried out after each test cycle and is determined if the number of accumulated responses to the true clock signal position for the next i-th test cycle is less than the synchronism loss threshold set using determinant 8 of the synchronism loss threshold. Thus, with a high probability of erroneous reception of clock pulses, the minimum synchronization recovery time is achieved, at which the required noise immunity is still provided. In this case, the required noise immunity of the device is ensured by the choice of the law of formation of the weight coefficient w for the shaper 21 of the response weight to the clock signal, threshold numbers d _r and q _r , for the threshold selection block 15 and threshold determiner 8, as well as the permissible number of undistorted clock pulses m _{error not r} for the block 9, the selection of the allowable number of undistorted clock pulses according to the corresponding measured values of the value of R _OS falling within any r-th interval with the boundaries of A _r and B _r , according to the principle: the larger the value of R _OS , the more the highest should be the threshold number d _r and the permissible number of undistorted clock pulses m _{osh non-r} . The values of the weight coefficient w and the threshold number q _{r are} determined according to the rules defined by formulas (1) and (2). The value of Y, which determines the counting coefficient of the counter 9 of the total number of clock pulses, should be selected, on the one hand, large enough to provide the required accuracy for estimating the probability of error P _{Оsh of a} single symbol, on the other hand, small enough to provide a measure of the value of Р _Ош in the limits between two failures of synchronism in cycles and tracking changes in communication conditions. If we assume that synchronism failures in cycles occur relatively rarely, i.e. at time intervals far exceeding the counting time Y of cyclic clock pulses, in practice, the value of Y can be chosen as:

where B ₁ - the upper limit of the value of R _OS within the first measurement interval, which corresponds to the smallest threshold number d ₁ ; [] - means rounding to the integer.

The above information indicates the following conditions are met when using the claimed device:

- a tool embodying the claimed device in its implementation, is intended for use in receiving devices synchronization cycles of systems for transmitting discrete messages;

- for the claimed device in the form described in the claims, the possibility of its implementation using the means and methods described in the application or known prior to the priority date is confirmed;

- a tool embodying the claimed invention in its implementation, is able to ensure the achievement of the perceived by the applicant technical result.

Thus, the claimed invention meets the criterion of "industrial applicability".

Claims (1)

A device for cyclic synchronization, comprising a clock identifier, consisting of a shift register, an error detector in the clock group and a response weight generator for the clock signal, while the signal input of the clock identifier is connected to the information of the shift register, the output of which is connected to the input of the error detector in the clock group, the second output which is connected to an additional output of the identifier, and the first output of the error detector in the sync group is connected to the data input of the response weight former the clock signal, the clock input of which is connected to the clock input of the shift register and is the clock input of the clock identifier, and the output of the response weight generator is the main output of the clock identifier, which is connected to the first input of the adder, the output of which is connected together to the first input of the third comparison unit and the signal the input of the block of shift registers, the main output of which is connected to the second input of the adder, and the additional output of the block of shift registers is connected to the signal the decisive node, the output of the decisive node is connected to the reset inputs of the cyclic pulse shaper, cycle counter, third comparison block and the shift register block, the clock input of which is combined with the clock inputs of the clock identifier, the decisive node, the counter of distorted clock pulses, the first AND element, counter clock pulses and a shaper of cyclic pulses, and the control input of the decisive node is connected to the output of the threshold selection unit, while the data input of the counter of distorted clock pulses is connected to an additional output of the clock identifier, and the output of the counter of distorted clock pulses is connected to the address input of the threshold selection unit, as well as the counter of the total number of clock pulses, the output of which is jointly connected to the reset input of the counter of distorted clock pulses, and also with the control input of the threshold selection block, and the output of the cyclic pulse shaper jointly connected to the control input of the counter of distorted clock pulses, the counting input of the cycle counter, the control input of the third comparison unit, the installation input of the trigger trigger and the second control input of the deciding node, the output of the third comparison unit is connected to the first control input of which, the output of the clock counter is connected to the reset reset input, and the trigger output is connected together to the reset input of the clock counter and the second input of the first AND element, output which is connected to the clock input of the counter of the total number of clock pulses, and the signal input of the clock identifier, the clock input and output of the cyclic pulse shaper are respectively channel input, clock input and output of the device, characterized in that it contains a block for selecting the permissible number of undistorted clock pulses and a determinant of the threshold for loss of synchronism, while the output of the counter for distorted clock pulses is also connected to the address input of the block for selecting the allowable number of undistorted clock pulses, the output of the cyclic pulse shaper also connected to the control input of the determinant of the loss of synchronism threshold, and the output of the counter of the total number of clock pulses is also connected to the control input b Loka selection of the permissible number of undistorted clock pulses, the output of which is connected to the first input of the determinant of the threshold of loss of synchronism, the second input of which is connected to the output of the loop counter, and the output of the determinant of the threshold of loss of synchronism is connected to the second input of the third comparison unit.