RU2280956C1 - Device for synchronization by cycles - Google Patents

Abstract

FIELD: electric communications, possible use in receiving devices for synchronization by cycles of system for transferring discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, forbidding element, first AND element, adder, shift registers block, generator of clock pulses, OR element, cycles counter, counter of distorted synchronization signals, block for selecting allowed number of distorted synchronization signals, block for selecting threshold, block for selecting counting coefficient, counter by exit from synchronization status, and also solving assembly, containing first comparison block, memory block, subtraction block, second comparison block, comparison counter, second AND element, third AND element, second OR element.

EFFECT: increased reliability of operation of device for synchronization by cycles due to excluded possibility of overflow of shift registers block in synchronous operation mode.

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Description

The invention relates to telecommunications and can be used in synchronization receivers on cycles of discrete message transmission systems.

A device for synchronization in cycles by AS USSR 436393 Class G 11 C 19/00, publ. 07/15/1974, Bull. No. 46, containing, like the proposed device, a clock identifier, an adder, a block of shift registers, a decision node, the output of a clock identifier connected to the first input of the adder, the output of which is connected to the signal input of a block of shift registers, the main output of which is connected to the second input of the adder . In addition, in the known device, the main output of the block of shift registers is connected to the signal input of the decision node. In this case, the adder is made in the form of an n-bit reversible counter, which performs the function of counting the responses of the synchronization identifier at each of the pulse positions of the observation interval cycles, and n shift registers of the shift register block store the counting results for the duration of the cycle. In the clock intervals specified by the clock pulses from the clock generator, the bits of the n-bit counter are written off to the first cells of the corresponding shift registers and the values of the last cells of the shift registers are written to the same counter. If in the clock interval there is a response of the clock identifier, then one is added to the n-bit counter, and thus the value of the binary number corresponding to the number of responses accumulated earlier at this position of the cycle is increased by one. If at the position of the loop there is no identity response, then the number written in the parallel binary code to the n-bit counter from the last register cells is reduced by one. After a cycle in the register cells in parallel binary code, the results of the counting of the responses of the identifier at all N pulse positions are recorded. Based on the analysis of these results, the decisive node determines the position number, which corresponds to the largest binary number of responses of the clock identifier, and thus makes a decision on the position of synchronism. The output of the decider is the output of the device. A disadvantage of the known device is the low reliability of operation, due to the possibility of overflow of the block of shift registers, leading to a violation of the correct operation of the decisive node and the entire device as a whole. This is due to the fact that the synchronization signal from the output of the decision node does not zero out the block of shift registers. At the same time, the block of shift registers continues to accumulate the responses of the synchronization identifier. Therefore, after a certain number of search cycles in many cells of the block of shift registers (not only at the position of the true clock signal), the setting of the maximum possible accumulation values will be observed, which will lead to disruption of the correct operation of the decision node and the entire device as a whole, because the decider after overflow cannot determine the position of the clock.

Closest to the proposed is a device for synchronization in cycles according to the patent of the Russian Federation No. 2231228 class H 04 L 7/08, publ. 06/20/2004, Bull. No. 17, a prototype containing, like the proposed device, a clock identifier, a prohibition element, a first AND element, an adder, a block of shift registers, a decision node, a pulse shaper, an OR element, a cycle counter, a counter of distorted clock signals, a block for selecting the allowable number of undistorted clock signals, threshold selection unit, account coefficient selection unit, counter for synchronism output. Moreover, the decisive node contains a first comparison unit, a memory unit, a subtraction unit, a second comparison unit, a comparison counter and a second element I. The output of the synchronization identifier is jointly connected to the second input of the inhibit element, the second input of the first element And, as well as the first input of the adder, the output which is connected to the signal input of the block of shift registers. The main output of the block of shift registers is connected to the second input of the adder, and the additional output is connected to the signal input of the decision node. The signal input of the decision node is the first input of the first comparison unit. The output of the first comparison unit is connected to the control input of the memory unit, the output of which is connected to the second input of the first comparison unit and the first input of the subtraction unit. The second input of the subtraction block is combined with the data input of the memory block, the first input of the first comparison block and is the signal input of the decision node. The output of the subtraction block is connected to the second input of the second comparison block, the output of which is connected to the reset input of the comparison counter, the output of which is connected to the second input of the second element I. In this case, the control and clock inputs of the deciding node are the first input of the second comparison block and the clock input of the comparison counter . An additional control input of the decisive node is the first input of the second element I. In this case, the output of the decisive node is jointly connected to the reset inputs of the cyclic pulse shaper, the block of shift registers, and also to the second input of the OR element. The output of the cyclic pulse shaper is jointly connected to the first input of the first AND element, the first input of the inhibit element and the input of the loop counter. The output of the cycle counter is connected to the control input of the counter of distorted clock signals. The output of the counter of distorted clock signals is jointly connected to the address inputs of the block for selecting the allowable number of undistorted clock symbols, the threshold selection block and the account coefficient selection block. The output of the block for selecting the allowable number of undistorted clock symbols is connected to the control input of the clock identifier. The output of the inhibit element is jointly connected to the counting inputs of the counter for exiting synchronism and the counter of distorted clock signals. The output of the first AND element is connected to the first input of the OR element, the output of which is connected to the counter reset input to exit synchronism. The output of the counter coefficient selection block is connected to the input of the counter data for the exit from synchronism. The clock input of the cyclic pulse shaper is combined with the clock inputs of the clock identifier, the block of shift registers, and the decision node. The control input of the decisive node is connected to the output of the threshold selection unit, and the additional control input of the decisive node is connected to the output of the counter for synchronism output. In this case, the signal input of the clock identifier, the clock input of the cyclic pulse shaper and the output of the cyclic pulse shaper are respectively the signal input, clock input and output of the device. In addition, in the known device, the output of the decisive node is the output of the second element And, which is connected to the reset input of the memory block. The disadvantage of the prototype is the low reliability due to the possibility of overflow of the block of shift registers in synchronous mode, leading to a violation of the correct operation of the decisive node and the entire device as a whole. This is due to the fact that the synchronization signal of the decisive node, resetting the block of shift registers, can only be generated if the counter detects a synchronism failure and the decisive node detects the synchronization signal upon exiting the synchronism. In synchronous mode, the counter for exiting synchronism is reset to zero. Therefore, even when the crucial node detects the true clock signal at its output, the synchronization signal is not formed. In this case, the block of shift registers is not reset, but continues to accumulate responses. Therefore, after a certain number of search cycles in many cells of the block of shift registers (not only at the position of the true clock signal), the setting of the maximum possible accumulation values will be observed, which will lead to disruption of the correct operation of the decision node and the entire device as a whole, because the decider after overflow cannot determine the position of the true clock signal, both in synchronous mode and after synchronism failure.

A feature of the transmission of a deterministic cyclic clock signal is the frequency of its repetition at the same positions of the group signal transmission cycle. In this case, the clock identifier can recognize in the received group signal not only true sync groups, but also false ones randomly generated at the information positions of the cycle. When generating responses of the synchronized signal at the output of the identifier in the form of units (to the identified synchronization group) and zeros (to the unidentified synchronization group), the required reliability of decision making by the decisive node is achieved due to the accumulation of responses in the block of shift registers. Recognition by the identifier of the clock signal of the code groups at the position of the clock signal leads to the accumulation of responses in the cell of the block of shift registers corresponding to the true sync group. In this case, the recognition by the identifier of the synchronization signal of the code groups at the information positions of the cycle leads to the accumulation of responses in the cells of the block of shift registers corresponding to the false synchronization groups. The decisive node defines the cell with the maximum accumulation of responses. This cell corresponds to the position in the cycle, which is taken by the deciding node as the position of the clock signal with the greatest probability. The decisive node can determine the position of the true cyclic clock signal only if the accumulation is exceeded by a certain value in one of the cells of the block of shift registers over the accumulations in all other cells. For the correct operation of the decisive node, it is necessary that, when determining the true clock signal, the block of shift registers is reset (zeroed), and the process of accumulating the responses of the identifier begins again. In this case, when synchronism fails, the reset of the block of shift registers can occur only after the detection of the device's output from synchronism. It should be noted that for reliable operation of the device, the reset of the block of shift registers in synchronous operation should also be carried out. Failure to perform this procedure may lead to overflow of the cells of the block of shift registers, which will lead to disruption of the correct operation of the decisive node and the entire device as a whole. These factors impose increased requirements for the reliable operation of the block of shift registers and to prevent its overflow in synchronous operation, which ultimately contributes to the reliable operation of the entire device for synchronization in cycles.

The device for synchronizing in cycles contains a clock identifier, a prohibition element, an AND element, an adder, a block of shift registers, a decision unit, a cyclic pulse shaper, an OR element, a cycle counter, a counter of distorted clock signals, a block for selecting the allowable number of undistorted clock symbols, a threshold selection unit, block selection of the coefficient of the account, the counter to exit synchronism. Moreover, the decisive node contains a first comparison unit, a memory unit, a subtraction unit, a second comparison unit, a comparison counter and a second element I. The output of the synchronization identifier is jointly connected to the second input of the inhibit element, the second input of the first element And, as well as the first input of the adder, the output which is connected to the signal input of the block of shift registers. The main output of the block of shift registers is connected to the second input of the adder, and the additional output is connected to the signal input of the decision node. The signal input of the decision node is the first input of the first comparison unit. The output of the first comparison unit is connected to the control input of the memory unit, the output of which is connected to the second input of the first comparison unit and the first input of the subtraction unit. The second input of the subtraction block is combined with the data input of the memory block, the first input of the first comparison block and is the signal input of the decision node. The output of the subtraction block is connected to the second input of the second comparison block, the output of which is connected to the reset input of the comparison counter, the output of which is connected to the second input of the second element I. In this case, the control and clock inputs of the deciding node are the first input of the second comparison block and the clock input of the comparison counter . An additional control input of the decisive node is the first input of the second element I. In this case, the output of the decisive node is jointly connected to the reset inputs of the cyclic pulse shaper, the block of shift registers, and also to the second input of the OR element. The output of the cyclic pulse shaper is jointly connected to the first input of the first AND element, the first input of the inhibit element, and the input of the loop counter. The output of the cycle counter is connected to the control input of the counter of distorted clock signals. The output of the counter of distorted clock signals is jointly connected to the address inputs of the block for selecting the allowable number of undistorted clock symbols, the threshold selection block and the account coefficient selection block. The output of the block for selecting the allowable number of undistorted clock symbols is connected to the control input of the clock identifier. The output of the inhibit element is jointly connected to the counting inputs of the counter for exiting synchronism and the counter of distorted clock signals. The output of the first AND element is connected to the first input of the OR element, the output of which is connected to the counter reset input to exit synchronism. The output of the counter coefficient selection block is connected to the input of the counter data for the exit from synchronism. The clock input of the cyclic pulse shaper is combined with the clock inputs of the clock identifier, the block of shift registers and the decision node. The control input of the decisive node is connected to the output of the threshold selection unit, and the additional control input of the decisive node is connected to the output of the counter for synchronism output. In this case, the signal input of the clock identifier, the clock input of the cyclic pulse shaper and the output of the cyclic pulse shaper are respectively the signal input, clock input and output of the device.

The technical result in the implementation of the invention is to increase the reliability of the device for synchronization in cycles - is achieved by introducing the third element AND, as well as the second element OR, into the decisive node. The output of the comparison counter is also connected to the first input of the third element And, and the second input of the third element And is connected to the output of the device. The output of the third AND element is connected to the second input of the second OR element, to the first input of which the output of the second element is connected I. The output of the second OR element is connected to the reset input of the memory unit. The output of the second OR element is the output of the decisive node. Thanks to the introduction of the third AND element, as well as the second OR element, into the decisive node, the reliability of the device for synchronization in cycles is increased, in synchronous operation, when a true clock signal is detected, the block of shift registers does not overflow. The block of shift registers is reset by a synchronization signal generated at the output of the second OR element. The fact that the critical node detects precisely the true clock signal in the synchronism mode is determined using the third element I. When signals are simultaneously received from the output of the comparison counter and from the output of the synchronization device in cycles to the inputs of the third element And at its output a synchronization signal is generated. In this case, with the help of the second OR element, the operation of switching on the synchronization signal output, which is generated either in the synchronism failure mode (from the output of the second AND element), or in synchronous operation mode (from the output of the third AND element), is performed.

The analysis of the prior art by the applicant, including a search by patent and scientific and technical sources of information, and the identification of sources containing information about analogues of the claimed invention, allowed to establish that the applicant did not find an analogue characterized by features identical to all essential features of the claimed invention. The selection from the list of identified analogues of the prototype, as the closest in the set of essential features of the analogue, allowed to identify the set of essential distinguishing features in relation to the applicant's technical result in the claimed device set forth in the claims. Therefore, the claimed invention meets the criterion of "novelty."

To verify the compliance of the claimed invention with the criterion of "inventive step", the applicant conducted an additional search for known solutions to identify signs that match the distinctive features of the claimed device from the prototype. The search results showed that the claimed invention does not follow for a specialist explicitly from the prior art determined by the applicant. The effect of the transformations provided for by the essential features of the claimed invention on the achievement of a technical result is not revealed. In particular, the claimed invention does not provide for the following transformations: the addition of a known product with any known part, attached to it according to known rules, to achieve a technical result in respect of which the effect of such additions is established; the replacement of any part of a known product with another known part to achieve a technical result in respect of which the effect of such a replacement is established; the exclusion of any part of the funds with the simultaneous exclusion of the function due to its presence and the achievement of the usual result for such exclusion; the increase in the same type of elements to enhance the technical result due to the presence in the tool of just such elements; the implementation of a known tool or part of a known material to achieve a technical result due to the known properties of the material; the creation of a tool consisting of known parts, the choice of which and the connection between them are based on known rules, recommendations and the technical result achieved in this case is due only to the known properties of the parts of this object and the relationships between them; a change in the quantitative features or the relationship of the features, if the fact of the influence of each of them on the technical result is known and new values of the features or their relationship could be obtained from known dependencies. Therefore, the claimed invention meets the criterion of "inventive step".

The invention is illustrated in the drawing, which shows a structural diagram of a device for synchronization in cycles. Information confirming the possibility of carrying out the invention with obtaining the above technical result are as follows.

The device for synchronizing in cycles contains a clock identifier 1, a prohibition element 2, an AND element 3, an adder 4, a shift register unit 5, a decision unit 6, a cyclic pulse shaper 7, an OR element 8, a 9 cycle counter, a distorted clock counter 10, block 11 the selection of the permissible number of undistorted sync symbols, the threshold selection unit 12, the account coefficient selection unit 13, the counter 14 for synchronism output, input 15 is signal, input 16 is clock, output 17 of the device. The decision node 6 comprises a comparison unit 18, a memory unit 19, a subtraction unit 20, a comparison unit 21, a comparison counter 22, an AND element 23, an AND element 24, and an OR element 25. The output of the clock identifier 1 is jointly connected to the second input of the inhibit element 2, the second input of the And 3 element, and also to the first input of the adder 4, the output of which is connected to the signal input of the shift register unit 5. The main output of block 5 of the shift registers is connected to the second input of the adder 4, and the additional output is connected to the signal input of the decision node 6. The signal input of the decision node 6 is the first input of the comparison unit 18. The output of the comparison unit 18 is connected to the control input of the memory unit 19, the output of which is connected to the second input of the comparison unit 18 and the first input of the subtraction unit 20. The second input of the subtraction unit 20 is combined with the data input of the memory unit 19, the first input of the comparison unit 18 and is the signal input of the decision unit 6. The output of the subtraction unit 20 is connected to the second input of the comparison unit 21, the output of which is connected to the reset input of the comparison counter 22. The output of the comparison counter 22 is jointly connected to the second input of the element 23 AND, as well as to the first input of the element 24 I. The output of the element 23 AND is connected to the first input of the element 25 OR, to the second input of which the output of the element 24 I. is connected. The output of the element 25 OR is connected to the reset input of the memory block 19. In this case, the control and clock inputs of the decision node 6 are, respectively, the first input of the comparison unit 21 and the clock input of the comparison counter 22. The first additional control input of the decision node 6 is the first input of the element 23 I. The second additional control input of the decision node 6 is the second input of the element 24 I. The output of the decision node 6 is the output of the OR element, which is connected to the reset inputs of the shaper 7 cyclic pulses, block 5 registers shift, as well as to the second input of element 8 OR. The output of the shaper 7 cyclic pulses is jointly connected to the first input of the 3 And element, the first input of the inhibit element 2, the input of the counter 9 cycles, and the second additional control input of the decision node 6. The output of the 9 cycles counter is connected to the control input of the counter 10 distorted clock signals. The output of the counter 10 distorted clock signals is jointly connected to the address inputs of the block 11 of the selection of the allowable number of undistorted clock symbols, block 12 of the selection of the threshold and block 13 of the selection of the account coefficient. The output of block 11 for selecting the permissible number of undistorted sync symbols is connected to the control input of the sync identifier 1. The output of the prohibition element 2 is jointly connected to the counting inputs of the counter 14 for exiting synchronism and the counter 10 of distorted clock signals. The output of element 3 AND is connected to the first input of element 8 OR, the output of which is connected to the reset input of counter 14 to exit synchronism. To the input of the data of the counter 14 at the exit from the synchronism is connected the output of the block 13 of the selection of the account coefficient. The clock input of the generator 7 cyclic pulses is combined with the clock inputs of the identifier 1 of the clock signal, block 5 of the shift registers and the decision node 6. The control input of the decision node 6 is connected to the output of the threshold selection unit 12, and the first additional control input of the decision node 6 is connected to the output of the counter 14 exit from synchronism. In this case, the signal input of the identifier 1 of the clock signal, the clock input of the driver 7 cyclic pulses and the output of the driver 7 cyclic pulses are respectively the signal input 15, the clock input 16 and the output 17 of the device.

The device synchronization cycles works as follows. The signal input of the identifier 1 of the clock signal receives a group digital signal containing deterministic groups of the clock signal repeating with the frequency of the cycles. At the information positions of the group signal, code groups of information symbols identical to the sync group are formed randomly. When a synchronization signal is combined with the structure of the synchronization group at the input of the identifier 1, a response is generated in the form of a “single” pulse, which then goes to the first input of the adder 4, the second input of the inhibit element 2 and the second input of the 3 I element. The sync signal identifier 1 the output of block 11 is the allowable number k of undistorted sync symbols. The clock identifier 1 consists of a shift register, a clock decoder, an encoder and a comparison device. The shift register performs the operation of converting a group digital signal received at the information input of the shift register from a sequence to a parallel code. During each clock interval, one character of the received signal is recorded in the shift register, and with the arrival of the next character, the previous one moves to the next cell of the shift register. Thus, for m clock intervals, an m-character code combination is written to the register (where m is the number of characters in the sync group). From the output of the shift register, the group signal in parallel code is fed to the input of the clock decoder. The decoder is set to recognize the clock. An encoder is connected to the decoder output. The encoder is designed to generate a binary code of the number of correctly detected sync symbols. The comparing device performs the operation of comparing the number of correctly detected synchro-symbols in the synchro-group with the permissible number k of undistorted synchro-symbols. If the number of correctly detected synchronization symbols is greater than or equal to the allowable number k of undistorted synchronization symbols, then a “single” signal (response) is generated at the output of the synchronization identifier 1. Otherwise, a “zero” signal is generated at the output of the identifier 1. The clock identifier 1 can be implemented, for example, as described in the description of the invention to the patent of the Russian Federation No. 2231228 class H 04 L 7/08, publ. 06/20/2004, Bull. No. 17, figure 2.

The adder 4 is a parallel combiner in which the least significant input of the first term (the least significant bits of the n-bit input) and the n-bit inputs of the second component are the first and second inputs of the adder, while the other (n-1) -digit inputs of the first term are connected to the source of "zero" level.

Block 5 of shift registers includes n N-bit (n = [log ₂ N] +1, N is the number of positions in one cycle) shift registers. In this case, the combined clock inputs and the combined reset input of the shift registers are respectively the clock input and reset input of the block 5 of the shift registers, and the signal inputs, outputs of the last bits and the outputs of the first bits of all shift registers are respectively the signal input, the main output and the additional output of the side of 5 registers shear. Thus, the response of the identifier 1 of the clock signal, which occurs in the i-th clock interval, is added to the adder 4 with the result of the previous count of responses at the i-th position of the cycle coming from the main output of the block 5 shift registers. A new result of the response count, greater by one unit of the former, is written as an n-bit binary number in the corresponding first cells (bits) of the shift registers of the block 5 of shift registers. In this case, the binary number previously recorded in the first cells of block 5 of shift registers, as well as all other numbers stored in subsequent cells of the same type, are simultaneously shifted by one bit, and from the main output of block 5 of shift registers to the second input of adder 4, the counting result responses - on the (i + 1) -th clock interval. If the response of the identifier 1 of the clock signal at the (i + 1) -th clock interval is absent, then the previous result of counting the responses at the (i + 1) -th position of the cycle is written to the first cells of the block 5 shift registers, and the remaining numbers stored in the same cells of the block 5 shift registers, are shifted by one bit, etc. Block 5 shift registers provides storage of the results of counting responses at each position of the cycle for the duration of the cycle. The value of n determines the memory capacity of the counting results. At the same time, the results of the response count at each position of the cycle from the additional output of block 5 of the shift registers are sequentially fed to the signal input of the decision node 6. In the decision node 6, for example, in the i-th clock interval, the input binary number in parallel code representing the current result of the response count at the i-th position of the cycle, simultaneously fed to the first input of the comparison unit 18, the data input of the memory unit 19 and the second input of the subtraction unit 20. In the comparison unit 18, the input number is compared with the binary number stored in the memory unit 19, and if it exceeds the number of the memory unit 19, an output is generated at the output of the comparison unit 18, which, when fed to the control input of the memory unit 19, erases the old one and writes new (input) number. After that, at the inputs of block 18 comparison are equal binary numbers. If the input number is equal to or less than the number stored in the memory unit 19, then the contents of the latter does not change. Thus, the largest current result of the response counting at any position of the cycle is copied to the memory unit 19, which is then compared with the counting results at subsequent positions of the cycle. The resulting difference (between the number of the memory block 19 and the input number) at the output of the subtraction block 20 as a binary number in the parallel code is compared in the comparison block 21 with the threshold number d supplied to its first input (which is the control input of the decision node 6) from the output of the block 12 threshold choices. Moreover, if the number from the output of the subtraction unit 20 is less than the threshold number d, then from the output of the second comparison unit 21, a “single” (inhibitory) potential is supplied to the reset input of the comparison counter 22, which sets and holds it in the “zero” state. When in the i-th clock interval the number from the output of the subtraction unit 20 is equal to or greater than the number d, the “zero” (resolving) potential comes from the output of the second comparison unit 21, and the comparison counter 22 calculates one clock pulse arriving at its clock input, which is the clock input of the decision node 6. If the largest binary number recorded in the memory block 19 will exceed each of the N-1 subsequent numbers coming one after another from the additional output of the block 5 shift registers by an amount equal to or greater than the threshold number d, then the counter 22 comparison will produce the following successive N clock pulses. After that, a “single” pulse signal is generated at its output, which goes to the second input of element 23 AND, as well as to the first input of element 24 I. Moreover, if counter 14 exits synchronism, it counts α non-identification of the true sync group once in a row then a logical “unit” signal is generated at its output, which is fed to the first input of element 23 AND, allowing the passage of a “single” pulse signal from the output of the comparison counter to the output of element 23 I. The passage of a “single” pulse signal from the output of the counter is comparable Ia to the output member 24 and carried at receipt output from generator 7 framer frame synchronization signal. The OR element 25 carries out the switching of the “single” pulse signal to the output of the decisive node 6 either from the output of the 23 And element, or from the output of the element 24 I. The signal at the output of the decisive node 6 is the synchronization output signal. In this case, in the first case, the synchronization signal at the output of the decision node 6 is formed when the synchronism state is lost (the loss of the synchronism state is determined by the counter 14 after the synchronism exit). In the second case, the synchronization output signal is generated in synchronous operation mode. The synchronization signal from the output of the decision node 6 is fed to the reset inputs of the memory block 19, the block 5 of the shift registers and the shaper 7 cyclic pulses, as well as to the second input of the element 8 OR. As a result, the memory block 19, the block 5 of the shift registers, and the counter 14, upon exit from the synchronism, are reset to zero. After that, the inhibitory “single” potential starts to arrive from the output of the comparison unit 21, and the comparison counter 22 is also reset to “zero”. The output synchronization signal of the decisive node 6 is the phasing of the shaper 7 cyclic pulses in such a way that the next cyclic pulses begin to arrive at the output 17 of the device, coinciding in time with the responses of the identifier 1 of the clock signal to the true clock groups. Further, the process of searching for the temporary position of the cyclic clock signal in the binary stream of the group signal starts again. In this case, the next synchronization signal of the decision node 6 will be generated under the condition that the sync signal is detected after the loss of the synchronism state (“single” pulse at the output of the 23 And element) or in the synchronous state (“single” pulse at the output of the 24 And element). In the first case, the synchronization signals of the decision node 6 will change the phase of the initial installation of the shaper 7 cyclic pulses. In the second case, the phase of the initial installation of the shaper 7 cyclic pulses will not change. The synchronism state failure can occur if the temporary position of the cyclic clock signal has changed or the clock signal α is distorted once in a row (by more than k clock symbols). Thus, the counter 14 at the exit from the synchronism counts the number of consecutive sync signal failure pulses generated by the prohibition element 2. Upon reaching the state of the account α at the output of the counter 14 to exit the synchronism, a signal appears allowing the formation of the deciding node 6 of the synchronization signal. In this case, when a true clock signal is detected or when a synchronization signal is generated at the output of the decision node 6, the counter 14 is reset to “zero” upon exit from the synchronism. Blocks 18 and 21 of the comparison can be performed, for example, in the form of n-bit binary code comparators, forming the sign "more", "less" with the corresponding sign of the difference in the values of the input operands, as well as a sign of their equality, applied to the first and second inputs of the blocks . The memory unit 19 can be made in the form of an n-bit register with a parallel input. In this case, the data input, control input, reset input, and output of the memory unit 19 is a data input, a clock input, a reset input, and an n-bit register data output, respectively. The subtraction unit 20 can be made in the form of a full n-bit parallel adder. The adder capacity is ensured by the serial connection of the transfer output of the low-order adder to the transfer input of the high-order adder. In order for the adder to perform the subtraction operation, the number from the memory unit 20 arriving at the first input of the subtraction unit is inverted, and the number received from the additional output of the shift register unit 3 to the second input of the subtraction unit is not inverted. The generator 7 cyclic pulses and counter 22 comparison and can be made in the form of series-connected binary decimal synchronous counter and decoder (see, for example, as described in the description of the invention to the patent of the Russian Federation No. 2231228 class H 04 L 7/08, publ. 20.06 .2004, Bull. No. 17, figure 3).

The counter 14 for the exit from synchronism is a binary-decimal synchronous pulse counter, the output of which is connected to the first input of the binary number comparator. The counter is designed to count the next consecutive pulses of a clock failure that come from the output of element 2 of the ban on the clock input of the counter. The comparator is designed to recognize when the counter reaches the maximum count state equal to the count coefficient α, which is supplied from the block 13 for selecting the count coefficient in binary code to the second input of the comparator. The counter reset input from the output of element 8 OR receives pulses for identifying the true clock signal or a synchronization pulse. To memorize the state signal of maximum accumulation by the counter 14, the trigger must be connected to the output of the comparator by the counter 14 to exit the synchronism. The counter and the trigger are reset to the “zero” state when the counter 14 is received at the reset input upon exiting the synchronism of the “reset” signal. The trigger output is the output of the counter 14 to exit synchronism. The counter 14 to exit synchronism can be implemented, for example, as described in the description of the invention to the patent of the Russian Federation No. 2231228 class H 04 L 7/08, publ. 06/20/2004, Bull. No. 17, Fig. 4.

The process of generating threshold numbers d for the decision node 6, the permissible number k of undistorted synchronization symbols for the identification 1 of the clock signal and the count coefficient α for the counter 14 to exit synchronism is as follows. The pulses of a shaper of 7 cyclic pulses are received at the first input of the inhibit element 3, and the pulses (responses) of the sync signal identifier 1 are received at its second input. As a result, only those pulses of the shaper of 7 cyclic pulses that correspond to the distorted clock signals of the received binary information sequence will go to the output of the inhibit element 2. By counting the number R of distorted sync symbols during the counting time of a rather large number of cyclic pulses, it is possible to periodically determine with a certain degree of accuracy the probability (frequency) of erroneous reception of the clock signal by the formula P _oc ≈ R / Q, i.e. make a current assessment of the degree of distortion of the received signal. In this case, the counter 10 distorted clocks counts the distorted clocks, and the counter 9 cycles - the total number Q of clocks transmitted over a certain period of time. The capacity of the 9-cycle counter is chosen equal to the value of Q. After counting every Q cycle pulses, a single pulse is generated at its output, which is fed to the control input of the counter 10 of distorted clock signals. Counter 10 distorted clock signals, designed to count erroneously received clock signals. Counter 10 distorted clock consists of a counting device and a storage device. In this case, the logical counter of signals “1” or “zero” is sent to the counting input of the counter 10 distorted clock signals from the output of the prohibition element 2. In this case, the logical “unity” signal corresponds to the detection of a failure (distortion) of the clock signal, and the logical “zero” signal corresponds to the detection of an undistorted clock signal. Therefore, the counter 10 distorted clock signals provides a count only distorted clock signals corresponding to the true clock groups. These signals are counted using a counting device. The storage device is designed to record and store the result (the number of distorted clock signals R) for the observation period (number of Q cycles). Counter 10 distorted clock signals can be implemented, for example, as described in the description of the invention to the patent of the Russian Federation No. 2231228 class H 04 L 7/08, publ. 06/20/2004, Bull. No. 17, Fig. 5. The inhibit element 2 can be made of series-connected EXCLUSIVE OR elements and element I. In this case, cyclic pulses are applied to the first input of the EXCLUSIVE OR. It is connected to the first input of element I. The second input EXCLUSIVES OR impulses (responses) from the identifier 1 of the clock signal. The EXCLUSIVE OR output is connected to the second input of the AND element. The output of the AND element is the output of the inhibit element 2.

The 9-cycle counter consists of a counting device and a decoder. The counting device is designed to count Q cycles. The decoder is designed to recognize that the counting device has reached the counting state equal to Q and generate a reset signal for the counting device, which is reset synchronously (on the positive edge of the cyclic pulse at the clock input of the counting device). The signal to reach the end of the observation period Q from the output of the 9-cycle counter is fed to the control input of the counter 10 distorted clock signals. The counter 9 cycles can be implemented, for example, as described in the description of the invention to the patent of the Russian Federation No. 2231228 class H 04 L 7/08, publ. 06/20/2004, Bull. No. 17, Fig.6.

Block 11 selects the permissible number of undistorted clock signals, block 12 selects the threshold and block 13 selects the account coefficient depending on the value of the number R recorded in the counter 10 of distorted clock signals, selects, respectively, a certain allowable number k of undistorted clock signals, threshold number d, and coefficient α of the counter exit from synchronism. The selected numbers k, d, and α from the outputs of blocks 11, 12, and 13 in a parallel code are respectively supplied to the control input of the synchronization identifier 1, to the control input of the decision node 6, and to the input of the counter 14 for synchronism output. The block 11 for selecting the permissible number of undistorted clock signals, the block 12 for selecting the threshold and the block 13 for selecting the account coefficient can be made in the form of read-only memory devices (for example, on K573RF13 microcircuits), in the memory elements of which are recorded the results of calculations of the permissible numbers of undistorted clock symbols k, threshold numbers d and the coefficient α of the counter for exiting synchronism, depending on the probability of erroneous reception of the clock signal (see Kalnikov V.V., Tashlinsky A.G. Methods for finding the internal parameters of cyclic synchronization with parallel and recircular search. - Ulyanovsk: UFVUS, 2002. 35 pp. - Dep. at TsVNI MO RF September 23, 02. No. B4898, publ. SRDR, ser. B., issue 61, 2002). In this case, the value of the measured probability of erroneous reception of the clock signal P _OS from the output of the counter 10 of distorted clock signals is supplied to the address inputs of the permanent storage devices of blocks 11, 12 and 13, from the outputs of which the numbers k, d and α are output. Thus, during the Q counting time, a certain allowable number of undistorted sync symbols is supplied to the identifier 1 of the clock signal, the threshold number d is sent to the decision node 6, and the count coefficient α, which can take one of h of discrete values (gradations) depending on the quality of the received signal. The required number of gradations h of the numbers k, d, and α is selected from the calculation of maintaining the probability of detecting a false clock within the required limits for various changes in the value of P _OS . In this case, the laws of the formation of specific values of allowable numbers k _{r of} undistorted synchronization symbols by block 11, threshold numbers d _{r by} block 12 and coefficient α _{r of the} counter for exiting synchronism by block 13 can be written in the form:

k _r = F ₁ (A _r ≤P _oc <B _r ),

d _r = F ₂ (A _r ≤P _oc <B _r ),

α _r = F ₃ (A _r ≤R _oc <B _r),

where F ₁ , F ₂ , F ₃ are pre-selected rules, respectively, for block 11 for selecting the allowable number of undistorted sync symbols, block 12 for selecting a threshold and block 13 for selecting an account coefficient, according to which the value of P _OS = R / Q, taking a value within r- of the interval (r can vary from 1 to h) of measurements, it is brought into correspondence with the values of the permissible number k _{r of} undistorted sync symbols, the threshold number d _r and the coefficient α _{r of the} counter for the exit from synchronism; And _r and B _r - respectively, the lower and upper boundaries of the value of P _OS for the r-th interval.

The required noise immunity of the device, which is determined by the probability of detecting a false sync signal, is ensured by the choice of the law of formation of numbers k _r for block 11 for selecting the allowable number of undistorted sync symbols, numbers d _r for block 12 for selecting a threshold and numbers α _r for block 13 for choosing a count coefficient from the corresponding measured values of P _os falling within the limits of any rth interval with the boundaries of A _r and B _r , according to the principle: the larger the value of P _os , the greater the numbers k _r , d _r and α _r should be.

The time interval for observing the responses of the identifier 1 of the clock signal, at the end of which a decision is made on the phase of the cyclic clock signal, adaptively varies depending on the value of P _OS and in each case (at a certain value of P _OS ) approaches the minimum possible for which the required noise immunity is still provided. The value of Q, which determines the counting coefficient of the counter of 9 cycles, should be selected, on the one hand, large enough to provide the required accuracy of estimating the probability of error P _{os of a} single character, and on the other hand, small enough to ensure the measurement of P _os between two failures of synchronism in cycles and tracking changes in communication conditions. If we assume that synchronism failures in cycles occur relatively rarely, i.e. at time intervals far exceeding the counting time Q of the cyclic clock signals, in practice, the value of Q can be chosen as:

where B ₁ - the upper limit of the value of P _OS within the first measurement interval, which corresponds to the smallest values of the numbers k ₁ , d ₁ and α ₁ ; [] - means rounding to an integer.

The above information indicates the following conditions are met when using the claimed device:

- a tool embodying the claimed device in its implementation, is intended for use in receiving devices synchronization cycles of systems for transmitting discrete messages;

- for the claimed device in the form described in the claims, the possibility of its implementation using the means and methods described in the application or known prior to the priority date is confirmed;

- a tool embodying the claimed invention in its implementation, is able to ensure the achievement of the perceived by the applicant technical result.

Thus, the claimed invention meets the criterion of "industrial applicability".

Claims (1)

A device for synchronizing in cycles, containing a clock identifier, a prohibition element, a first AND element, an adder, a block of shift registers, a decision unit, a cyclic pulse shaper, a first OR element, a cycle counter, a counter of distorted clock signals, a block for selecting the allowable number of undistorted clock symbols, a selection block threshold, block selection of the coefficient of the counter, the counter for the exit from synchronism, and the output of the clock identifier is jointly connected to the second input of the inhibit element, the second input of the first element And, as well as the first input of the adder, the output of which is connected to the signal input of the block of shift registers, the main output of which is connected to the second input of the adder, and the additional output of the block of shift registers is connected to the signal input of the decision node, consisting of the first comparison unit, memory unit, subtraction unit, the second comparison unit, the comparison counter and the second element And, while the output of the first comparison unit is connected to the control input of the memory unit, the output of which is jointly connected to the second input of the first block with equalization and the first input of the subtraction unit, the second input of which is combined with the first input of the first comparison unit, as well as with the data input of the memory unit and is the signal input of the decision node, the clock and control inputs of which are the clock input of the comparison counter and the first input of the second comparison unit, respectively the second input of which is connected to the output of the subtraction unit, and the output of the second comparison unit is connected to the reset input of the comparison counter, the output of which is connected to the second input of the second AND element, the first input The first additional control input of the decisive node is expensive, while the output of the decisive node is connected to the second input of the first OR element, as well as to the reset inputs of the cyclic pulse shaper and the block of shift registers, the clock input of which is combined with the clock inputs of the clock identifier, decisive node, and cyclic shaper pulses, the output of which is jointly connected to the first input of the first AND element, the first input of the inhibit element and the input of the cycle counter, the output of which is connected to the control input the counter of distorted clocks, and the output of the inhibit element is jointly connected to the counting inputs of the counter of distorted clocks and a counter for synchronism output, the output of which is connected to the first additional control input of the decisive node, and the output of the counter of distorted clocks is jointly connected to the address inputs of the block for selecting the number of undistorted clock symbols , an account coefficient selection unit and a threshold selection unit, the output of which is connected to the control input of the decision node, and the output of the selection unit the permissible number of undistorted clock symbols is connected to the control input of the clock identifier, while the output of the first AND element is connected to the first input of the OR element, the output of which is connected to the counter reset input for synchronism output, the input of which is connected to the output of the account coefficient selection block, the signal input the clock identifier, the clock input of the pulse shaper and the output of the shaper are respectively the signal input, clock input and output property, characterized in that the second OR element and the third AND element are introduced into it, while the output of the comparison counter is also connected to the first input of the third AND element, the second input of which is the second additional control input of the decision node, which is connected to the output of the device, and the output the third AND element is connected to the second input of the second OR element, with the first input of which the output of the second AND element is connected, and the output of the second OR element is connected to the reset input of the memory unit, while the output of the second OR element is output node is Busy decisive.