RU2450465C2 - Frame synchronisation device - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: frame synchronisation device, having a shift register, a decoder, generating equipment, a clock-frequency discriminator, a channel distributor, four AND elements, two logic inverters, two OR elements, lock-in and -out accumulators, a first adder, a first threshold device, two multipliers, a flip-flop and a frequency divider, also includes a second adder, a second threshold device, a fifth AND element and the number of shift register cells is equal to the number of code word symbols (n, k) of a linear block code used in a digital transmission control channel.

EFFECT: reduced probability of false frame synchronisation of digital transmissions in which frames contain symbols of combined digital transmissions and n control channel symbols, including a clock signal combination consisting of m successive symbols, housekeeping symbols, and verification symbols of a linear block code.

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Description

The invention relates to digital communications, and in particular to devices for cyclic synchronization of digital information transmission systems with temporary compression.

Known devices for cyclic synchronization carry out synchronization by combinations of the clock signal transmitted at certain positions of the digital transmission cycle.

However, there are digital transmissions in which, in order to provide dynamic temporal multiplexing, a cycle is organized that contains n control channel symbols and symbols reserved for combined digital transmissions. The control channel includes a combination of a clock signal consisting of m (m≤2) consecutive characters, service characters and (n-k) check characters (n, k) of a linear block code.

Known devices for cyclic synchronization [RF patent No. 20119046 C1, RF patent No. 2136111 C1] containing a shift register, a cyclic clock signal identifier, a clock signal analyzer, generator equipment, AND, OR elements, inputs and outputs of the device connected in a certain way.

The disadvantage of these devices is the high probability of false cyclic synchronization of digital transmissions with a clock signal consisting of one or two consecutive characters.

The closest in technical essence to the claimed invention is selected as a prototype device for cyclic synchronization [Levin L.S. Digital information transmission systems / L.S. Levin, M.A. Plotkin. - M .: Radio and communications, 1982. - S.102-103, Fig.4.4], containing a clock identifier, consisting of a shift register and a decoder, a hold and synchronism search circuit, generator equipment, a clock isolator, channel distributor, inputs and device outputs.

The disadvantage of this device is the high probability of false cyclic synchronization of digital transmissions with a clock signal consisting of one or two consecutive characters.

An object of the invention is to reduce the likelihood of false cyclic synchronization of digital transmissions, in which the cycle contains symbols of combined digital transmissions and n symbols of the control channel, including a combination of a clock signal consisting of m (m≤2) consecutive symbols, service symbols and (nk) check symbols ( n, k) a linear block code.

The specified technical result is achieved in that the device for cyclic synchronization, like the prototype, contains a shift register, a clock isolator and a channel distributor, the signal inputs of which are combined and are the input of a device, a decoder whose inputs are connected to m outputs of the shift register, the first, second and the third elements And, the first inputs of which are combined with the first inputs of the first and second elements NO, while the second inputs of the first element And and the first element NO are combined and connected to the output of the generator equipment, the output of the first AND element is connected to the second input of the first OR element, the output of which is connected to the zeroing input of the drive by synchronism output, the accumulating input of which is connected to the output of the first element NO, and the output is connected to the input of the first multiplier, the output of which is connected with the first input of the first adder, the output of which is connected to the input of the first threshold device, the output of which is connected to the first input of the fourth element And, the output of which is connected to the reset input the generator equipment ode and the first input of the first OR element, the combined second inputs of the second and fourth elements AND and the second element NO are connected to the output of the frequency divider, the output of the second element NO is connected to the first input of the trigger, the output of which is connected to the second input of the third element AND, the output of which connected to the second input of the trigger, resetting the input of the frequency divider and the second input of the second OR element, the first input of which is connected to the output of the second AND element, and the output is connected to the drive input by input In synchronism, the output of which is connected to the input of the second multiplier, the output of which is connected to the second input of the first adder, the output of the clock isolator is connected to the combined clock inputs of the frequency divider and generator equipment, the address outputs of which are connected to the inputs of the channel distributor.

The peculiarity lies in the fact that the number of cells in the shift register is equal to the number of characters of the code word (n, k) of the linear block code used in the digital transmission control channel, and a second threshold device, a fifth AND element, and a second adder, the inputs of which are connected to n outputs of the shift register, and (nk) outputs are connected to the inputs of the second threshold device, the output of which is connected to the second input of the fifth element And, the first input of which is connected to the output of the decoder, and the output is connected to the first first inputs of the first, second, third AND elements and the first, second elements NO.

A synchronization system using a cyclic clock signal is described by two probabilities - the probability of skipping a clock signal and the probability of false cyclic synchronization [P. Bylanski Digital transmission systems / P. Bylanski, D. Ingrem; Per. from English / Ed. A.A. Wiesel. - M .: Communication, 1980. - S.99-101; Sklyar B. Digital Communication. Theoretical foundations and practical application / B. Sklyar. - Ed. 2nd, rev .: Per. from English - M .: Williams Publishing House, 2003. - S.659-663; Krukhmalev V.V. Digital transmission systems / V.V. Krukhmalev, V.N. Gordienko, A.D. Mochenov. - M .: Hot line - Telecom, 2007. - S.251-253].

Provided that the probabilities of occurrence of “0” and “1” at any position are the same and equal to 0.5, the probability of false cycle synchronization caused by m bits of a random data sequence during the analysis of one cycle is described by expression (1).

where t is the number of errors allowed in the cyclic clock signal by the synchronization circuit.

Reducing the likelihood of false cyclic synchronization of digital transmissions with a cyclic clock signal, consisting of one or two characters, is possible due to the use of the properties of the control channel, which uses a (n, k) linear block code.

The verification matrix (n, k) of the linear block code has the form:

, состоящий из n элементов. Так как каждый проверочный вектор

отражает проверку на четность, введенную для любой кодовой комбинации, то при отсутствии ошибок скалярное произведение любой кодовой комбинации

на этот вектор, определяемое выражением (2), равно нулюEach row of the verification matrix H _{[nk, n]} is a verification vector

consisting of n elements. Since each verification vector

reflects the parity check introduced for any code combination, then in the absence of errors the scalar product of any code combination

to this vector defined by expression (2) is zero

For a n-character codeword, 2 ⁿ events are possible. Of these, 2 ^k events correspond to resolved. Then, provided that errors in the code combinations of the linear block code are not allowed by the cycle synchronization scheme, the probability of false cycle synchronization in the analysis of one cycle is described by the expression (3)

When checking d characters for parity in a code combination of length n (d≤n) characters, the number of all possible events is 2 ^d ; the number of events satisfying the parity condition is 2 ^d-1 . The probability of simulating the parity of the checked characters by a random data sequence is

If several verification vectors are used, the probability of false cyclic synchronization is described by the expression (4)

where i = 1, 2, ..., n-k is the number of verification vectors used to detect code words of a linear block code.

The minimum value of the probability of false cyclic synchronization is achieved at i = n-k.

и

, т.е.In cyclic synchronization, both by the combination of the clock signal and by the combination of code words of the linear block code used in the digital transmission control channel, the probability of false cycle synchronization is equal to the product of the probabilities

and

, i.e.

, при этом

,

, wherein

,

The proposed device is illustrated by drawings, which depict:

figure 1 is a structural diagram of a device for cyclic synchronization;

figure 2 is a functional diagram of the adder 8;

figure 3 is a functional diagram of a threshold device 9;

figure 4 - dependence of the probability of false cyclic synchronization on the number of analyzed cycles obtained by simulation.

The device for cyclic synchronization (Fig. 1) contains a clock identifier 1, a synchronization hold circuit 2, a synchronism search circuit 3, a clock selector 4, a channel allocator 5. Moreover, the clock identifier 1 contains a shift register 7 with the number of cells equal to the number of code symbols combinations of (n, k) linear block code used in the control channel, decoder 6, second adder 8, second threshold device 9, fifth element 10. The synchronization hold circuit 2 contains the first element 11, the first element NO 12, the first element OR 13, the drive 14 to exit the synchronism, the first multiplier K 15, the first adder 16, the first threshold device 17, the fourth element And 18, the generator equipment 19. The synchronization search circuit 3 contains a second element And 20, the second element is NO 21, the second element OR 22, trigger 23, the drive 24 at the input of synchronism, the third element And 25, the second multiplier K 26, the frequency divider 27. In this case, the input of the shift register 7 is the signal input of the device for cyclic synchronization. The taps from the first to the mth shift register 7 are connected to the input taps of the decoder 6, the taps from the first to the n-th shift register 7 are connected to the input taps of the second adder 8, the output taps of which from the first to (nk) th are connected to the input taps the second threshold device 9. The outputs of the second threshold device 9 and the decoder 6 are connected to the second and first inputs, respectively, of the fifth element And 10, the output of which is connected to the combined first inputs of the first element And 11, the first element NO 12, the second element And 20, the second element NO 21, the third element And 25. To the second inputs of the first element And 11, the first element NO 12 is connected to the synchronizing output of the generator equipment 19. The output of the first element And 11 is connected to the second input of the first element OR 13, the output of which is connected to the resetting input of the drive 14 through an output from synchronism, the accumulating input of which is connected to the output of the first element NO 12. The output of the drive 14 after the exit from synchronism is connected to the input of the first multiplier K 15, the output of which is connected to the first input of the first adder 16. The output of the first the adder 16 is connected to the input of the first threshold device 17, the output of which is connected to the first input of the fourth element And 18. The output of the fourth element And 18 is connected to the reset input of the generator equipment 19 and the first input of the first element OR 13. To the second inputs of the fourth element And 18, the second element And 20, the second element NO 21 is connected to the output of the frequency divider 27. The output of the second element NO 21 is connected to the first input of the trigger 23, the output of which is connected to the second input of the third element And 25. The output of the third element And 25 is connected to the reset input of the frequency divider 27 and the second inputs of the trigger 23 and the second element OR 22, to the first input of which the output of the second element AND 20 is connected. The output of the second element OR 22 is connected to the input of the drive 24 at the synchronism input, the output of which is connected to the input of the second multiplier K 26. The output of the second multiplier K 26 is connected to the second input of the first adder 16. Output to a clock frequency separator 4 is connected to the clock input of the frequency divider 27 and the clock input of the generator equipment 19, the address outputs of which are connected to the address inputs of the channel distributor 5.

A device for cyclic synchronization (figure 1) works as follows. The multiplex digital stream is input to the identifier 1 of the clock signal, consisting of a shift register 7 with the number of cells equal to the number of characters of the code combination (n, k) of the linear block code used in the control channel, decoder 6, second adder 8, second threshold device 9, the fifth element And 10. During each clock interval in the shift register 7 is written one character of the received signal, and with the arrival of the next character, the previous one moves to the next cell. If the shift register 7 contains a code combination (n, k) of a linear block code that includes a combination of a clock signal (first m consecutive characters), then, if received without errors, the first causes the formation of signals at all (nk) outputs of the second adder 8, and the last - the formation of the signal is not the output of the decoder 6. The signal at the output of the decoder 6 reflects the coincidence of the first m characters of the code combination recorded in the shift register 7 with the combination of the clock signal, and each signal at the output of the second adder 8 is the result of scalar code combination of n characters and one of (n-k) test vectors (2).

The second adder 8 in conjunction with the shift register 7 is a typical scheme for calculating the syndrome when decoding linear block codes [Clark, J. Error coding / J. Clark, J. Kane; Per. from English - M .: Radio and Communication, 1987. - P.53-96; Sklyar B. Digital Communication. Theoretical foundations and practical application / B. Sklyar. - Ed. 2nd, rev .: Per. from English - M.: Williams Publishing House, 2003. - S.354-367]. For example, figure 2 presents the functional diagram of the second adder 8 for a special case when the Golei code (24, 12) with a verification matrix of the form is used in the digital transmission control channel:

.

.

In this case, the second adder 8, at the input and output of which 24 and 12 conclusions, respectively, consists of a set of one-bit binary adders connected to its inputs in accordance with the presented verification matrix.

In case of receiving errors with errors, depending on their number and location in the code combination (n, k) of a linear block code, the latter will not cause the formation of signals at certain outputs of the second adder 8. The number of signals generated at the outputs of the second adder 8 is equal to or greater than the established the threshold causes the formation of a signal at the output of the second threshold device 9. At a zero threshold set on the second threshold device 9, a signal is generated at the output of the synchronization identifier 1 only when zhenii combination timing signal.

The second threshold device 9 is a combinational circuit having k inputs and one output and realizing a function [G. Pukhalsky Digital devices: Textbook for technical colleges / G.I.Pukhalsky, T.Ya. Novoseltseva. - St. Petersburg: Polytechnic, 1996. - S.553-556]

,

,

where ν = (x _k , ..., x _i , ..., x ₁ ), x _i is the signal at the ith input of the threshold device 9; l is the set threshold, 1≤l≤k.

Figure 3 presents the functional diagram of the second threshold device 9 for a special case when the Golei code is used in the digital transmission control channel (24, 12). The second threshold device 9 consists of a combination of binary adders, which allows calculating the number of incoming signals, a threshold selection unit, with which a threshold l is set, a digital comparator that compares the number of incoming signals with a threshold l, and a logical OR element. If the number of incoming signals is greater than or equal to the threshold l, then a single signal is formed at the output of the logical OR element, which is the output of the second threshold device 9.

The detection signal of the combination of the clock signal from the decoder 6 and the detection signal of the code combination of the linear block code used in the control channel from the second threshold device 9 are supplied to the fifth element And 10. When the event data is simultaneous at the output of the fifth element And 10, a signal arrives at the first element And 11, the first element is NO 12, the second element is AND 20, the second element is NO 21 and the third element is AND 25. If the cyclic synchronization device is in a state of synchronism, then the signal from the output of the identifier 1 sync the signal coincides in time with the signal from the output of the generator equipment 19, supplied to the first element And 11, the first element is NO 12. In this case, the output of the first element NO 12 connected to the storage input of the drive 14 at the exit of synchronism, there is no signal, and the output the first element And 11 connected through the first element OR 13 with the resetting input of the drive 14 at the exit from the synchronism, a signal is formed, resetting the drive 14 at the exit from the synchronism (usually calculated for four to six consecutive pulses). False combinations of a clock signal and a linear block code generated in a multiplex digital stream due to a random combination of ones and zeros do not coincide in time with the signal at the output of the generator equipment 19, and therefore do not participate in the accumulation process. Due to the coincidence of the temporal positions of the pulse sequences from the outputs of the sync signal identifier 1 and the frequency divider 27 (the division coefficient of which is equal to the division coefficient of the generator equipment 19), the drive 24 at the synchronization input is filled, and the trigger 23 holds the third element And 25 in a closed state, in which false combinations of the clock signal generated in the multiplexed digital stream do not cause a reset of the frequency divider 27. The enable signal from the output of the drive 24 at the synchronism input (usually calculated for two or three consecutive pulses) is fed to the second input of the first adder 16 through the second multiplier K 26, where it is multiplied by a coefficient corresponding to the weight of the signal. In the first adder 16, the signals from the outputs of the drive 14 at the exit from the synchronism and the drive 24 at the entrance to the synchronism are added up taking into account the coefficients of the first multiplier K 15 and the second multiplier K 26. The generator equipment 19 is reset only if the total drive capacity reaches the level set the first threshold device 17. In the event of a synchronism failure, the drive 14 fills out of synchronism and generates an enable signal. However, the fourth element And 18 remains closed until an enable signal from the output of the drive 24 at the synchronism input is supplied to the input of the first adder 16, and the total capacity of the drives does not exceed the level set by the first threshold device 17. In the synchronism search circuit 3 the third element And 25 is opened by the signal from the output of the trigger 23, and the first false clock signal generated in the multiplex digital stream will set the frequency divider 27 and the trigger 23 to the zero state. As a result, the third AND element 25 is closed until a combination of symbols different from the synchronizing one is formed at the positions being analyzed, after which the next false sync signal again sets the frequency divider 27 and trigger 23 to the zero state. When a true clock signal is detected, the drive 24 at the input to the synchronism is filled and generates an enable signal, which passes through the second multiplier K 26 to the first adder 16. If, by this moment, the drive 14 is out of synchronism and the sum of the signals at the input of the first threshold device 17 exceeds a predetermined threshold, the signal from the output of the frequency divider 27 sets the generator equipment 19 to zero. With long-term distortion of the clock signal, the state of cyclic synchronism is maintained for an arbitrarily long time due to the absence of an enable signal from the synchronism search circuit 3.

The present invention, compared with the prototype, has a lower probability of false cycle synchronization of digital transmissions, in which the cycle contains symbols of combined digital transmissions and n symbols of the control channel, including a combination of a clock signal consisting of m (m≤2) consecutive symbols, service symbols, and ( nk) check symbols (n, k) of the linear block code, since the cycle synchronization is carried out both by combinations of the clock signal and the code words (n, k) of the linear block code used in the channel management.

To determine the quality indicators of the device for cyclic synchronization, its simulation model was built.

Modeling was performed with the following initial data:

- there are no errors in the communication channel (t = 0);

- the probabilities of occurrence of "0" and "1" at any positions are not the same;

- transmission cycle length L = 2048 bits;

- the length of the sync combination m = 2 (01);

- linear block code used in the digital transmission control channel: Golay code (24, 12);

- the number of test vectors used: i = 2 ÷ 12;

- the number of analyzed cycles N = 1 ÷ 6;

- threshold on the threshold device in the clock identifier: 0.

As a result of simulation, the device showed the characteristics that are presented in figure 4 (the dotted line shows the characteristics of the prototype).

Modeling confirmed the achievement of a technical result — a reduction in the likelihood of false cyclic synchronization — in the practice of the invention.

Claims (1)

A device for cyclic synchronization containing a shift register, a clock selector and a channel distributor, the signal inputs of which are combined and are the input of a device, a decoder whose inputs are connected to the m outputs of the shift register, the first, second, and third AND elements, the first inputs of which are combined with the first the inputs of the first and second elements NO, while the second inputs of the first element And and the first element NO are combined and connected to the synchronizing output of the generator equipment, the output of the first element And connected to the second input of the first OR element, the output of which is connected to the zeroing input of the drive after synchronism, the accumulating input of which is connected to the output of the first element NO, and the output is connected to the input of the first multiplier, the output of which is connected to the first input of the first adder, the output of which is connected to the input of the first threshold device, the output of which is connected to the first input of the fourth element And, the output of which is connected to the resetting input of the generator equipment and the first input of the first element And And, the combined second inputs of the second and fourth elements AND and the second element NO are connected to the output of the frequency divider, the output of the second element NO is connected to the first input of the trigger, the output of which is connected to the second input of the third element And, the output of which is connected to the second input of the trigger, resetting input frequency divider and the second input of the second OR element, the first input of which is connected to the output of the second AND element, and the output is connected to the drive input at the synchronism input, the output of which is connected to the second input, multiply I, whose output is connected to the second input of the first adder, the output of the clock isolator is connected to the combined clock inputs of the frequency divider and generator equipment, the address outputs of which are connected to the inputs of the channel distributor, characterized in that the number of cells of the shift register is equal to the number of characters of the codeword (n , k) a linear block code used in the digital transmission control channel, and a second threshold device, a fifth AND element and a second adder, the inputs of which are additionally introduced connected to n outputs of the shift register, a (nk) outputs connected to the inputs of the second threshold device, the output of which is connected to the second input of the fifth element And, the first input of which is connected to the output of the decoder, and the output is connected to the combined first inputs of the first, second, third elements AND and the first, second elements NO.

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