SU978349A1 - Ring-type pulse distributor - Google Patents

Description

(5) RING DISTRIBUTOR OF PULSES

one

This invention relates to automation and computing.

Known ring distributors of pulses containing a T-trigger and in each channel RS trigger fl.

The disadvantages of this device include such functional capabilities.

Closest to the present invention is a ring pulse distributor containing a TJ trigger, the T input of which is connected to the clock bus, and the S input is connected to the main bus of the installation, as well as in each channel an RS trigger on two IS-NOT elements, the second the input of the first of which is connected to the output of the second element AND –NE of the previous channel, the third input to the second input of the second element AND –NE of this channel, the output of the first element AND –NE of the subsequent channel and the main output bus of the subsequent channel, and the fourth input of the first AND element -NO to In addition to the first and last channels, the third input of the second NAND element in odd channels is connected to the Trigger borrowing output, and in even channels to the transfer output of the T-Trigger 2j.

The disadvantages of the known device are narrow functional capabilities.

The purpose of the invention is to expand the functionality of the ring pulse distributor.

This goal is achieved by the fact that in the ring, pulse distributor, containing a 1-trigger, the input of which is connected to the clock bus, and the S input is connected to the main bus of the installation, as well as in each channel the RS-trigger on two IS-NOT elements, the second input of the first one is connected to the output of the second AND-NOT element prior to its channel, the third input is connected to the second input of the second AND-NOT element of this 1st channel, output-. 3973 the house of the first AND-NOT element of the subsequent channel and the main output bus of the subsequent channel, and the fourth input of the first AND-NOT element, besides the first and last channels, is connected to the main bus of the installation; the third input of the second IS-NOT element in odd channels is connected to the output of the T-trigger trigger, and in even channels with the transfer output of the T-trigger, inserting an additional installation bus that is connected to the R input of the T |. trigger, the fourth input of the first AND-first element of the first channel, the fifth input of the first element AND-NOT the second channel and even The vertical inputs of the second AND-NOT elements of the odd channels start from the third one, while the main installation bus is connected to the fourth inputs of the second AND-NOT elements of the first and last channels, and the outputs of the second AND-NOT elements are connected to additional output buses. I The drawing shows the functional diagram of the proposed distributor. The circuit contains the following elements: T-trigger 1, T-input of which is connected to the clock bus, 2, and S-input is connected to pin 3 of the installation; in each channel I there is an S-trigger on two I-elements NOT-t and 5; the second input of the first one is connected to the output of the NAND 5 element of the previous channel, the third input is connected to the second input of the NAND element 5 of this channel, the output of the NANDA element of the subsequent channel and the output bus 6 of the subsequent channel, and the fourth input element AND NOT, except for the first and last channels, is connected to the bus 3 installation; the third input element AND-NOT 5 in even-numbered channels is connected to the output of loan T, -trigger 1, and in even-numbered channels - to the transfer output of T -trigger 1; bus 9 of the installation, which is connected to the I-input of the T-trigger 1, the fourth input of the NANDA element of the first channel, the fifth input of the NAND element | the second channel and the fourth inputs of the elements AND-NOT 5 odd channels, starting with the third; The bus 3 of the installation is connected to the fourth inputs of the AND-HE 5 elements of the first and after channels, and the outputs of the K-HE 5 elements are connected to the output buses 10. The T-trigger 1 contains the AND-HE elements 11-16. The ring pulse distributor operates as follows. In the initial state, we have a high potential at the outputs of the AND-HE elements 13 and 14, the AND-HE elements of all channels except the last, the AND-HE element 5 of the last channel and on the bus 3 of the installation. At the next time point, a low potential appears on the clock bus 2, which causes, after a time equal to the delay time for the operation of one element, the appearance at the output of the low-potential element AND-NOT 4. Low potential from the output of the element AND-NOT AND enters the input of the element AND-NOT 5 odd channels and causes a high potential at the outputs of these elements. The high potential from the output of the element -NON 5 of the first channel causes the appearance of a low potential at the output of the AND-HE element k of the first channel. The bottom potential from the output of the element AND-NOT k of the first channel enters the inputs of the elements AND-NO 4 and 5 of the last channel and causes a high potential at the output of the element AND-NOT of the last channel. Next, the negative impulse ends at the output of the NAND 14 element, at its output a high potential appears, which enters the input of the NAND elements 12, 13 and 1b and causes the latter to trigger. At the output of the element AND-NOT 16, a low potential appears. To receive the next second positive impulse, the IS-HE 13 element is ready, which is triggered at the next dv1Y moment. Further, at the output of the element IS-NE 13, a low potential appears, which causes high potentials at the outputs of the elements AND-HE 5 of odd channels. High potential at the output of the item NAND. 5 of the second channel causes a low potential at the output of the element AND-NO 4 of the second channel. The low potential from the output of the IS-NE element k of the second channel enters the input of the IS-NE element 4 of the first channel, at the output of which a high potential appears. Then the low potential terminates at the output of the AND-HI element 13 and therefore the low potential appears at the output of the N-5 element of the last channel, as well as at the outputs of the N-5 elements of the fourth and sixth channels and the N-11 element. the third positive pulse on the clock bus 2, which similarly causes the sequential operation of the elements AND-KE 1 and AND-NOT 5 of the third, fifth and seventh channels, then the elements of AND-NOT (the third and second channel. Thus RS-trigger the third channel is set to c With a high potential at the output of the element IS-NOT k and a high one at the output of the element H-NOT 5. The arrival of the fourth pulse on the clock bus 2 triggers the operation of the element IS-NOT 13, since high potentials act on its inputs at this moment. I-NE 13 rewrites the low potential to the fourth trigger, on the trigger of the element AND-NOT k which has a low potential. Similarly, the low potential from the outputs of the AND-NOT elements of the PS trigger triggers to the next I trigger with the arrival of the next pulse on the clock bus 2, When coming to order A sixth, eighth, positive pulse per clock bus 2 negative pulses appear at the outputs of the AND-NE elements of the fifth, sixth, seventh, eighth channels, respectively. After the ninth positive pulse arrives, a negative pulse appears at the clock bus 2. element AND-NOT k of the first channel and when the next positive pulses arrive on the clock bus 2, the cycle of operation of the ring pulse distributor is repeated. The outputs of the ring-jj of the pulse distributor in this mode are the output busses 6. In the second mode, a negative pulse is fed through the installation bus 9. In this case, a high potential will be established at the outputs of the AND-HE elements 11, 1t, 15 AND-NO 4 of the first, second, sixth and seventh channels, AND-HE 5, starting from the second channel. At the moment of termination of the negative impulse on the bus 9 of the installation, the ring pulse distributor will be set, taking into account the time taken to trigger the elements, into a state with high potentials at the outputs of the AND-NE elements 11, k l 15, AND-NOT k all channels except the last, AND NOT 5 starting from the second channel. Since, as a result, high potentials act at the inputs of the AND-HI element of the second channel, then the potential at the output of a given element at a time equal to a single element has a low potential. Then, a t96 positive potential appears on the clock bus 2, which causes the appearance of a low potential at the output of the NANDI element 1, since high potentials act on its inputs. The low potential from the output of the NAND element H arrives at the inputs of the NAND element 12, 13, 16, NAND 5 of odd channels and causes the output of the NAND element of the first high potential channel, which, in turn, causes the appearance of a low potential at the output of the NAND element of the first channel. The low potential from the output of the NAND element (the first channel enters the input of the NAND element K of the last channel and causes its high potential at the output. The high potential at the output of the NAND element 4 of the last channel causes the appearance of a low potential at the output of the AND element NOT k of the seventh channel, in a swap queue, causes the output of the AND-NE element of the sixth high-potential channel.The high potential from the output of the AND-NE element of the sixth channel is fed to the input of the AND-NE element k of the fifth channel. appears low a potential which causes a high potential at the output of the element I-HE i of the fourth channel.Further appears a low potential on the clock bus 2, which is fed to the input of the element AND IS-HE k, at the output of which the potential is high, which leads the appearance at the outputs of the third-channel elements AND-NOT 5 and the low-potential AND-12 of 12. A rising edge of the negative pulse arrives on the clock bus 2, i.e. a positive potential appears. From the moment the high potentials act on the input of the element IS-NE 13 and therefore from the next moment it does NOT exit the low potential which enters the input of the element IS-HE 5 of the second channel, at the output of which a high potential appears which causes .low potential at the output of the NAND + element of the second channel, which, in turn, causes the sequential operation of the NAND 4 elements of the first, eighth, seventh, sixth and fifth channels. Further, a low potential appears on the clock bus 2, which causes the appearance of a high potential at the output of the NAND 13 element, which, in turn, causes the appearance of a low potential

at the outputs of the element AND-NOT 5 of the fourth channel. The low potential at the output of the NAND 11 element causes the appearance of a high potential at the output of the NAND 12. Then the trailing edge of the third negative impulse arrives on the clock bus 2, which causes the sequential operation of the elements NID 4, 16, NON 5 third anal, and-NOT if third, second, etc. , the sixth channel, with the potential that appears at the output of each next element of this row, inverse to the potential at the output of the previous element. When applying on the clock bus 2 of the trailing edge of the fourth negative impulse, the elements AND-NOT 13, 15, AND-NOT 5 of the fourth channel, AND-NOT of the fourth, third, and t "d. seventh channel. Next, on the clock bus 2, the front of the fifth negative pulse arrives, the AND-HE element 3 is triggered, and a low potential appears at the output of the AND-HE element 5 of the sixth channel. When the sixth negative pulse arrives on the clock bus 2, a negative pulse appears at the output of the NAND 5 element of the seventh channel. When the seventh and eighth negative pulses arrive on the clock bus 2, a negative pulse appears at the outputs of the AND-HEY elements of the eighth and first channels. When the next negative pulses arrive on the clock bus 2, the ring pulse distributor is repeated. In this mode, the outputs of the ring pulse distributor are the output bus 6.

Thus, due to the introduction of an additional installation bus and new structural links in the present invention, the functionality of the ring pulse distributor is enhanced by the possibility of obtaining a series

both positive and negative impulses.

Claims (2)

1.Bukreev I.N. and others. Microelectronic circuits of digital devices. M., Soviet Radio, 1975, p. 29, fig. 6.26. 2. USSR author's certificate No. 680172, cl. H 03 K 17/62, 28.06.77 PROTOTYPE).