SU762203A1 - Pulse number divider - Google Patents

Description

The invention relates to computing and automation.

The divider of the number of pulses is known, which contains a push-pull register, each digit of which consists of a trigger on AND — NOT elements. The divider contains $ two clock busses, the first of which is connected to the inputs for zeroing triggers of odd bits of the register, and the second one - to the inputs of zeroing triggers of even bits of the register. Inputs trigge- discharge ditch each register, except the last, coupled to the trigger unit output register subsequent discharge and zero the output is connected with _{unit] 5} iichnym input trigger subsequent discharge. The divider contains four additional IS-NOT elements, the first inputs of the first and second additional elements are connected to the meter input, and the outputs are connected to the buses for setting the register [D.] triggers to zero.

The disadvantage of this divisor is ’

pulses is a large number of ele2

• cops, and consequently, low reliability. The number of elements is not less than two per unit division ratio, and is exactly 2p + 4 η 1

where b is the division factor of the divider. The purpose of the invention is to increase the reliability of the divider number of pulses.

To this end, the pulse number divider containing a push-pull register ^ each digit of which consists of a trigger on the NAND elements, two clock buses, the first of which is connected to the inputs of zeroing triggers of odd bits of the register, and the second to. inputs of resetting triggers of even bits of the register, except for the last, are connected to a single output of a trigger of a subsequent register discharge, the zero output of which is connected to a single input of a trigger of a subsequent discharge, additional I-NOT elements and a trigger are introduced, the loan output of which is connected

3 '762203

to the first clock bus, and the transfer output - to the second clock bus, with the first 'input of the additional element AND-NOT connected to the single output of the trigger of the last register bit, and the output to the first input of the second additional element AND — NOT whose second input is connected to the second clock bus, and the output to the trigger inputs of the last register bit, to the second input of the first additional AND — NOT element, to the setup input of the first register bit trigger and to the first input of the third additional AND NONE element, the second · the course of which is connected to the first bus, and an output - to a third input of the second additional AND-NO element.

The drawing shows the structural electrical circuit of the divider number of pulses (with a division factor equal to 8).

The pulse number divider contains a push-pull register, each digit of which contains a trigger on the elements

x and NOT. Thus, the first digit is made on the elements AND-NOT 1-1 and 1-2, the second one is 2-1 and 2-2, the third one is 3-1 and 3-2, and so on. The inputs of the AND elements are NOT for each trigger the register, except the last one, is connected to the unit output of the next register trigger.

The inputs of the elements AND-NOT 1-1 and 1-2 are connected to the output of the element Y-NOT 2-1, and the inputs of the elements AND-NOT 2-1 and 2-2 - to the output of the element AND-NOT 3-1, etc. .

The zero output of each trigger, except the last one, is connected to the input of the set to "1" of the next trigger, the output of the element AND-NO 1-2 is connected to the input of the element AND-NOT 2-1, the output of the element AND-NOT 2-2 is connected to the input of the element AND-NOT 3-1, etc.

The divider contains the input bus 5, which is connected to the input of the T _g trigger on the elements AND NOT 6-11, and also contains the input bus 12, which is also connected to the input of the trigger. The output of the loan signal T ^ -trigger, i.e., the output of the AND-HE 8 element, is connected to the zero reset triggers bus of the register.

The output of the transfer signal is a 7т-trigger, / i.e., the output of the AND-HE 9 element is connected to the zero reset triggers bus of the register. The divider also contains the elements AND — NOT 13, 14, and 15. First entry |

element AND —NE 13 is connected to the unit output of the last trigger, i.e., to the output of the NAND element 4-1, the second one, the input is connected to the unit input of the first _5th trigger, i.e. to the input of the AND- NE- 1 element —1, to the inputs of the AND-HE elements 4–1 and 4-2, to the output of the AND-NOT element 15 and. to the primary input of the element IS-NOT 14, and the output of the element IE-NOT 13 is connected to the first input of the element AND-NOT 15, the second input of which is connected to the second clock bus, and the third input to the output of the element AND NOT 14, the second input which is connected to the first clock bus,

15 The input bus 12 is used in the construction of multi-bit dividers.

¹ The device uses AND-NOT elements for positive signals on

20 input and all elements of the scheme have a delay in their operation.

Suppose, at the initial time T, the circuit is in a position with high output potentials

²⁵ elements AND-NOT 8.9, 1-1, 2-1, 3-1,

4-1, 10 and 15 and low potentials at the outputs of the elements AND-NOT 1-2, 2-2, 4-2, 11, 13 and 14.

After the arrival of a positive impulse of ³⁰ ca on the input bus 5 at the time T, after a time equal to the element response delay time at the moment T _g , a low potential appears at the output of the element IS-HE 8, which is fed to the input

^{The 33} elements AND –NE 1-2, 3–2, and 14 cause a high potential at the outputs at the moment.

High potential from the output of the element AND NOT 1-2 arrives at the input of the element

40 AND-NOT 1-1 and at the output of the element AND-NOT 1-1 at time T, a low peak appears. *

the potential, i.e., on, all its inputs from the moment high potentials act. At the moment Тd, a second positive impulse arrives at the input bus 5 and at the output of the element AND — NOT at the moment T ₁₀ a low potential appears, which causes the appearance of a high potential at the output of the elements AND-NO 2-2 and 4-2 at the moment T _1A A high potential at the output of the AND – NOT 2–2 element causes a low potential at the time T <r, the output of the AND – NE 2-1 element that enters the input of the AND – 1-1 element and causes a high potential at the output .

At the time of entry 5 divider

comes the third positive impulse

and in a similar way. sequentially

762203

With signal inversion, the elements AND-NE 8, 3-2, 3-1, 2-1 and 1.1-1 are triggered. . <

At the moment T £ d, the fourth pulse arrives at the input 5 and the elements 5 AND-NOT 9, 4-2, 4-1, 3-ΐ are triggered successively with signal inversion; 2-1 and 1-1.

When appearances at the moment of low potential at the output of the element AND-NOT 1-1, except for the element AND-NOT 3-1, the element AND-NOT 13 also works, and at the output 10 of the element AND — NOT 13 at the moment there is a high potential.

At the moment the fifth pulse arrives at the input 5, and the elements 15 AND-NOT 8, 14, 15, 4-1, 3-1, 2-1, 1-2 work in series with signal inversion.

At the time of entry 5 comes

the sixth impulse and, in a similar manner, in succession with inversion, the elements AND-HE 9, 15, 4-1, 3-1 are triggered. 20

The high potential at the output of the element AND-NOT 15 at the moment Tdg also causes a low potential at the moment of the outputs of the elements AND-NOT 13 and 14, but the input potential of the element AND-NOT 13 at the moment Tsch 25 starts to flow low from the output of the element AND -NOT 4-1 and at the output of the element AND-NOT 13 at the moment there is a high potential.

At the moment Tdd, the 30th seventh positive impulse arrives at the input 5 and the elements AND-HE 8, 14, 15 and 4-1 trigger in succession with inversion.

At the moment 5, an eighth positive impulse arrives at input 5; successively with inversion, the elec- tron triggers. cops 9, 13 and 15. High potential at the output of the element AND — NOT 15 at the moment

causes a low potential at time T (, o not only at the output of the element 40 AND-NOT 13, but also at the output of the element AND-NOT 14.

At the time of entry 5 comes

the ninth positive pulse at the output of the element AND-NOT 8 at the time T && 45

a low potential appears, which at the time T ^ ₇ causes a high potential at the output of the AND-NOT 1-2 element, which causes at the time T _& g at the output. element AND NOT 1-1 low potential and 50 waveform at the outputs of all elements repeated.

With the arrival of eight pulses at the input 5, at the outputs of elements 1-2, 2-2, .3-2,

4-2 and 13 one wide im- 55 appears.

pulse, i.e., the frequency of the input pulses are divided by 8.

Thus, due to a definite connection of the NAND elements and T outputs (. -Riggers, it is possible to obtain a divider with a coefficient equal to 8. If we take a different number of triggers in the register, then / then we get a different division factor.

Claims (1)

Claim The divisor of the number of pulses containing a push-pull register, each digit of which consists of a trigger on the elements. I-NOT, two clock buses, the first of which is connected to the inputs of zeroing triggers of odd bits of the register, and the second - to the inputs of zeroing triggers of even bits of the register, the inputs of the trigger of each register bit, except for the next discharge, and zero the output of which is connected to a single input of a trigger of a subsequent discharge, characterized in that, in order to increase the reliability of the device, additional I-NOT and T ^ elements are introduced into it. the trigger whose loan output is connected to the first clock bus, and the transfer output to the second clock bus, while the first input of the additional AND-NOT element is connected to the single output of the trigger of the last digit of the register, and the output to the first input of the second additional AND element NOT, the second input of which is connected to the second clock bus, and the output is to the trigger inputs of the last digit of the register, to the second input of the first additional AND-NOT element, to the setup input of the trigger of the first digit of the register and to the first input of the third additional An additional NAND element, the second input of which is connected to the first clock bus, and the output is connected to the third input of the second additional NAND element. .