SU978197A1 - Associative on-line memory device - Google Patents

Description

This invention relates to memory devices.

A known associative random access memory containing an associative drive, an address register, a control unit, decoders, write and read amplifiers, switches, signal conditioners and a C 11 register

The disadvantage of this device is low speed.

The closest in technical essence to the present invention is an associative operative memory comprising a memory matrix, X and Y decoders, an address register and a number register, with the outputs of the address register being connected to the inputs of the X and Y decoders that are connected to the memory matrix, and the outputs and inputs of the number register are connected to the corresponding inputs "w and outputs of the memory matrix, and there is a correspondence between the key values and the sequence numbers (i.e., address) of the binary bits of the memory device, m in the memory cell corresponding to characteristics of selected words, recorded on February 1.

A disadvantage of the known device is that the sampling is carried out only when the polling code completely coincides with the key that is the address, and the masking is applied to an arbitrary number of bits of the polling code is invalid, which limits its functionality.

ten

The purpose of the invention is to expand the functionality of the device by implementing the information search mode when masking the polling code.

15

The goal is achieved by the fact that B is an associative random-access memory containing a storage matrix, an address register, descramblers whose outputs are connected to the input inputs of the storage matrix, and inputs from one of the number register inputs other inputs and outputs are connected to the outputs and information inputs

25 of the storage matrix, a polling code modification block is entered, the inputs of which are connected to the outputs of the address register, and the outputs are connected to the inputs of the first and second decoders respectively, the polling code modification block contains groups of elements AND, element OR, group elements OR, shift registers, triggers, a mask counter and register, the first inputs of the AND elements of the first group are the inputs of the block and connected to the first inputs of the AND elements of the second group, the second inputs of which are connected to the outputs of the mask register, and the third inputs to The outputs of the first shift register, the outputs of the elements of the second group are connected to the first inputs of the flip-flops and the inputs of the OR element, the output of which is connected to the input of the second shift register, the output of which is connected to the second inputs of the flip-flops, the outputs of which go to the third inputs of the third And Groups whose second inputs are connected to the counter outputs, and outputs to the first inputs of the elements OR groups, the second inputs of which are connected to the outputs of the elements AND of the first group, the outputs of the elements OR groups are the outputs of the block, volts The second inputs of the elements of the first group are combined and are the input of the gating unit.

The drawing shows the functional diagram of the device.

The device contains a memory matrix 1, the first 2 and the second 3 decoders, register 4 numbers, address register 5 and block b of the modification of the interrogation code, which contains the mask register 7, the first shift register 8, the first group 9 elements AND, the element OR 10, counter 11 , triggers 12, designed to distribute the mask, the second group of 13 elements AND, the group of elements OR 14, the third group of elements AND 15 and the second shift register 16. Matrix 1, decoders 2 and 3, the lower bits of register 4 can be performed on one type of LSI (for example, on a standard LSI RAM).

Block 6, register 5 and high bits of register 4 can be made as a separate LSI,

In associative search mode, the device works as follows,

A poll code is presented to register 5, which is the value of the character (senior) bits of a word, a mask code to register 7. In this mode, the polling code is preliminarily entered into block 6, the polling code is fed from register 5 to the first the inputs of elements And 13. The mask code, set in register 7, is fed to the second inputs of elements And 13. Then a strobe pulse is applied to the third input of element 13, corresponding to the first bit of the interrogation code, from the output of register 8. Single,

temporarily from the output of the first bit of register 16 to the first inputs of the corresponding triggers 12, the resolving potential is applied. If, for example, a mask is applied to the first digit of the poll code, i.e. the value of the first bit of the mask code is equal to the TO by coincidence of the signals from the output of the corresponding element And 13 and the register 16 is entered into the trigger 12 corresponding to the first bit.

The signal from the output of the element And 13 also enters through the element OR 1 at the input of the register 16, after which the output potential, for example, of the second bit of the register 16, is established. A gate pulse is applied to the output of the second bit of register 8, which is fed to the third input of the And 13 element corresponding to the second bit of the interrogation code. If the value of the second digit of the mask code is equal, then the mask is inserted into the corresponding trigger 12, the signal at the input of register 16 is passed through the OR 10 element, and the enabling potential is set at the output, for example, of the third register bit 16

If the value of the second bit

ABOUT

then mask mask is equal to

mask does not occur, and at the output of the second bit of register 16, the resolving potential is saved. Then a gate pulse is applied to the output of the third bit of register 8. The resolving potential at the output of the second bit of register 16 is held until the value of one of the following code bits

The masks will not be equal to H — in this case, the mask is written to the corresponding trigger 12 by matching the signal from the output of the corresponding element I 13 and from the output of the second bit of register 16. At the output of trigger 12, a potential is established to allow the signal to pass from the second discharge counter 12 to the second input of the corresponding element or 14. Then the enabling potential is set at the output of the third bit of register 16, and so on, until a strobe pulse is fed to the output of the last (senior) bit of register 8.

Thus, the polling code is entered into block 6 in the following sequence: gating pulses are output alternately from register 8 outputs to third And 13 elements and the sequential supply of resolution potential from register 16 outputs to the second inputs of the corresponding triggers 12 after each successive

Claims (2)

entering the mask code into the corresponding bit. As a result, in each masked bit, in position 1, only that of the flip-flops 12 will be connected to the corresponding output of the counter 11. This ensures that all 3 combinations of the polling code are searched (where m is the number of masked bits) interrogation of matrix 1. After entering the interrogation code taking into account the mask in block b, interrogation of the matrix 1 by a sequence of codes corresponding to a search interrogation code is performed with regard to the mask. Consider polling matrix 1 using the example of a four-digit polling code. Suppose the polling code has the following form: OMM where M is a masked bit. So, as the mask is superimposed on the second and third bits, then in block b, those triggers 12 are associated with the first and second bits, respectively. the counter 11, and thus the second and third bits of the address code, coming in to the corresponding decoder 2 or 3, are associated respectively with the first and second bits of the counter 11; This ensures that the following code sequence is polled by the matrix 1 polls equal to che wipe as the mask is applied two times. After each survey, analyzes the value of the characteristic bit. If it is equal to H, then the word whose key (the higher bits match the polling code is in matrix 1, the information from the lower bits is calculated from matrix 1 and is fed through the second inputs to register 4, and the information from the higher ps The code is written to the high bits of register 4, respectively, with polling matrix 1, regardless of the value of the attribute bit. After the interrogation of the interrogation code combinations, the counter is reset, and the device is ready to receive the next interrogation code. Technical and economic advantage of the proposed device in its broader functionality compared with the prototype, since it provides an associative search mode when masking the interrogation code, Claim 1, Associative random-access memory containing a storage matrix, address register, decoders, outputs which are connected to the address inputs of the storage matrix, and the inputs to one of the inputs of the number register, the other inputs and outputs of which are connected to the outputs and information inputs of the storage matrix, different so that, in order to expand the functionality of the device by implementing the information search mode when masking the polling code, a polling code modification block is entered in it, the inputs of which are connected to the outputs of the address register, and the outputs are connected to the inputs of the first and second decoders 2. The device according to claim 1, characterized in that the polling code modification block contains AND groups of elements, OR element, OR groups of elements, shift registers, triggers, counter and mask register, with the first inputs of elements AND The main groups are the inputs of the block and are connected to the first inputs of the elements of the second group, the second inputs of which are connected to the outputs of the mask register, and the third inputs to the outputs of the first shift register, the outputs of the elements of the second group are connected to the first inputs of the trigger and inputs. of the OR element, the output of which is connected to the input of the second shift register, the outputs of which are connected to the second inputs of flip-flops, whose outputs are connected to the first inputs of elements AND of the third group, the second inputs of which are connected to the outputs of the counter, and the outputs of the elements OR the groups whose second inputs are connected to the outputs of the elements AND of the first group, the outputs of the elements OR of the group are the outputs of the block, the second inputs of the elements AND of the first group are combined and are the input of the gating of the block. e into account in the examination 1.Krayzmer LP High-speed ferromagnetic storage devices, M, -L ,, Energie, 1964, p. 324-326. , 2. I shade in B, P. and Yar. The ordered extraction of a multi-valued response from the associative ZU.-Cybernetics, 1965, 5, s, 32-34 (prototype).