SU1363512A2 - Channel selection device - Google Patents

Abstract

The invention relates to telecommunications and is an improvement of the invention in an. No. 1298940. The purpose of the invention is to reduce the channel selection time. The device contains input channels 1 consisting of keys 24, comparators 14 and triggers 10, block 2 of parallel registers, output channels 3, consisting of elements AND 19 and triggers 11, elements OR 4-7. triggers 8, 9, sawtooth voltage generator 12, comparator 13, elements 15-18, counters (MF) 20, 21, 22 and sequential write register 23. To reduce the time-channel selection, the element OR 7 and the counter 22. MF 22 dry; there are m single signals from the output of the element OR 5. When the rth signal is received, the signal 1 from the output of the MF 22 passes through the element OR 7. If the signal 1 does not appear at the output of the MF 22, then when the comparator 13 is triggered, 1 OR 7 passes through the element 1 from its output. In this case, a single signal from the element of the NII 7 transfers block 2 and register 23 from the parallel recording mode to the sequential read mode, 1 slug. c (O (L 1gZh1 OO O5 00 ayu My My-SCHR MS)

Description

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The invention relates to radio and can be used in receiving equipment of communication systems.

The purpose of the invention is to reduce the time of channel selection.

The drawing shows a structural electrical circuit of the device.

The channel selection device contains input channels 1, block 2 of parallel registers, output channels 3, elements OR 4-7, triggers 8-11, generator 12 sawtooth voltage, comparators 13 and 14, elements 15-19, counters 20-22 , the sequential write register 23 and the keys 24,

The device works as follows.

The keys 24 connect the device inputs to the first inputs of the comparators 14 for the time of channel analysis. The second inputs of the comparator 14 from the generator 12 are supplied for the selection time linearly, the varying voltage. Triggers 10 serve for short-term memorization of channels with extreme average voltages. Block 2 of the parallel recording registers is designed to memorize the numbers of channels with extreme voltages each time the comparators 14 trigger, Trig-. Ger 8 starts generator 12 and opens keys 24 for the duration of the selection. The second element OR 5 forms the reset pulse of the flip-flops 10 and the rewrite pulse of the block 2 parallel-write registers. The comparator 13 is triggered when the input voltage of the generator 12 drops to a certain level. The second counter 21 performs the counting of m single signals, the Counter 20 performs the transfer: the counting of clock pulses modulo n, the register 23 records the n-bit combination from the output of the last register of the block 2 through the element 16, the trigger 9 serves for fixing the moment of reading m single signals from the output of the last register of block 2, through the elements AND 19 single signals from the outputs of the register 23 of sequential recording go to the inputs of the installation 1 of the flip-flops 11, Element And 17 provides the passage of clock pulses from the clock input of the device to the inputs of the counters 20 and 21, block 2, register 23 after the trigger 8 is triggered and the comparator 13, the counter 22 performs the count m unit

R

0 0 B 0 5 0

five

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signals from the output of the second element OR 5,

When a short start pulse arrives at the control input of the device, the registers 23, block 2, trigenera 10, 11, and 9, the counters 20-22 are set to the zero state, the start pulse from the output of the first trigger 8 starts the generator 12, goes to the control the inputs of the keys 24, opens them and enters the first input of the first element And 17,

The voltage from the information inputs of the device through the public keys 24 is applied to the first inputs of the comparators 14. The second inputs of the comparators 14 are supplied with linearly varying voltage from the output of the generator 12. At the time when the voltages are equal at the inputs of the comparator 14, one or more input channels 1 are formed a short pulse that sets the trigger 10 to one state, while the pulses from the outputs of the flip-flops 10 through the second element Sh1I 5 and the third element HJM 6 arrive at the clock inputs of the block 2 and register 23, which are set s in parallelyuy signal recording mode On the fourth output of OR 7,

When one or several triggers are triggered, the signal 1 is recorded at the corresponding bit of the block 2 parallel recording registers and through the OR 4 and 5 elements the triggers 10 are set to the zero state. Single signals from the output of the element OR 5 are counted by counter 22, the voltage at the output of generator 12 continues to decrease — comparators 14 and 10 other channel triggers are triggered and signal 1 is recorded in the first register of block 2, from which information recorded from previous trigger operations 10 is rewritten into the second register of block 2. During the subsequent triggers of the triggers 10, the information is successively moved to the register of block 2. At the moment when the counter 22 receives m single signals, the signal 1 from the output tchika 22 appears at the output of the fourth element IL1-1 7. If the signal 1 at the output of the counter 22 is not at VILS, when the generator output voltage 12 becomes equal to a predetermined level

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(in the particular case equal to zero), the comparator 13 triggers and, from its output, signal 1 passes to the output of the fourth element OR 7. From the output of the element OR 7, a single signal arrives at the control inputs of block 2 and register 23 and transfers them from parallel recording information in the sequential reading of information.

Under the action of clock pulses from the clock input of the device coming through the element AND 17 and the element OR 6 to the clock inputs of block 2 and register 23, information from the output of the last bit of the register of block 2 through elements 18 and 16 goes to the counting input of the second counter 21 and register input 23, respectively, where the information is written sequentially. The counter 20 performs the counting of clock pulses. Every n clock cycles, a single signal from the output of counter 20 is supplied to the second inputs of elements AND 19 and single signals from the outputs of register 23 through elements AND 19 arrive at the inputs of installation 1 of the corresponding triggers 11, with the result that at the outputs of the device single signals appear .

When a single signal arrives at the second counter 21 t-h6, trigger 9 is set to one. Editor T. Lazorenko Order 6384/56

Tehred I.Popovich Proofreader M.D.

Circulation 636 Subscription VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Rauschska nab. d., 4/5

Production and printing company, Uzhgorod, st. Project, 4

2

and the signal from its output at the time of the output of the counter 21 of a single signal through the element OR | 15 sets the first trigger 8 to the zero state and the clock pulses from the clock input through the element 17 does not pass. The single sigal (from the output of the register 23) corresponding to the th channel with extreme mean voltage through the element 19 and sets the corresponding trigger 11 in a single state. This completes the process of selecting m channels with extreme average voltages.

Claims (1)

Invention Formula Device channel selection by bus. St. No. 1298940, characterized by the fact that, in order to reduce the channel selection time, a fourth OR element and a third counter are introduced, the counting input of which is connected to the output of the second OR element, and the control input is combined with the first input of the first OR element, and the comparator output is connected to the combined first input of the first element AND and the control input of the block of parallel recording registers through the fourth element OR, while the second input of the fourth element OR is connected to the output of the third counter. Compiled by A. Alexandrov Tehred I.Popovich Proofreader M.Demchik