SU1343417A1 - Device for checking digital units - Google Patents

Abstract

The invention relates to digital computing and can be used to monitor the operability of digital blocks and localize faulty nodes in them. The aim of the invention is to increase the reliability of control by providing control of the levels of the input signals. The device contains 1 test generator, 2 input-output groups, multiplexers 3, 4, 5, an analog control mode generator 6, an indication block 7, an analog multiplexer 8 monitored signals, memory blocks 9, 10, a signature analyzer 11, a control block 12 , two-threshold voltage comparator 13, upper threshold reference voltage generator 14, memory block 15, lower threshold reference voltage generator 16, signature comparison block 17, adders 18, 19 modulo two, IK-trigger 20, D- trigger 21,. delay element 22, element nt I 23. In the proposed device, when monitoring time sequences of digital signals using a signature analysis method, the level of digital signals is monitored simultaneously by F (L

Description

the upper and lower thresholds characteristic for this or another elemental base of the monitored digital blocks. In the event that the established level of at least one bit does not correspond, the generated signature will differ from the reference device. The device allows you to control the temporal sequences of the digital signals 1

The invention relates to digital computing and can be used to monitor the operability of digital blocks and localize faulty nodes in them.

The purpose of the invention is to increase the control quality by controlling the levels of the input signals.

Figure 1 shows the structural diagram of the device; Figures 2-4 are block diagrams of a control block, a comparison signature block and a two-threshold voltage comparator, respectively;

The device (Fig.) Contains test generator 1, stimulation output 2a, synchronous input 26, group of informational inputs 2c, input stop, start and synchronization groups 2r, 2d and 2e, respectively, multiplexers 3-5 stop, start and synchronization signals, respectively , shaper 6 diggs of argalogue control mode display unit 7, analog multiplexer 8 monitored signals, first and second blocks 9 and 10 of memory, signature analyzer 11, control unit 12, two-threshold voltage comparator 13, shaper 14 reference voltage of the upper poro and a third unit 15 memory driver 16 reference voltage and a lower threshold, the comparison unit 7 of signatures.

MP

adders 18 and 19 modulo two, 1K flip-flop 20, B flip-flop 21, delay element 22, And 23 element,

The shaper 6 signals of the mode, the analog control unit consists of the generator 24 and the trigger 25.

There is simultaneous control of their single and zero levels of any standard type, in addition, it is possible to control over a wide range the value of constant or time-quantized analog voltages of any polarity, which significantly increases the accuracy of the control of digital blocks. 4 ill., 1 tab.

The signature analyzer 11 consists of from the imaging unit 26 of the measurement interval and the shift register 27 with feedback (RSOC).

Positions 28-30 denote the information inputs of the multiplexers of the Stop, Start and Sync signals, respectively.

Further, the positions denote 31 0, the direct output of the generator 24; 32 —inverse output of generator 24, controlled by the first output of driver 6; 33-35 - groups of address inputs of the multiplexers of the signals Stop, Start

5 and synchronization, respectively; 3638- inputs Stop, Start and synchronization of the signature analyzer 11;

39- information input of the register 27; 40-43 g- address inputs, respectively

0 of the display unit 7, the MultiGex 8, the memory blocks 9 and 10; 44 - register reset input 27; 45 — group of control information outputs of control unit 12; 46-48 - the first, second and third inputs of the comparator 13; 49 — group of address inputs of the third memory block 15; 50 - gating output of the signature analyzer 11; 51-installation input signature analysis of torus II; 52 - synchronous register 27; 53 and 54 - the first and second groups of information inputs of block 17; 55 and 56 — the first and second — groups of information outputs of the third block, 15 pa35 mti; 57 and 58, respectively, control and installation inputs, control unit 12; 59, 60 and 61, 62 - the first and second inputs of adders 18 and 19 modulo two, respectively; 63 - Equalization progress of block 17 compare sig5

313

natures; 64 - information output device; 65 - input the initial installation of the device.

The control unit 12 (FIG. 2) contains a code comparison unit 66, a counter 67, switches 68 and 69, a delay element 70 and an OR element 71. The position 72 designates the output of the block 66, the position

73- reset input of counter 67. Signature comparison unit 17 (FIG. 3)

contains a storage device (memory)

74 standard signatures and comparator

75 codes

The two-threshold voltage comparator 13 (FIG. 4) comprises an upper threshold comparator 76 and a lower threshold comparator 77.

The device works as follows.

The test generator I generates stimulating signals that, through the stimulation outputs 2a of the device, enter the monitored digital block. In order to ensure the synchronization of the stimulating signals with the monitored and control signals generated by the monitored digital unit, the reference sync signal arrives from the latter through the device's synchronous input 26. In this case, the information inputs 2c of the device and further to the inputs n of the multiplexer 8 are supplied produced by controlled digital blocks.

monitored signals, which are specific time sequences of digital signals, constant or time-quantized analog voltages. Through the inputs 2g, 2d, 2e of the device from the monitored digital block, the inputs 28-30 of multiplexers 3-5 receive sets of control signals. The performance monitoring or diagnostics of a digital unit is performed by alternately automatically checking the temporal sequences of digital signals arriving at it with simultaneous control of their unit and zero levels and constant or analog voltages.

In block 12 control switch 69 sets the number of the monitored signal, from which must

The test of the digital unit begins, and the switch 68, the number of the last monitored signal being monitored.

When a pulse is applied to the input 65 of the initial setup of the device, the triggers 20 and 21 are reset, the measurement interval driver 26 and the RSOC 27 of the signature analyzer 11 are reset to the initial state of waiting for the trigger signal. The falling edge of the initial setup pulse at the input 58 of the control unit 12 into the counter 67 records the initial code received from the first switch 69 (the initial number of the monitored signal). The indicated code from the output of the counter 67 is supplied to a group 45 of the control information outputs of the control unit 12 and further to the inputs 40-43, 49 and 54, respectively, of the display unit 7, multiplexer B of monitored signals, the first 9, the second 10 and the third 15 memory blocks and block 17 comparing signatures. At the input 72 of the block 66, the code comparison is absent. For accurate operation of the device, the duration of the initial setup signal must be greater than the delay value of the block element 70

12 controls

At the same time, a channel is opened in the multiplexer 8, corresponding to the set number of the monitored signal, according to which the monitored signal Ujf selected for testing is fed to the input 47 of the two-threshold comparator

13captions. From outputs 55 and 56 of the third memory block 15, the shaper 14 and 16 receive the reference voltage value codes for the upper and lower thresholds, respectively. The selected reference voltages of the upper threshold Ug and the lower threshold U are respectively fed to the inputs 46 and 48 of the two-threshold comparator 13, which compares the monitored signal U x to the reference voltages U p and. The table shows the state of the inverse 59 and direct 61 outputs of the comparator 13 for different polarities and ratios of values

and uj ,, and „,.

lu

np

 lUvl r lU

Overhead line

U, I I and „p

 lUgJ

From the output of the second memory block 10 to the polarity control inputs of the formers 14 and 16, as well as to the inputs 60 and 62 of the adders 8 and 19, a signal O is output if the monitored signal is positive, or signal 1 in the case of a negative polarity of the monitored signal. The address inputs 33–35 of multiplexers 3–5 receive the code for selecting a set of control signals recorded in the cell of the first memory block corresponding to the given number of the monitored signal.

At the inputs 36-38 of the signature analyzer 11, the corresponding control signals Stop, Start and Synchronization are received, which are related to this monitored signal. When a signal arrives at the input 37 of the signature analyzer I, it passes to the imaging unit 26, which enters the measuring state and expresses the impulse set at input 44 of the initial setup of the register 27. At the same time, the influence of the control signals is blocked in the imaging unit 26 A start received at input 37 is allowed to receive Stop signals at input 36, and a measuring (time) strobe is generated} allowing the passage of control synchronization signals from input 38 of the signature analyzer 11 to the sync input C of the RSOC 27 and through the sync output 52 to the C input of the 1K flip-flop 20,

At the same time, if the level K of all zero bits of the controlled sequence arriving at the input 47 of the two-way comparator 13 is less

one

0

one

0

one

0

20

the reference voltage U of the lower threshold coming from the imager 16 to the input 48 of the comparator 13, and the level

Uv

all single bits controlled5

0

five

0

five

0

five

my sequence is greater than the reference voltage Ugj, the upper threshold coming from shaper 14 to input 46 of comparator 13, then regardless of the polarity of the digital signals representing the controlled-sequence, at the output of the 1K flip-flop 20 there will be a sequence and in terms of ones and zeros, it is expressed in TTL levels (IC series 155, 133, 533).

The elimination of the influence of the polarity of the monitored signals is achieved by the adders 18 and 19 modulo two, the first inputs of which are connected to the corresponding outputs 59 and 6 of the two-threshold voltage compressor 13. When the polarity of the monitored signals from the second memory block 10 is positive, the second inputs 60 and 62 of the adders 18 and 19 are applied O and the signals at the outputs of the specified adders repeat the signals at their first inputs. If, on the second inputs of these adders, 1 is applied, which takes place in the control of sequences represented by negative signals, then the outputs of the adders will be signals inverted with respect to the signals on the first inputs of these adders.

The synchronization signals in the PCOC 27 record the data stream coming from the output of the 1K flip-flop 20 to the information input 39 of the signature analyzer 1 Coming from the output

7-13 of the multiplexer 3 to the input 36 of the signature analyzer. 11 the Stop signal shifts the driver 26 to the waiting state of a new trigger signal Start. In this case, the formation of the measuring strobe stops, in connection with which the passage of synchronization pulses to the corresponding RSOC 27 and the C-input of the 1K-trigger is prohibited. ra 20.

After the end of the measurement interval, the RSOC 27 status code, i.e. signature (K-bit binary number), through a group of 53 outputs of signature: analyzer 11 goes to the group of inputs of signature comparison block 17 and then to the second group of information inputs of the code comparator 75, the first group of information inputs of which receives the reference signature written in corresponding to the monitored monitored signal cell of the memory 74 of the reference signatures of the signature comparison block 17.

If the generated signature corresponds to the reference one, which takes place when the monitored sequence of digital signals meets the specified requirements for the levels of the single and zero bits and their temporal spread, then the output 1 of the signature comparison block 17 reads the signal 1, otherwise O. This signal is sent to the D-input of the

Hera 21, the recording of information in which is carried out by the falling edge of the measuring gate coming from the signature analyzer 11 through the output; 50 to the C input of the trigger 21.

If the signature of the first monitored signal is correct, i.e. corresponds to the reference one, then the D-flip-flop 21 switches to state 1 and an input potential of the element 23 and the information output 64 of the device enters the breaking potential. At the same time, with the falling edge of the measuring strobe through the delay element 22 and the AND element 23, the content of the counter 67 of the control unit 12 is increased by one, which corresponds to the following code being set on the outputs 45 of the control unit 12 of the control signal.

In this case, in the multiplexer 8, the channel for the passage of the previous monitored signal is closed and the channel for the passage of the next control is opened.

roll signal. On address inputs 33-35. Multiplexers 3-5 pos-. the selection code of the control signal set fades; the selection voltage of the upper and lower thresholds, respectively, from the output of the second 5 memory block 10 to the shapers 14 and 16 and the inputs from the outputs 55 and 56 of the third memory block 15 to the drivers 14 and 16; 60 and 62 adders 18 and 19 are fed 1 or O from the memory 74 of the reference signatures of the signature comparison block 17, the signature corresponding to the number of the next monitored signal is read. The measurement cycle repeats and, if the signature of the second Monitored signal is correct, the device proceeds in the same way to test the third signal, etc. If the signatures of all signals are correct, then the counter 67 from the initial state passes through all the states successively to the last. After checking the last monitored signal, if its signature is correct, counter 67 switches to the state when its outputs set a code equal to the code dialed on the second switch 68. At the same time, the output 72 of the code comparison unit 66 produces a signal that delays and the OR element 71 is fed to the input 73 of the initial installation of the counter 67, and the monitoring cycle is repeated from the beginning.

If the monitored signal arriving at the input 47 of a two-threshold comparator 13 is a constant or time-quantized analog voltage of positive polarity, then it is compared with the positive reference voltages of the upper Ugp and the lower and thresholds supplied to the comparator 13 at inputs 46 and 48 respectively. With / and ,, .. / / Uv / / and ..., /, i.e. when

 np

the monitored signal is normal, signals 1 and 1 are set at outputs 59 and 61 of comparator 13. Since simultaneously from the second memory block 10, O arrives at inputs 60 and 62 of adders 18 and 19, signals 1 appear at the outputs of these adders on K-input and 1-input trigger 20.

For AND negative polarities, Uj ,, and UHJ, also negative polarity, are formed, in this case with

/ and / / U, I / Ugn / at outputs 59 and 61 of the comparator 13, signals O are set, but due to the fact that at the same time, inputs 60 and 62 of adders 18 and 19 from the second memory block 10 are output 1, at the outputs of adders 18 and 19 modulo two, and the K- and 1-inputs of the trigger 20, the signals 1 are set again.

When monitoring constant or time-quantized analog stresses, the output signal of shaper 6 is used as the Start, Stop, and synchronization signals controlling the operation of the signature analyzer 1I, which are fed to one of the pre-selected inputs of the corresponding multiplexers 4-5. In this case, the control synchronization signals are removed from the inverted output 32 of the generator 24, and the Start and Stop signals from the output of the counting trigger

on the information input 39 of the signature analyzer 11, the signature of the last signature 00 formed. .01 1 dl / ux / / and bl /

 or 00 ... 000 dl / and X / / and np / will be different from the reference. Thus, when testing any constant or analogue Q, neither the resulting signature can be of three types; 00 ... 010 dl / UHH / / and, / / and ate /, 00 ... 011 dl / and // / and 00 ... 000.dl and u / / and /, the analysis of which allows 15 receive additional information about the state of the controlled voltage.

If in the process of checking the signature of the monitored signal turns out to be 2Q with an incorrect one (different from the reference one), then at the output 63 of the signature comparison block 17, the signal O is set, which is written to the D-flip-flop 21, and to the input element AND

25 shaper 6 .. As a result, at 25 23 and the information output 64 of the test of any monitored signal enters a inhibitory potential. The passage of counting pulses through the element 23 on the counter 67 of the chenal, represented as a constant or analog voltage of any polarity, is not allowed by the driver 26 of the signature analyzer 11 to operate and the output of the control unit 12 is the same code control input 57 of block 12

a strobe allowing the passage of only two synchronization pulses on the RSBP 27 and the C input of the 1K-flip-flop 20. Because with / and „p /; / and X / / and 8l / at inputs K and I of trigger 20 cost 1, then its state will change each time when a synchronization pulse arrives at the C input. Thus, during the measurement interval at the input 39 of the signature analogue-t, the mash 1 will have a defined binary sequence, as a result of which the output 53 of the signature analyzer will generate a signature- 45 digital and digital-analogue blocks pa 00 ... 010, one and the same / u of all allows for

along with automatic control of time sequences of digital signals by the method of signature analysis gQ of the simultaneous control of their

single and zero levels of any standard extremes (TTL, CMOS, ECL), as well as providing them with the ability to control over wide limits, the signals at the outputs 59 and 61 of the comparative-gg are quantized or time-pa 13 and respectively K and I- the analog voltages of any field terminal inputs of the trigger 20 will be inversely, significantly increasing the authenticity or analogue U, which are within the established thresholds. This signature should be recorded as a reference in the corresponding cells of the memory 74 of the signature comparison block 17.

If Ux does not comply with the norm, i. / Ux / / Ug, / or / and, / / inp /,

ze (o

1 or 1

ABOUT). In the control of digital and digital-ana. logs of blocks.

The result is a binary follower type 43417

to

about

on the information input 39 of the signature analyzer 11, the signature of the last signature 00 formed. .01 1 dl / ux / / and bl /

 or 00 ... 000 dl / and X / / and np / will be different from the reference. Thus, when testing any constant or analogue Q, neither the resulting signature can be of three types; 00 ... 010 dl / UHH / / and, / / and ate /, 00 ... 011 dl / and // / and 00 ... 000.dl and u / / and /, the analysis of which allows 15 receive additional information about the state of the controlled voltage.

If in the process of checking the signature of the monitored signal turns out to be 2Q with an incorrect one (different from the reference one), then at the output 63 of the signature comparison block 17, the signal O is set, which is written to the D flip-flop 21, and the input element

control is prohibited and the output of the control unit 12 remains the code

cutting control input 57 of block 12

a measure of a signal that is classified as faulty. Block 7 displays the number of this monitored signal or directly the number of the corresponding failed part of the monitored block. Thus, in the event of the inoperability of the controlled digital unit, operational information is provided on the location of the damage, up to the numbers of the failed parts (nodes) or microcircuits in order to replace them.

The use of the proposed device for monitoring and diagnosing

control of digital and digital-ana. logs of blocks.

 13434

Claims (1)

Invention Formula A device for controlling digital blocks, comprising a test generator, an analog multiplexer of monitored signals, a signature analyzer, a control unit, an indication unit, a signature comparison unit, an And element, a delay element, a D-trigger, a first memory block and three control multiplexers the output and the synchronous input of the test generator are connected respectively to the information output and the synchronous input of the device 15, the group of information inputs of the analog multiplexer of monitored signals form a group of information Ion inputs of the device, inputs of Start, Stop, and synchronization of the signal analyzer 20 are connected to the outputs of the corresponding multiplexers of control signals, the information INPUT1) of which form a group of information inputs of the device, the building output of the signature analyzer of the analyzer is connected to the D-trigger synchronous input —pa and with the input of the delay element, the output of which is connected to the first input of the element I, the output of which is connected to the synchronous input of the control unit, the output of the D-flip-flop is the output of a sign of a device error and connected to the second input of the element I, the information input of the D-flip-flop is connected to the equality output of the signature comparison unit, the first group of information inputs of which is connected to the information output group of the signature analyzer, the group of outputs of the control unit 40 is connected to the address group of the analog multiplexer of monitored signals , a group of inputs of the display unit, a second group of information inputs of the block of comparison of signatures and a group of address inputs of the first memory block, the first, second and third g groups of information outputs of which are connected to groups of address inputs of corresponding multiplexing type controllers, the input of the initial installation of the device is connected to the installation inputs of the signature analyzer, control unit 1712 laziness and the input of the installation to the D-Trigger, excepting it is that, in order to make the control more reliable by ensuring control of the input signal levels, the device contains the upper and lower threshold voltage drivers, the two-threshold voltage comparator, the first and the second adders modulo two, 1K-flip-flop, driver of analog control mode signals, second and third memory blocks, groups of address inputs of which are connected to the output group of the control unit, the first and second groups of information outputs The second storage unit is connected to groups of information inputs of onopiuix voltage drivers, the outputs of which are connected to the first and second information inputs of the two-threshold voltage para- meter, respectively, the third information input of which is connected to the output of the analog multiplexer of monitored signals, inverse and direct the outputs of the two-threshold voltage comparator are connected to the first inputs of the first and second modulators two respectively, the outputs of the first and second modulators two two Connected respectively to the K- and 1-inputs of the 1K-flip-flop, the second inputs of modulo-two adders are connected to the information output of the second memory block and the polarity control inputs of the reference voltage drivers, the 1K-flip-flop sync is connected to the signature analyzer synchronous input, the information input which is connected to the output of the 1K-flip-flop, the first and second inputs of the installation in Oh which are connected respectively to the input of the initial installation of the device and the output of the delay element, the second information input of the third multiplex A cue of control signals is connected to the first output of the signal generator of the analog control mode, the second output of which is connected to the second information inputs of the first and second control multiplexers. Editor E. Papp Compiled by S. Starchikhin Tehred M. Didyk- Proofreader S. Cherni Order 4825/50 Edition 672 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 4/5, Raushsk nab., Moscow, 113035 Production and printing company, Uzhgorod, st. Project, 4 Phi2l