SU1180819A2 - Multichannel device for functional checking of integrated circuits - Google Patents

Abstract

1. MULTI-CHANNEL DEVICE FOR FUNCTIONAL CONTROL OF INTEGRATED SCHEMES according to author. St. No. 857890, characterized in that, in order to increase reliability and speed, the first and second code converters are introduced into the time interval, the control register, the input group of which is connected to the corresponding inputs of the device, and the group of outputs - to the group of the corresponding inputs of the first code converter in the time interval, the clock input of which is connected to the output of the control element I, and the output - to the clock input of the second code converter in the time interval, the group of inputs of which is connected to The corresponding group of outputs of the group of elements is OR, and the output is with the clock input of the distributor. 2. Device POP.1, characterized in that the code converter in the time interval contains the element AND, the shift register and the decoder, the group of inputs of which is connected to the corresponding i inputs of the code converter in the time interval, the group of outputs - with (L group of the corresponding inputs of the shift register whose clock input is connected to the clock input of the converter and the first input of the element I, and the output to the second input of the element I, the output of which is connected to the input of the operating mode of the 00 shift register and the input of the converter ers. 00 with

Description

The invention relates to computing technology, is intended for use in instrumentation technology, and is an improvement to the device according to the basic author. St. No. 857890.

The purpose of the invention is to increase the reliability and speed of control by reducing the time interval for changing each test set to the minimum required by encoding the duration of each time interval for changing the test set for the purpose of the groups of bits of each test set specifically for this purpose.

At the same time, changing the frequency of changing test sets is done by hardware using a code converter during the time interval of pulses directly in the control dynamics, as well as by forming a time control chart corresponding to the working one, as well as by determining the frequency of the stable operation of the control object, since the interval (duration) of the impact of the input signals on the object of control and controlled operations, equal to the worker, allows the control If the controlled object performs each operation taking into account the effect of transients occurring in the control object during the execution of each previous operation on the correctness of each operation following it, the control with the duration of the input signals and the duration of the controlled operations that differ from the workers allows does not determine the stability of the object of control, since under actual conditions, under the influence of external factors, the frequency of functioning of the object of control may differ from the frequency at which the control is made of the calculated working t

FIG. 1 is a prescheduled multi-channel control unit for functional control of integrated circuits; in fig. 2 is a functional diagram of a code converter in a pulse time interval.

A multichannel device for functional control of integrated circuits contains a trigger 1, a single input of which is connected to the trigger input of the device, and a zero output to the output of an OR 2 control element, an AND 3 control element whose first input is connected to a single trigger trigger 1 output, the second the input with the output of the clock generator 4, and the output with the clock input of the first converter 5 of the code in the time interval of the pulse, the output of which is connected to the clock input of the converter 6 of the code in th pulse pulse interval, control register 7 for controlling the converter 5 of the code in the time interval, group of elements OR 8, distributor 9 for synchronizing and controlling the device blocks, input register 10 for receiving monitored signals from the controller of N channels, each of which contains block 11 comparison , for comparison of monitored object control signals with control signals, memory block 12 for storing and storing test sets, output register 13, first element 14, trigger 15 for storing the result Comparison of block 11, the second element And 16 and the third element And 17, each converter 5 and 6 containing-. There is a decoder 18, the inputs of which are connected to the inputs of the converter 5 or bis informational inputs of the shift register 19, and the element 20. The shift register 19 can be made similarly.

The operation of the device is as follows.

The block 12 of the i-th channel memory contains sets of control and control signals of the test (test set) with numbers i, N + i, 2N + i, etc., where, and in the control register 7, the code of the pulse following period is written At the output of the converter 5, the code is the time interval. Pre-block 12 of memory of each channel selected the first sets of control and control signals. Further, in all channels, except for N-ro, the selected sets of control and control signals are recorded in the corresponding output registers 13 and registers of comparison units 11. After that, in all the 12 memory blocks, except

(N-1) -ro and N-th channels, selects the second set of control and pilot signals. Then, from the output register 13 of the first channel, the first set of control signals is fed to the control object and the converter 6 of the code in the time interval through the elements of OR 8.

The signal from the trigger input of the device triggers the trigger 1 into a single state, as a result of which the lock is removed from the control element AND 3. Pulses from the output of the generator 4 are fed to the input of the first converter 5 of the code in the time interval and the shift register 19 starts the shift of the unit level in the direction from the lower bits of the shift register to the higher one, triggered by the trailing edge of the generator 4 clock pulses. When the high bit is reached by a single level. and with the arrival of the next clock pulse pulse generator 4 as a result of element I 2 triggering a pulse from the output of the latter connected to the output of converter 5 of the code in the time interval is fed to the input of the next converter 6 of the code into the time interval and the input of the operating mode of the shift register 19. At the trailing edge of the clock pulse, recording information arriving at the inputs of the shift register 19c of the outputs of the decoder 18, as a result of which it is established in the unit state corresponding to the code at the input of the decoder 18, one of the races limiter 9. In this way, the code to time converter is prepared for the next cycle.

The converter 6 of the code in the time interval with the arrival at its input of clock pulses from the output of the converter 5 of the code in the time interval works in a similar way and at the output of the converters 5 and 6 of the code in the time interval are formed sequences of pulses with a time interval corresponding to the code in control register 7 and on the inputs of the first group of elements OR 8, while the pulse period at the output of the converter 5 of the code in the time interval is set equal to the weight value of the time code The test case change terminal, under which a group of bits is allocated in the test set, and at the output of the code converter 6 at a time interval equal to the test case change time and varies in control dynamics with the code change at the outputs of the first group of elements 8, corresponding to the corresponding the transducer inputs 6 code in the time interval. The pulses from the output of the converter 6 of the code in the time interval arrive at the clock input of the distributor 9 and the control input of the input register 10. At the same time, the input register 10 functions on the leading edge of a unitary logic level, set by the converter 6 of the code in the time interval, the distributor 9 - on the falling edge specified single logical level. As a result, in the first cycle of operation, the first set of output signals of the control object is recorded in the input register 10, which is compared in block 11 for comparing the first channel with the first set of control signals from the outputs of the corresponding memory block 12 and stored in the register of the specified block 11 . According to the first signal of the distributor 9, the result of comparison through the first channel element 14 is stored on the corresponding trigger 15, which is preliminarily set to the zero state. At the same time, the N-ro channel of the test set of control signals is written to the output register 13 and the next test set of controls is sampled. control signals in memory block 12 (N-1) -th channel, as well as feed from the output register 13 of the second channel through a group of elements OR 8 to the inputs of the converter 6 of the code in the time interval and control object of the second test set of control signals.

In the second cycle of operation after the end of a predetermined time interval, the second set of output signals from the control object is recorded in the input register 10, which is compared in the second channel comparison unit 11 with the second test set of control signals fed from the outputs of the corresponding memory block 12 and stored in the register of the specified block 11 comparison. According to the second signal of the distributor 9, the result of the comparison through the second channel element 1A is stored on the corresponding trigger 15 of this channel, previously set to the zero state. At the same time, the contents of the first channel trigger 15 are analyzed by unlocking the AND 16 and 17 elements of the same channel. If the first sets of input signals of the control object and the control signals in the unit 11 compare the first channel, i.e. When the control object is properly functioning, the trigger 15 of the first channel is in a single state, as a result of which, using a single logic level from the output of the corresponding output element AND 16, the next test set of control and control signals is written to the output register 13 and the register of block 11 compare this channel. At the same time, the second test set of control and control signals in the memory block of the N-ro channel is sampled along the second signal of the distributor 9, and the third channel is fed from the output register 13 through the group of elements OR 8 to the inputs of the code converter 6 in the time interval and the object control of the third set of control signals. .

If the control object is not functioning properly, the trigger 15 of the first channel is in the zero state, as a result of which, using a single logic level from the output of the corresponding element AND 17 through the control element OR 2, the trigger 1 is switched to the zero state. As a consequence, the trigger 4 is disconnected from the code converter 5 in the time interval.

The device operates in the mode of Toden - Marriage.

Further operation of the device is carried out similarly when a trigger is triggered to the trigger input 1 from the trigger input of the device, with each i-th signal of the distributor 9 setting the channel trigger 15 (i-2) -ro to the initial zero state.

When determining the frequency-time domain of stable operation of the control object, the control register 7 is recorded by means of the device to obtain a new code value at the output of the code converter 5 in the time interval of the required pulse time interval, the value of which is the weight for the code converter 6 in the time interval , the information inputs of which receive the code of the time interval for changing test sets from the group of the corresponding outputs of the group of elements OR 8, i.e. By changing the course in control register 7, you can quickly change the time interval for changing test sets and the time interval after which you monitor the output signals of the control object without changing the corresponding code in the test sets for which change requires an overload of memory blocks 12, which causes to increase the time control.

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Claims (2)

1. MULTI-CHANNEL DEVICE FOR FUNCTIONAL CONTROL OF INTEGRAL CIRCUITS by ed. St. No. 857890, characterized in that, in order to increase reliability and speed, the first and second code converters are introduced into it in a time interval, the control register, the group of inputs of which are connected to the corresponding inputs of the device, and the group of outputs - with the group of corresponding inputs of the first code converter in the time interval, the clock input of which is connected to the output of the control element And, and the output - with the clock input of the second code converter in the time interval, the group of inputs of which is connected to a group of outputs of the group of OR elements, and the output is with the clock input of the distributor. 2. The device according to claim 1, characterized in that the code converter in the time interval contains an element And, a shift register and a decoder, the group of inputs of which is connected _{to the} inputs of the code converter in the time interval ®, the group of outputs - with the group of corresponding inputs a shift register, the clock input of which is connected to the clock input of the converter and the first input of the And element, and the output to the second input of the And element, the output of which is connected to the input of the shift register operating mode and the input of the converter. SU „„ 1180819 118081