SU1591045A1

SU1591045A1 - Device for checking microassemblies

Info

Publication number: SU1591045A1
Application number: SU884610833A
Authority: SU
Inventors: Valerij M Vishnevskij; Yurij V Timofeev; Evgenij I Kudryashov; Lyudmila S Petrova
Original assignee: Valerij M Vishnevskij; Yurij V Timofeev; Kudryashov Evgenij; Lyudmila S Petrova
Priority date: 1988-11-25
Filing date: 1988-11-25
Publication date: 1990-09-07

Description

The invention relates to automation and can be used in instrumentation technology, The purpose of the invention is to increase the reliability of the control. The device contains switches, a block of comparators.

2

logic levels, an OR element, a mode control and synchronization unit, a pulse generator, a ring re- '. shift register, address register, triggers, AND element, NOT element, sawtooth voltage driver, key, expiration indicator, unit of standard logic signals, group address decoder, group indicator, pulse formers at the front, counter. The signals from the controlled microassembly through the switch come to the block of logic level comparators, where they are compared with the reference signals. In case of identification of the malfunction, the sequence of operation of the sawtooth voltage driver is broken, which is fixed on the indicator of fitness. 10 silt

(L

with

The invention relates to automation and can be used in instrumentation technology.

The aim of the invention is to increase the reliability of control by localizing the fault.

Figure 1 and 2 presents the scheme of the device; FIG. 3 is a diagram of a mode control and synchronization block; figure 4 - diagrams of the second and third switch and the block circuit reference dogic signals; Fig.5-10 timing charts of the device.

The device contains (Fig.1 and 2) the first switch 1, block 2 of the Compara ··· / tori logical levels, element

OR 3, mode control and synchronization unit 4, 5 pulse generator, shift ring register 6, address register 7, second switch 8, first trigger 9, element 10, NOT 11 element 11, second trigger 12, sawtooth driver 43, key 14, 15-year indicator, block 16 reference logic signals, third 17 switch, decoder 18 group addresses, indicator 19 groups,, driver 20 pulses on the front and counter 21.

The mode control unit and the synchronization contains the element NOT 22,

frequency divider 23 and driver

24 pulses.

3

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The second and third switch and th unit of the reference logic signals (FIG. 4) contain elements AND 25, elements NOT 26, elements OR 27, switches 28, reference voltage source 29 and trigger 30 (FIG. 3).

The device monitors the health of the microassembly of the decoder by the presence of signals at the outputs, divided into groups, and can work in automatic and manual control modes. ”The selection of the control mode is carried out by the third switch 17; when entering from the fifth output of the mode control block 4 and synchronization to its control input signal with the level "Log, 1" in manual or "Log" 0 "in automatic modes, In the automatic control mode, all output groups are monitored in continuous sequence, in manual mode each group of outputs is controlled separately

The binary code, supplied to the input of the microassembly of the decoder being tested, is generated by counter 21, while the number of low-order bits (n) determines the number of outputs of the micro-assembly in the controlled group, and the number of high-order digits (ha) .- the number of controlled groups * Selection of a certain group for control is carried out by the second switch 8, the inputs of which from the outputs of the decoder 18 addresses of the groups are served decrypted high-order bits "The presence of" Log "1" on any of the outputs of the decoder group addresses means control of a certain group nN "For example," Log ₀ 1 "output" Vyh.O "means control the first group" Log "1" at the output "O" 1 "- control of the second group and so on" switch these control signals is performed with the annular O register 6 shift.

The device on the example of the control of groups of eight outputs of Fig "5-10 works as follows.

The formation of the input code of the controlled microassembly takes place when the device is turned on, which is set to its initial state. For this, the signal from the second output of the mode control unit 4 and synchronization is written into the most significant digit of the shift ring register 6 "1" and into the other digits "0".

In the manual mode, from the fourth output of the mode control and synchronization unit 4, a signal is sent to the input of the ring register 6 of the shift through the third switch 17, which moves "1" from the most significant bit to. younger, while at the output of the former ** on the front of this "1", a short pulse appears, which resets the counter 21 o The presence of "1" in the digits of the ring shift register is indicated on the indicator of 19 groups. The zero state of the counter 21 fron15 'signal volume from the "Out. O" decoder 18 group addresses, which passes through the second switch 8 _? is written to the 7-address register "From the seventh output of the mode control block 4 and

2θ synchronization start pulse, coinciding in time with the pulse front of the generator 5 pulses, sets the first trigger 9 in one state, which allows you to pass

25 sequences of pulses from a generator of 5 pulses through elements AND 10 and HE 11 to the gate input of the microassembly being checked and to the synchronous input of the counter 21, respectively "B

50 is the time at the correct output "Out" 0 "of the monitored microassembly, an impulse equal in duration to the gating impulse should form. The changing state of the counter 21 is decrypted by the microassembly being checked.

35 when the strobe pulse arrives at it. When the number “8” is written to the counter 21, the signal “Log.O” is set at the output “Out.” Of the decoder 18 of the group addresses, and the signal “Log” is output at the output. .one". This signal "Log.1" from the output of "Out.1"

the decoder 18 group addresses passes through the second switch 8 and from its

dd of the first output is fed to the third input of the third switch 17 and to the first input of the first trigger 9, setting its front. in the zero state and closing the element And 10 for

50 pulses from the generator 5 "

From the second output of the third switch 17, this signal "Log” 1 "is fed" to the input of the resolution of parallel recording of counter 21, rewriting the contents of the register 7 address into the counter,

³³ i.e., “0”, with the output “Vykhoo”

decoder 13 group addresses and corresponding. at the second exit of the second

switch 8 signal appears

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6

“Log, 1”, and at the first output - the signal “Log.O.” When the next ¹ trigger pulse arrives from the mode control and synchronization block 4, the process of forming the input code is repeated.

The input code to control the group of outputs "Vyh.8". about lvyh The 15 "checked microassembly is formed when, during manual control, a new short pulse appears at the fourth output of the mode control and synchronization unit 4, which through the third switch 17 is fed to the input of the new register 6 shift register, moving the" 1 "from the first digit to the second At the same time, the “!” From the second digit of the 6th shift register is fed to the second control input of the second switch 8. When the count 21 starts counting eight pulses after the arrival of the start pulse, the output of the decoder 18 of the group addresses will be 8 The signal "Log.1", which via the second switch 8c of its second 25 output is fed to the synchronous input of the address 7 register and the front of this signal, the status ^< bits of the counter 21, i.e. the number "8" is written to the address register 7. the arrival of the 16th pulse at the synchronous input of the counter 21 at the output Vykh.2 of the decoder 18 group addresses generates a signal Log, G, which through the second switch 8 sets 35 from its first output

the first trigger 9 in "0" and the flow of pulses to the input of the counter 21 is stopped. The same signal is fed to the third input of the third switch 17 and from its second output is fed to the input 40 of the resolution of parallel recording of the counter 21, rewriting the contents of the register 7 address, i.e. the number "8" is in • the counter 21. At the second output of the second switch 8, a signal 45 is generated

"Log, 1", and on the first output - the signal "Log.0". With the arrival of the next start-up pulse, gating is received from the seventh output of the control unit 4 to the controlled microassembly · 50 gating

pulses and pulses on the synchronous input of the counter 21. The content of the counter 21 increases from the initial state ^ i.e. the recorded number "8", and with the arrival of the 16th pulse, 55 the contents of register 7 of the address are rewritten, i.e. the numbers "8" in the counter 21. Similarly, the input code is formed for the others / manual groups of the manual control mode.>'

In the automatic mode, the third switch 17 commits only the start pulse, which, via the seventh output of the mode control unit 4 and synchronization, passes through the third switch 17 and from its first output goes to the ring re-ι shift 6 of the shift. The signal at the second output of the third switch 17 is absent, therefore, the overwriting circuit of the counter 21 is open. The register 7 does not accept the address in the automatic participation control mode. Moving "1" in the ring register 6 shift is carried out every time with. the arrival of a launch pulse. In the initial state, "1" is recorded in g high bit, therefore, with the arrival of the first start pulse after switching on the automatic control mode "1", the most significant bit is moved to the low bit and the second switch 8 is controlled and the counter 21 is reset. groups of exits in the manual mode.

When writing to the counter 21 of the number "8", the first trigger 9 stops the flow of the generator 5 pulses through the elements AND 10 and NOT 11, and the counter 21 remains in this state. At the same time, there is no signal at the output of Vykh.8 of the monitored microassembly, since there is no gating pulse on it. When the next trigger pulse arrives at the input of the ring register 6, the shift “1” moves to the next bit, controlling the second switch 8, since the strobe pulse is sent to the micro loop assembly, a signal appears at the normal output “Out.8” Further, when counting clock pulses, signals are output at all outputs of this group of controlled microassembly.

With the arrival of the following start-up pulses, a code is formed in a similar way to control all the other groups of micro-assembly outputs.

When you move the "I" in the ring register 6 shift from the highest order to the youngest repeated continuous. sequence control groups of exits.

Outputs controlled microassembly ·

connected to the inputs of the first comm.

tator 1, representing a block

7

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eight

multi-channel switches, the number of outputs of which is determined by the number of controlled groups of outputs, that is, 2 ^. Each multichannel switch provides a serial connection of signals from the outputs of one group of monitored microassembly to one output. The connection of the ΐ-th signal in the group, θ to the output is controlled by the code supplied to η of the control inputs of the first switch 1, the binary code is fed simultaneously to the control inputs of all multi-channel, 5 switches. Connecting one or another group of supervised microassemblies to a specific output of the first switch 1 is carried out by applying signals from the decoder 18 group addresses to its permitting inputs.

Therefore, in the manual control mode ι, when one selected group of outputs of the microassembly is controlled, at the corresponding output of the first 25

switch 1, there is a bundle of 2 ^ъ pulses, repeating each time with the appearance at the seventh output of block 4 of the mode control and trigger pulse synchronization. thirty

In the automatic control mode, each time with the appearance at the seventh output of the mode control block 4 and the trigger pulse synchronization, the subsequent group of micro-assembly turns is controlled, on the corresponding

the outputs of the first switch 1 after D

a bundle of 2 pulses appears,

Impulses in packs are compared ¹ 40

unit 2 comparators of logical 'levels in amplitude with reference levels "0" and "1", set by the block 16 reference logic signals.

Formation of reference levels 0

45

and "I" by the block of 16 reference signals · occurs when the control input from the third output of the mode control block 4 and the synchronization signal with the level "Log, 1" 50 arrives at its control input

or "Logo0" respectively. The results of the comparison of logic levels from the corresponding output of block 2 comparators (in the manual control mode) or sequentially from all its outputs $$$ (in the automatic control mode) through the OR element 3 are fed to the second input of the second trigger 12.

Since block 2 comparators consist

of comparators, which in most cases have a high input resistance, when switch 1 is disconnected from the resolution inputs on the signal inputs of the comparators, an interference signal is present which will lead the comparators to their indeterminate state at the output of the element OR 3, to eliminate this phenomenon between the signal input of each comparator and the case included a resistor R _o '

The second trigger 12, the driver 13, the key 14 and the indicator 15 of the validity allows you to visually determine the defective output of the microassembly.

The second trigger 12 eliminates the appearance of a false pulse in the packet corresponding to the faulty output of the monitored microassembly when monitoring the level "Log.1", if there is no spark pulse on this output, and there is a constant level exceeding the "Log ₀ 1" coming from the output of the element NOT 11 to the reset input of the second trigger 12, and pulses coming to the installation input from the element OR 3, setting the trigger

12. At the second entrance to the unit state and the appearance of a false unit does not occur, that is, there is no corresponding impulse in the packet. The second trigger 12 performs a similar function if, when the unit compares 2 logic level comparators with respect to the amplitude of the pulses in the packet with the reference level “O”, the level “Log, 0” at the controlled output is greater than the reference.

Packs of pulses from the second trigger 12 are fed to the input of the former 13 sawtooth voltage.

The first impulse in the packet, arriving at the input of the shaper 13 (the reference frequency input), forms the minimum value of the output voltage, the second and subsequent pulses of the same pack form the leading-increasing one. sawtooth tension. The voltage shaping by the shaper 13 begins when a start pulse arrives at its start input from the seventh> output of block 4. A signal of the "Meander" type is sent to the input of the block installation from the first output of the mode control and synchronization block 4, while the presence interval "Log.O" equal to the monitoring time interval selected

'1591045 "

9

groups of controlled microassembly outputs. The signal from the output of the imaging unit 13 comes to the indicator 15 of the life through the key 14, which is controlled by the signal from the sixth output of block 4. The duration of this signal corresponds to the duration of the burst.

The key 14 allows you to exclude on the indicator 15 validity signal corresponding to the restoration of the imaging unit 13 to its original state, if there are no pulses in the pack.

Detection of malfunctions of the outputs of the first group of microassemblies is shown in the manual control mode (FIG. 10) where there are serviceable outputs:

"Out, 0", "Out.2", "Out, 5", "Out, 6", "Out 7" and faulty outputs: "Out 1" (there is a constant level "Log„ 1 ”),“ Out. З "(there is a constant level" Log.0 ") and" Vych.4 "(there is a constant level" Log.1 "), At the same time, at the input of the second trigger 12 (input of the pi · ay) driver, the pulses correspond to the healthy outputs microassemblies in the bundle are absent. The shaper 13 from the first impulse-30 in the bundle forms the minimum level (flat part) of the output voltage. different voltage, the duration of which is equal to the repetition period of pulses in a pack.In the absence of pulses in a pack, the corresponding portion of the sawtooth voltage is not formed and the voltage remains constant for the duration of the repetition period of the missing pulse.

Plots of output voltages on a 15-life indicator (FIG. 9) are shown in automatic control mode.

Since the generated signal for each group of outputs of the microassembly is synchronized with a trigger pulse and the same pulse triggers the usefulness indicator, at the last, at the corresponding duration of its sweep, the figures are superimposed.

If all outputs of the microassembly are in good condition, the waveform on the 55 55 availability indicator corresponds to FIG. 9a. If there are faulty outputs in any of the output groups, several 10 are installed on the 15 display availability indicator.

k figures, for example, as shown in

Fig, 96, If in the automatic control mode on the screen of the indicator 15

shelf life is observed waveform

5 is different from Fig. 9a, then in order to find faulty outputs of the microassembly, it is necessary to switch to the manual control mode.

Claims

Claims • A device for controlling micro-assemblies, containing a first switch, a logic level comparators unit, an OR element, a mode control and synchronization unit, a pulse generator, a ring shift register and an address register; , the outputs of the first switch are connected to the information inputs of the logical level composer unit, the outputs of which are connected to the inputs of the OR element, the output of the gene The pulse ramp is connected to the clock input of the mode control and synchronization unit, which is the fact that, in order to increase the reliability of the control by localizing the fault, the device contains the second and third switches, the first and second triggers, the unit of reference logic signals, AND element, NOT element, key, sawtooth voltage driver, pulse shaper on the front, counter, group address decoder, ^ 0 group indicator and expiration indicator, OR element output connected to the installation input of the second trigger a, the output of which is connected to the input of the reference frequency of the shaper, sawing voltage ^ 5 of different voltage, output and input. The settings of which are connected respectively to the information input of the key and the first output of the mode control and synchronization unit, the second to the sixth outputs of which are connected respectively to the input of the annular shift register recording, the control input of the reference logic signal block * '· catch, the second information and control inputs of the third switch n the control input of the key, the output of which is connected to the information input of the expiration indicator, the seventh output of the mode control unit and synchronization time 1591045 12 is connected to the input installation of the first trigger, the trigger input of the sawtooth voltage former, the first information input of the third switch and the synchro-input of the expiration indicator; the first and second outputs of the third · of the switch are connected respectively to the synchronous input of the ring shift register and the enable input of the parallel record of the counter, the group of lower-order output of which is connected to the terminals of the device for connecting the first group of inputs of the monitored microassembly to the first group of control inputs of the first switch and The group of information inputs of the address register whose outputs are connected to the information inputs of the counter, the high-order group of the output of which is connected to the terminals of the device to connect the second group of inputs of the monitored microassembly, the second group of information inputs of the address register and the inputs of the group address decoder whose outputs are connected to the second group the control inputs of the first switch and the control input of the second switch, the second output of which is connected to the synchronous input address register, the outputs the shift shift register is connected to the 5 inputs of the group indicator and to the information inputs of the second switch, the first output of which is connected to the reset input of the first trigger, the third, 0 information input of the third: switch, the high bit of the output of the ring shift register is connected to the input of the pulse shaper along the front, the output which is connected to, 5, the reset input of the counter, the synchronous input of which is connected to the output of the element NOT and the reset input of the second trigger, the output of the block of reference logic signals is connected to the input of the reference 20 nap yazheniya block comparator logic levels, the first latch output is connected to a first input of AND gate whose output is connected to the input terminal of the NOR and ustroyst25 wa for connecting the clock controlled microassembly, the pulse generator output is connected to a second input of the LP I I. FIG. 1 1591045 FIG. 2 2nd yyoda δβί n4 | counter Г7 - ^ Оре ^ собобокка "^ ^ ц · Rehip control 3rd Exit. μ mg and 11 I 30 'ι" Group selection * Input \ 6A2 "AbtanolR ggh 5th Exit, ....... ........ "Manual" ----- 0 —9 * · + 56 4th Output ~ ίth bykod 6th Output - 7th exit ........— About Fig. 1591045 from the outputs of the decoder / C of the outputs of the ring shift register Figure 4 Generator output is impulseV Seventh output of the block d Second output of the second switchboard PfVyi Output of the second switch Output of the first trigger xgshitllggsh! Outputs of Controlled Microassembly tllgsllllllllg 10 lh lh LA LG1GSHLAGSH.zlpllllllg - X -......... lh lh lh LLPLG 1PLL. P0 L1_ _lh _ gy Fig 5 1591045 Outputs of controlled micro · assemblies Output of the Second trigger 6th Output of the block 4 L1__ p £ _p ± _ ___ C7 glollll .. ...... Ί

1st Dmkha output 4 Dust-exerted aydnirubotel exit

FIG. 6

Pulse generator output

Packing Up And}} ^^

Seventh block output 4

Second Output Second Switch

LERBY EXIT Tue-_ G

horn switch

Exit first ——

trigger ’

Output element and

Counter input Outputs controlled microassembly

gllllup

ΐ2 __: _

P ±

_P2.

L £

1_Г

G-1

lllll

tllplsh ld .... — __

"P?_

A22

_gsh_

shshp

tllg

Gsy_

„Λί1_

п®

___Gi ⁵

FIG. 7

1591045

Outputs of controlled picrosdorn

Output of the second trigger

Exit / Bucket Dust Shaped Voltage

. P* ΠΖ2 -...... PL L # ____________ pl _ ......... pp those gryapppp PPPPLG1P ppp • 1 ______ (1__ P_ one Y ⁷ FIG. AT s

Microsdork is OK Myhrosdorha is defective

(Outputs of all groups are OK) 1-Outputs of the group (s) are OK

2 ^ - faulty outputs in groups

FIG. 9

1591045

findings

controlled

nikrosdrhts

5АЯГ.0Л · Ouch.1 Ex. 2 Vyhz Vyv.4 Vyh.5 Vyh.5 Oyh.7

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and.

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whether.

-e * "

L-DLL

lll

The output of the first konnutotor The output of the second trigger (input shaper

dust stress)

ι and