SU1499350A1 - Device for analyzing the state of logical circuits - Google Patents

Abstract

The invention relates to automation and computing and can be used in the implementation of means for monitoring and diagnosing logical node failures. The purpose of the invention is to expand the functionality of the device due to the possibility of registering the degree of activation of the logical circuit under study. The device contains a group of 1 information inputs, a group of 2 elements And, a group of 3 elements And, a group of 4 triggers, a group of 5 counters, a group of 6 display elements, a group of 7 triggers, a group of 8 elements EXCLUSIVE OR, an input 9 of device synchronization, an input 10 of the initial installation of the device . The device provides information about the number of logical differences transmitted along the information path of the circuit under study, as well as about the number of transmitted differences at intermediate points of the path. A positive effect is achieved by introducing AND AND EXCLUSIVE OR groups of elements, triggers, counters, and display elements. 1 il.

Description

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The invention relates to automation and computing technology and can be used in the implementation of means of monitoring and diagnostics of failures of logical nodes.

The aim of the invention is to expand the functionality of the device by providing the possibility of registering the degree of activation of the logical circuit under study.

The drawing shows a diagram of the device

The device contains a group of 1 information inputs of the device, a group of elements I 2, a group of elements I 3, a group of triggers 4, a group of counters 5, a group of elements 6 of the display, a group of triggers 7, a group of elements 8, EXCLUSIVE W), input 9 of the device synchronization, input 10 initial installation of the device, Triggers of the 7th group and elements EXCLUSIVE OR 8 groups are combined in pairs in the logical-analyzer 11,

Let it be necessary to determine the degree of activation of a certain path of the logical scheme under study. The degree of activation refers to the number of logical drops transmitted from the beginning of the information path to its end, or the number of changes in logical levels at the output of the last element of the information path being scanned, caused by changes in logical levels at the input of the first element of the path. the number of points of the studied information path, the following are chosen as points of the studied information path:

the beginning of the path is the input of the first log-element.), clocked inputs of the memory elements;

clock inputs of the memory elements of the information path under study;

end of the path (the output of the last element of the path).

Under the zero level event we will

to understand the change at any point of the studied path of the logic level, the first level event is the change of the logic level at two points of the logical circuit under study, which occurred during one tact of supplying the input action. In this connection, the selected points are combined into a pair, opportunity

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the occurrence of the first level event at these two points.

Zero level events denote

S.-O S °, - / "(21-1) and 2i are the numbers of points (inputs). First level events are denoted by S I, where i is the device channel number or the number of a pair of points. Event S is an event S. provided that an event has occurred at some preceding clock.

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The device operates as follows.

After connecting the device to the logical circuit under study, a clock pulse of positive polarity is applied to the device input 9, which records the initial state of the logical circuit being studied in the triggers 7 of the first group. Then, the device is initially set up, which implies that a positive polarity pulse is fed to the input 10 installation of the device, resulting in triggers 4 of the second group and counters 5 are reset to zero, Dp of the triggers 7 are not required for the initial setup, which follows from the algorithm operation. The synchronization of the device is such that the occurrence of a positive pulse at input 9 permits the passage of signals from the output 2i-: ro of the EXCLUSIVE OR 8 element to the clock input of the trigger 4 of the second group of the i-ro channel, except for i p, and the second input of the i-ro element And 3 of the second group, as well as clocks the i-th element And 2 of the first group. By the decay of the positive clock pulse, the triggers 7 of the first group enter information about the new state of the circuit under study.

Each i-th analyzer 11 assembled on triggers 7 of the first group and elements EXCLUSIVE OR 8 provides registration of zero-level events at points (2i-l) and 2i circuits to which the corresponding inputs of the device are connected. The registration of the indicated zero-level events is accompanied by the appearance of a single logical level at the outputs of the corresponding elements EXCLUSIVE OR 8,

When an event S occurs at point 1 connected to input 1.1 of the device, a logical unit appears at the output of the first element EXCLUSIVE OR 8, arriving at the information input of the first trigger 4 of the second group, as well as at the first input of the first element 3 of the second groups. If at the same clock an event Sj occurred at the point connected to the input 1 ± 2 of the device, then a logical unit also appears at the output of the second element EXCLUSIVE OR 8. When the next clock pulse is applied, this pulse goes through the AND 2 element of the first group, the second input of which is also set to a logical unit, to the input of the recording of the first trigger 4 of the second group, and this trigger switches to one if the first level event occurs at points 1 and 2 connected to the inputs 1-1 and 1.2 of the first channel of the device. Since at the first input of the first element And 3 of the second group there is a signal of a logical unit, the clock pulse is fed to the counting input of the first counter 5 and the last information is written that the event S occurred in the first channel.

The logical unit from the output of the first trigger 4 of the second group is fed to the third input of the element AND 2 of the first group of the second channel and is the enable signal of the second channel of the device. If at points 3 and 4, connected respectively to inputs 1 3 3 and 1.4, a first level event S also occurred, then when a clock pulse arrives at the counting input of the second trigger 4 of the second group, a logical unit is written to the trigger provided that the first channel recorded an event Sj on some previous tick Logical unit at the output. the second trigger 4 of the second group arrives at the third input of the element And 2 of the third channel of the device, allowing its operation, etc.,

The impulse from the output of the second element And 3 of the second group arrives at the counting input of the second counter 5, which captures the event S. The same impulse goes to the first input of the zero setting of the first trigger 4 and resets it to zero, thereby prohibiting the repeated event s second channel device

Before the occurrence of the next event S, the registration of which is performed by the first channel. When the first channel registers an event device S, the second channel is again enabled by turning on the second element 2.

The operation of the last channel is as follows. If there is an enable signal for the n-th channel from the output (nl) -ro of trigger 4 of the second group, as well as the appearance of logical units at the outputs of the n-th input analyzer, which corresponds to the fixation in the n-th channel of the S event, the clock pulse passes through the element AND 2 of the first group and arrives at the counting input of the nth counter 5, which is fixed0 RUB event S The clock pulse from the output of the nth element AND 2 of the first group enters the first input of the zero setting (nl) -ro trigger 4 second group and reset to zero occurs

5 of this trigger, thereby prohibiting the fixation of the nth channel of the repeated

S

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before registration (p-1) -k

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katsiya display the contents of the counters dp of its visual perception I

The use of two elements: And 2 of the first group and And 3 of the second group in each channel, except the last, is explained by the peculiarity of the functioning of the triggers 4 of the second group, which is that the trigger 4 of the second group should be set to one if in the corresponding pairs of points connected to this channel, event S occurred, where i is the channel iomer, if during the time interval between the occurrence of events S and S, a zero level event occurred at the second point of the pair in question, i.e. at point 21, trigger reset 4 is necessary. channel i-ro groups and channel lock () -ro, since otherwise the registered event may carry distorted information about the activation of the corresponding information path, since one of the reasons for the occurrence of the S% event may be a change in the logic level at the second point of the pair ( point 2i) due to circuits that are not included in the considered 1 1st information path,

Claims (1)

Claims A device for analyzing the states of logic circuits containing the first group of two triggers and an EXCLUSIVE OR element, and the clock inputs of the first group of triggers are combined and connected to the synchronization input of the device, the information input of the first trigger of the first group is EXCLUSIVE OR, the second the input of which is connected to the output of the first trigger of the first group, characterized in that, in order to expand the functional capabilities of the device by enabling of the activation degree of the logical circuit under study, in the device the first group of triggers contains 2 (n-1) triggers, and a group of 2n-1 elements EXCLUSED OR, the first group of n-elements AND, the second group of p-1 tr igggers, a group of n counters and a group of n display elements, the information input 2i-ro of the trigger of the first group (i 1,2, o., p) connected to the first input of the 21st element EXCLUSIVE OR group, the second input of which is connected to the output of the 2i-ro triggers of the first group, the output of the 2i-th element of the IC Iii) - sistent OR group is coupled to a first input of i-ro AND gate second input of the first group is combined with clock inputs of triggers of the first group and connected to the synchronization input of the device, output (21-1) -th element EXCLUSIVE OR group is connected to the first input of the i-ro element AND the second group and information input of the i-ro trigger group, output j-ro (, 2,., „, P-1) of the element AND of the first group is connected to the second input of the j-ro element of the second group and the clock input of the j-ro trigger of the second group, the output of the j-ro element of the second group is connected to the counting input of j-ro the group counter and the first input of the setup in O (jI) -ro trigger of the second group-, the output of the J-ro trigger of the second group You are connected to the third input (j + l) -ro of the element AND of the first group, the second inputs of the installation into the O triggers of the second group are combined with the installation inputs of the About counters of the group and connected to the input of the initial installation of the device, the outputs of the i-ro counter of the group are connected to. the inputs of the i-ro element of the group indication, the output (2p-1) of the element EXCLUSIVE OR of the group is connected to the fourth input of the n-th element AND the first, the output of which is connected to the clock input of the n-th group counter and the first input of the installation to O ( n-1) th trigger of the second group, informational inputs trigger s of the first group form a group of informational inputs of the device