SU1399706A1 - Apparatus for monitoring and diagnosis of faults - Google Patents

Abstract

The invention relates to means of automatic control and diagnostics of complex technical systems and can be used to recognize faults in systems with a predominantly discrete nature of the technological cycle. The chain of the invention is to increase the completeness of control. The device contains the first 1 and second 2 registers, display unit 3, multiplexer-4, memory block 5, first 6 and second 7 counters, element 8, clock generator 9 and control unit 10. Fault recognition is performed by highlighting the group of diagnostic features that are significant for a given fault and checking them for consistency with the values characteristic of the fault. 3 il. about iS (L

Description

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The invention relates to automation and computer technology and can Syt used to monitor and diagnose complex technical systems, in particular in the systems of electroautomatics of aircraft.

The purpose of the invention is to increase the completeness of the control device.

The device is tuned to the environment of a specific monitoring object by setting a task for each diagnostic situation (malfunction) S, - (i 1, ha) of the diagnostic vector

Fig. 1 shows the functional (1a diagram of the device proposed; ka Fig. 2 is the control unit; Fig. 3 is a timing diagram explaining the operation of the device. 15 p (S;), P (S;) (Р ,,, Pj, ..., Р; „).

The device contains (Fig. 1) the first rd p ;. f-1,0, + 11 and is defined in 1 and second 2 registers, block 3 indications - depending on the value of the diagnostic, multiplexer 4, block 5 of memory, of which sign d;

malfunction S;

first 6 and second 7 counters, first

n i

-1 if S; characterized by the value of d, - 0;

Oh, if S; any d value is allowed ;; +1 if S; characterized by the value of dj.

i

These numbers P; J in binary complement

The i / ioM (two-bit) code is stored in memory block 5 at an address determined according to the following code, (by healing:

I A (P ;.) 2 - (i - 1) - «- (j - 1),

k-t to where K is chosen from the condition 2 ns2

providing with this organization the process of recognition is the most: the commercial use of memory. - The diagnostic vector P () is recorded in the memory (the one in the 1st diagnostic situation is the absence of (; fault P (S,) (0.0, f ... O)).

I Fault Recognition is performed as follows.

At the beginning of each new recognition cycle in the second register 2, the current vector of binary signs D (d, ..., d) from the control object is recorded and the first 6 and second 7 counters are embraced. In this case, the first element P is selected from the memory block 5.

P

The first diagnostic vector P (S,), and using multiplexer 4, selects the first bit d, the binary characteristics vector D. In control block 10, the sign bit of the number P is summed modulo 2 with binary binary d, and the result is logically multiplied by the bit module (the element EXCLUSIVE OR 11 and the second element And 15), forming a logical signal ot.

o

the element AND 8, the clock generator 9 and the control unit 10 containing (FIG. 2) the element EXCLUSIVE OR 11, the element NOT 12, the first 13 and the second 14 elements OR NOT, the second 15, third 16, fourth 17, fifth .18 and the sixth 19 elements And, entrances 20-24, exits 25-28.

The device is tuned to the environment of a specific monitoring object by setting a task for each diagnostic situation (malfunction) S, - (i 1, ha) of the diagnostic vector

5 p (S;), P (S;) (Р ,,, Pj, ..., Р; „).

n i

is poised

five

0

five

0

with

five

0

It's obvious that . O only when the current value of the attribute d satisfies the diagnostic situation S ,. In this case, a single level signal appears at the output of the first element OR NOT 13, opening the sixth element AND 19 and the next pulse of the clock generator 9 is fed to the counting input of the first counter 6, increasing its content by one. This selects the next element of the diagnostic vector and the next bit of the binary signs vector D. The process is repeated for all P, - and d - for which oi 0. If about 1 (the current value contradicts the diagnostic situation S), then a signal appears unit level at the output of the element is NOT 12, the third 16 and fifth 18 elements are opened AND, and the next clock pulse arrives at the zeroing input of the first counter 6 and the counter input of the second counter 7. Thus, the return to the first binary sign d is made and the transition to first item in P, the next diagnostic vector P (Sj). If for the second vector (there are PJ. And d, for which cd 1, then the transition to the third diagnostic vector is made, etc.

If for any diagnostic situation (k t) oi O for all Rc | and d; (with k m + 1, this is obviously done), then the contents

the first counter 6, increasing, reaches the value (n - 1). At this moment, at all inputs, and, consequently, at the output of the first element AND, signals with a level of logic one appear. Since ot O, the signals of the unit level appear also at the outputs of the second element OR NOT 14 and the element 12, the fourth I7 and the fifth I8 AND elements open and, on the leading edge of the next clock pulse, the contents of the second register are entered into the first register 1 counter 7, which uniquely identifies the number of the given diagnostic situation S, which goes to the display unit 3. On the falling edge of the same pulse, a new vector of binary features D is inserted into the second register 2 and the first 6 and second 7 counters are zeroed, thereby initiating a new recognition cycle.

An indication of the diagnostic situation S indicates the absence of malfunctions in the controlled system, the occurrence of which could be detected by the proposed device.

In comparison with the known, the proposed device allows to implement a fundamentally different algorithm for recognizing faults in a controlled system. This significantly expands the class of recognizable faults, and, consequently, enhances the functional reliability of the monitored system.

Claims (1)

Invention Formula A device for monitoring and diagnosing faults, containing the first register connected by outputs to the inputs of the display unit, the first counter connected by the outputs to the address g inputs of the multiplexer to the inputs of the first element I, and the clock pulse generator differing 15 0 25 ABOUT 0 g so that, in order to increase the control field, a second counter, a second register and a control unit containing the first and second OR-NOT elements, the NO element, the EXCLUSIVE OR element, AND elements from the second to the sixth, second register are entered into the device the outputs are connected to the information inputs of the multi-apexor, the second counter is connected to the information inputs of the first register, the low and high address bits of the memory block are connected respectively to the outputs, the first and second counters, the first and second inputs of the EXCLUSIVE ALREAM OR connected respectively to the first data output of the memory block and to the multiplexer outputs, and the output to the first input of the second element AND, the second input of which is connected to the second data output of the memory block, the output of the second element AND connected to: the first inputs of the third element AND , the first and second elements are OR NOT, the second input of the first element OR is NOT connected to the output of the first element AND, and the output to the first input of the sixth element AND to the second input of the second element OR NOT and through the element NOT to the first input n of the element And, the first the input of the fourth element I, is connected to the output of the second element, the second inputs of the third, fourth, fifth and sixth elements I are connected to the output of the clock generator, and the outputs of the third, fifth and sixth elements I are connected respectively to the counting input of the second counter, to the input reset and with the counting input of the first counter, the course of the fourth element I is connected with the counting input of the second counter and with the gate inputs of the first and. the second registers, the information inputs of the second register are the inputs of the device for connection to the outputs of the control object.