SU1182540A1 - Device for checking digital units - Google Patents

Abstract

A DEVICE FOR CONTROL OF DIGITAL BLOCKS, containing a control unit, the first output of which is connected to the first input of the display unit, the first input and the second output are connected respectively to the transfer port of the first discharge and the counting input of the test counter, the output of which is connected to the first input of the first And element connected the output with the second input of the display unit, the second input of the first element I is connected to the second input of the second element I and the output of the comparison unit, the first input of which is connected to the output of the memory of the standards, Connections. an entrance with the third exit of the unit up. The fourth output of which is connected to the installation input of the counter of monitored units, connected by the first output to the first input of the second element I, the output of which is connected to the third input of the display unit, the second output of the counter of monitored units is connected to the second input of the control unit, the fifth output connected to the counting input of the counter, controlling the MBtx of the blocks and the control input; Yultiplexer, whose output is under-i. It is connected to the second input of the comparator unit, the sixth output of the control unit is connected to the input of the test memory block, the output of which is connected to the output of the device, different from the fact that, in order to reduce the testing time of the same type of blocks with integrated control, a major element and register are entered into the device The inputs of which are connected to the first inputs of the device, the second 00 inputs of which are connected to the first information inputs of the multiplex Q1 and the inputs of the majority element, “lik whose output is connected to the second information onnym input of the multiplexer, the third information inputs connected with outputs of register.

Description

111 The invention relates to computing and can be used to control blocks of the same type during testing. The purpose of the invention is to reduce the time for checking single-type blocks with integrated controls. FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - functional block diagram. The device contains a control unit 1., an indication unit 2, a test counter 3, a counter of 4 monitored blocks, a reaction measurement memory block 5, a test memory block 6, the first element AND 7, the second element AND 8, a comparison unit 9, a multiplexer 10 , control unit 11, majority element 12, parallel register 13. Control unit 1 includes the first trigger, 14, the third element 15, the first shift register 16, the counter of test addresses .17, the fourth element, And 18 the counter of 19 addresses of the reference reactions, the fifth element And 20, pulse shaper 21, second trigger 22, element 23 h supports, encoder 24, generator 2 5 pulses, neck element AND 26, second shift register 27, first element OR 28, third trigger 29, comparison circuit 30, seventh element AND 31 second 32 and third 33 elements OR, number 34 of controlled blocks, the keyboard 35. The device works as follows. Control units 11 that do not have built-in control means are connected to the first inputs of the multiplexer 10. Before starting operation from control unit 1, 5 and 6 tests and standards are entered in accordance with the test sequence and test standards of units 11, into the counter 4, corresponding to the number of blocks 11, and in the counting 3 - the numbers (in the additional code) corresponding to the number of control tests with which the control of blocks 1t is carried out. From block 1, the device starts up, while from block 6 the first control test is given to the inputs of blocks 11, and one of the inputs of block 9 is the standard of the reaction of blocks 11 to this test from block 5. By the signals of block 1, multiplexer 10 0 performs connecting the outputs of blocks 11 to the second input of block 9 at the same time. Simultaneously in counter 4, blocks 11 are connected by block 9. If the results of the comparison of blocks 11 with standards are positive, block 9 generates a inhibitory signal to the inputs of elements 7 and 8. In block 2 nikaka information qi does not arrive. In case of correction of the reaction of any of the blocks 11 with the standard, block 9 provides the enabling signal to blocks 2 and 3, and block 2 receives information about the failure of a specific test. At the same time, the control of this test of subsequent blocks is not violated. After the last test block 11 finishes monitoring, block 1 generates a signal in block 6 about issuing the next test to blocks 11, and the control cycle repeats. The end of the test of blocks 1 1 with the last test is recorded by block 2 according to the signal received from block 1 and formed last by the signal from the counter of 3 tests. In block 2, all losses of the defective blocks 11 and tests with which faults were detected are recorded. Block 1 works as follows. Before the device starts operating, the signals from the keyboard 35 of the former 21 are recorded through the elements 15 and 18 and the control tests and reaction standards of blocks 11 are recorded in blocks 6 and 5. A number corresponding to the number of simultaneously controlled blocks 11 is entered into register 34 from the keyboard 35 Using the keyboard 35 and the encoder 24, a number is generated corresponding to the number of control tests in the additional code that enters counter 3. When the described sequential operations are completed, press the button on the keyboard The trigger trigger 29 is set to 1, the element And 26 allows the flow of pulses from the generator 25 to the shift register 27. From the first output of the register 27, a clock pulse arrives at the counting input of counter 17, which forms the address of the first test, which enters block 6. Similarly, the clock pulse from the second output of register 27, the counter 19, forms the address of the response standard of blocks 11 to the first test, which arrives at block 5 By the clock pulse from the third output of the register 27, the trigger 29 is set to 1, and through the element AND 15 the pulses from the generator 25 are fed to the register 16. From the output of which the control signals are sent to the multiplexer 10 for serial connection or to block 9 outputs the comparison unit 11. When comparing codes received from the counter unit 4 and code written in the register 34, the comparison circuit 30 generates a reset signal to the flip-flop 22. The AND element 15 is closed, the register 16 is reset. At the same time, through the OR element 32, the signal from the comparison circuit 30 sets the trigger 29 to 1, three successive pulses arrive in register 27 from generator 25, and the next test runs the same test cycle

The arrival in unit 1 of imuls. Co) of counter 3 (the pulse of transfer of the first discharge of the counter) indicates that the last test has been outputted to blocks 11, trigger 14 is set to 1 and prepares the first input of element 3 When a signal arrives at its second input indicating the end of the test of the last block 11, triggers 29 and 22 are reset. The cycle for issuing tests and reaction standards from blocks 6 and 5 stops. On block 2

An end signal is issued, checks of the blocks 11 connected to the device.

Blocks 11, which have built-in controls, are connected by the first outputs to the element 12, and the second outputs are connected to the inputs of the register 13. Counters 3 and 4 are reset to the initial state.

From the output of block 6, test signals are simultaneously supplied to the inputs of all monitored blocks 11. Information from their outputs through the majority element 12 and multiplexer 10 is fed to the input of the comparison unit 9, and then to the display unit 2.

After that, all bits of the parallel register 13, in which the fixed signal of the control devices, pb is divided, are compared with the reference during the test.

The verification of the distortion of the output information of the individual blocks 11 arising in the process of execution is countered by the majority element 12, therefore a positive result of checking the same type of blocks according to the information on their outputs indicates that most of them are in good condition. A comparison with the standard of the contents of the register 13 allows to establish the correct functioning of each monitored block during the test, and the accuracy of the missing error is determined by the efficiency of the built-in hardware of the monitored blocks.

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Claims (1)

DEVICE FOR MONITORING DIGITAL BLOCKS, containing a control unit, the first output of which is connected to the first input of the display unit, the first input and second output are connected respectively to the transfer output of the first discharge and the counting input of the test counter, the output of which is connected to the first input of the first AND element connected by the output with the second input of the display unit, the second input of the first element And is connected to the second input of the second element And and the output of the comparison unit, the first input of which is connected to the output of the memory unit of standards, connected Nogo. an input with a third output of the control unit, the fourth output of which is connected to the installation input of the counter of the controlled units, connected by the first output to the first input of the second element AND, the output of which is connected to the third input of the display unit, the second output of the counter of the controlled units is connected to the second input of the control unit the fifth output of which is connected to the counting input of the counter is controlled by 1 blocks and the control input of the multiplexer, the output of which is sub-ι. '· Keys to the second input of the comparison unit, the sixth output of the control unit is connected to the input of the test memory unit, the output of which is connected to the output of the device j characterized in that,' in order to reduce the time of checking the same type of units with built-in control, the device has 2 majority element and register, the inputs of which are connected to the first inputs of the device, the second inputs of which are connected to the first information inputs of the multiplexer and the inputs of the majority element, the output of which is connected to the second information input a duplexer, the third information inputs of which are connected to the outputs of the register.