SU1274007A1 - Device for checking address sections of memory blocks - Google Patents

Abstract

The invention relates to a computational technique and can be used to control the address circuits of memory blocks. The aim of the invention is to increase the speed of the device. The device contains an address tap, a multiplexer, a comparison unit, a control unit, an address fixing unit, groups of display elements, a local control unit, and a logic unit. The device provides a sequential check of address circuits (AD) of memory blocks, and the i-ro bits of the address code from the multiplexer are used as data for checking the i-AD. At the same time, in the address fixing block, the results of the address analysis are accumulated during each test reading cycle. The results of the analysis for cadz AD are memorized until the end of the test, and then transferred to a logical block where the failed ACs are located. The device detects multiple faults with a constant fault and a short time between the ATs. 5 il. tc

Description

The invention relates to computing and can be used to control the address circuits of RAM blocks. The aim of the invention is to improve the speed of the device. Figure 1 presents the scheme set-. 2 are a diagram of a control unit i in FIG. 3 is a diagram of a comparison unit; in FIG. 4 is a diagram of a local control unit; in FIG. 3 is a diagram of a diagnostic unit. The device (Fig. 1) contains the address counter 1, multiplexer 2, comparison block 3, control block 4, KE 5 elements group, AND 6-9 element groups, OR 10, P element groups, RAM blocks 12, 13, groups of display elements 14 and 15, local control unit 16, logical block 17. Figure 1 also shows the monitored memory block 18, the inputs of the installation 19, the start 20, the synchronization 21 and the data sampling of the device 22, communication 23-46 . Blocks 5-13 form a block fixing addresses. The control unit (Fig. 2) contains the triggers 47, the elements NOT 48, the elements AND 49, the elements OR 50. The comparison unit (Fig. 3) contains the elements EXCEPTING OR 51 and the element OR 52, The local control unit (Fig. 4) contains the triggers 53, counters 54, elements And 55. multiplexers 56. The logical block (figure 5) contains a group of elements EXCLUSIVE OR 57, element NOT 58, groups of elements And 59, element And 60, groups of flip-flops 61. The device operates in two modes. In the first mode, a sequential check of all address circuits of the memory block 18 is performed. The DP control of each address chain of block 18 conducts a cycle of writing test numbers into a controllable memory block 18 and a cycle of reading numbers test numbers from block 18, as well as their bitwise comparison with reference test numbers. As test numbers (z. Writeable and reference for checking the i-th address circuit, signals of the i-th bit of the address code to the monitored memory block are used. The choice of the tested address circuit is made by the g-bit code (r log N ) generated by the second control unit and acting on the control inputs 24 of the multiplexer 2. In the read-out cycle of test numbers from the monitored memory block 18 a random analysis of the address address code is performed, for KOTOR07-4, what value is (logical 0 or 1) accept code bits these addresses. The results of the analysis of the address code when checking each address chain are stored in 12jH 13 blocks (blocks 12 and 13 are 2 n words, word width is n) until the end of the first mode separately for cases when there were failures when reading the test the numbers from block 18 and separately for cases where such failures were not.In the second mode of operation, the analysis results are processed sequentially for each address chain and the indication of fault information is displayed. Processing of the analysis results consists in a parallel comparison of mod 2 equality information O bits in the codes of addresses of references with information on equality 1 of the corresponding bits in the codes of addresses addresses. Such processing allows detection of a faulty address chain. Processing results are recorded and indicated by display elements 14 and 15. Before performing the cervical mode, the device is reset. To bring the device back to its initial state, the input 19 of the initial installation is given a logical O signal, and the clock frequency pulses are input to the device synchronization input 21. Signal 19 goes to the first input (setting) of the address counter I and zeroes it. In addition, the signal 19 (logical O) goes to the first inputs of the first b, second 7, third 8 and fourth 9 groups of elements I, which leads to the formation of information inputs 39 and 43, respectively, of the first 12 and second 13 RAM blocks of the initial zero , information. Simultaneously, in control block 4, which also receives a logical O signal from input 19 and pulse 3

In this case, the clock signal 21 is formed, the information recording signal and alternately the first and second addresses are received respectively at the write-read input 33 and the first address input 32 of the first 12 and second 13 RAM blocks, as well as the input of the second control unit 16. At the same time, the inputs 34 of the first

12 and the second 13 blocks of RAM, a sequence of n addresses (r-bit code) is received, which is formed in the second control block 16 in the presence of signals 19 and 32. This will lead to writing to all memory elements of blocks 12 and

13 original zero information (i.e., the first 12 are reset

and the second 13 blocks of RAM). In addition, the logical O signal arrives at the inputs of the second control unit 16 and the logical unit 17. This will result in the initial setting of the logical unit 17 and forming at the outputs 30 and 35, respectively, the signals of the logical 1 and logical O, which prepares the device for the first mode of operation. A zero code is also set at the control inputs 24 of multiplexer 2, which selects the signals of the first digit of the address code as the test number for checking the first address circuit of the monitored memory block 18.

To carry out the first mode of operation, the logical O signal is removed from the input 19, and a logical 1 signal is sent (the clock frequency pulses continue to arrive at the device synchronization input 21). This sets a zero code at address inputs 34, which defines the memory area (corresponding to the first address chain of block 18) in blocks 12 and 13, into which the results of the analysis of the addresses of the calls will be recorded. To start the device, an input signal {logical O) is input to input 20. From the output of the local control unit 16, the direct count input 23 of the address counter 1 begins to receive clock pulses. In the counter of address 1, the n-address code of the address addresses is sequentially generated, which are fed to the address buses 26 of the monitored block 18, as well as the information g

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multiplexer 2. The control inputs of multiplexer 2 and the second group of address inputs 34 of the first 12 and second 13 blocks 5 of the operational memory from the corresponding outputs of the local control unit 16 receive the g-bit (zero) code corresponding to the first checked address circuits in memory block 18, to ((this code was formed during the initial setup of the device). At the outputs of multiplexer 2, the signals of the first digit of the address code are passed to the m input numeric tires 15 27 of the monitored memory block. -ch The readout of the monitored memory block 18 from the output of the control block 4 receives signals for recording test numbers. After recording 20 test numbers into the controlled

the memory unit 18 at the last address, the address counter 1 continues to sequentially generate the address addresses (the clock frequency pulses continue to arrive at the input 23 of the address counter from the 5 output of the local control unit 16), and an overflow pulse is generated at its output 25, which goes to the control unit 4 0 and in block 16 of local control. The overflow pulse 25, having entered the control unit 4, will prohibit the signal 29 from entering the test numbers from the bus 29 and allow the read signals to it, i.e. Test numbers will be read from the monitored memory block 18. In the read cycles, the reference m inputs of the comparison unit 3 receive the reference test numbers from the outputs 27 of the multiplexer 2. The second m inputs of the comparison section 3 receive the read test numbers from the output numeric tires 28 of the monitored memory block 1B. With proper comparison of the read and reference test numbers, the output signal 31 of the comparison unit 3 produces a logical signal O about the absence of failure, and if Q is incorrect, the logical signal 1 indicates that there is a failure. The signal 31 is fed to the input of the control unit 4. If there are failures, then in control block 4 a first address is formed (for example, logical O), and if there are no failures, then the second hell: res (for example, logical I). The first or second addresses are fed to the first address input 32 of the first 12 and second 13 blocks of RAM. In addition, in block 4 of the control, in each step of reading the test number from the monitored block 18 of memory, recording signals are generated which are fed to the input 33 of writing the reading of the first 12 and second 13 blocks of RAM, simultaneously from the outputs 26 of the address counter 1 n-bit code the addresses are fed to the inputs of the n elements of HE 5 and the second inputs of the n elements of the second group 7. From the outputs of the NE 5 elements the inverted n-bit code of the address goes to the second inputs of the n elements of the first group 6. The first inputs of the elements of the first 6 and second - 7 gr the signals of logical 1 are received from input 19.. If all n bits of the address code of the address have a logical 1 state, then from all outputs of n elements AND of the second group 7 signals of logical 1 will pass through n elements of the OR of the second group 11 to n information inputs 43 the second block 13 of the operative memory and recorded in all n of its bits at the first or second address (respectively, for failures and for the absence of failures in the memory area specified by the code on the inputs 34 of the second group corresponding to the tested address circuit of the monitored block 18 ami The information inputs of the first 12 blocks of operational memory do not receive signals from logical 1, and the original zero information will remain in it. Similarly, if all n bits of the address address code have a logical O state, then the logical 1 signals from the outputs of the element group - NOT 5 will go to the output of the elements AND of the first group b and through the elements of the OR of the first group 10 will go to the information inputs 39 only the first 12 blocks of RAM and will be written in all n of its bits at the first or second address in a given area. Once recorded in the first 12 or in the second 13 block of RAM, then 1 is rewritten into it in all the remaining test cycles, arriving at information inputs 39 or 43 via the information outputs 40 of the first RAM block 12, the second inputs the elements of the third group 8, the second inputs of the elements OR of the first group 10 or through the circuit, the information outputs 44 of the second RAM block, the second inputs of the elements AND of the fourth group 9, the second inputs of the elements OR of the second group 1. Therefore, if test number from the monitored memory block 8 at which there was (no failure 5i was detected, and the address code of the address was at least once equal to the logical O signal, then at the first (second) address in the 1st bit the corresponding the area of the first RAM block 12 will record the signal of logical 1, which will remain until the end of the device operation in the first mode. Similarly, when reading a test number from the monitored memory block 18, which was (the failure of the i-th code code was not detected the address of the address was from least once equal to the signal logic 1, then the first (second address in the i-th bit of the corresponding area 13 of the second operational zapishets memory block. a logical 1 signal, which is maintained until the end of operation of the device in the first mode. After handling the reading of the test number from the monitored memory block 18 at the last address, the address counter I continues to sequentially generate the address addresses (the input 23 of the address counter 1 continues to receive clock pulses from the output of the second control unit, and an overflow pulse is generated at its output 25, which enters the control unit 4 and the local control unit 16. The overflow pulse 25, entering the control unit 4, will prohibit the receipt of read signals to the bus 29 and will allow the e of the recording signals. At the same time, the overflow pulse 25, having entered the local control unit 16, will generate at outputs 24 and 34 a g-bit code corresponding to the verification of the second addressable circuit of the controlled control unit 18. described above, the next (second) address circuit of memory 18. Then, in a similar way, the device will test the 3rd, 4th, .. ,, nth address circuit. After completing the verification of the last (nth) address circuit the local control unit 16 will stop the formation of pulses,. arriving at the input 23 of the address counter 1, and also forms at the outputs 30 and 35i, respectively, the signals of logical b and logical 1, which will transfer the device to the second mode, work. In the second mode of operation, at the output 33 of the control unit 4, read signals are generated, which are fed to the write-read input of the first 2 and second 13 RAM blocks. If at the input 22 a logical O signal is set, then from the output of the control unit 4 to the first address inputs of 32 RAM blocks 12 —and 13 the signal of the first address (logical signal, and if input 22 has a logical I signal, the signal the second address (logical 1 signal) From the outputs of the local control unit 16 in the second mode of operation, the signals of all n addresses (r-bit code) are sequentially received at the second address inputs 34 of the first 12 and second 13 blocks of the working memory. from the first 12 and second 13 blocks opera information on the results of the analysis of all n address circuits of the monitored memory block 16 by the first (input 22 signal logical O | or the second (input 22 signal logical IM address. Information about the results of the analysis from the outputs of block 12 and 13 goes to: logical block 17. In logic block 17, information about the results of the analysis, read from the first 12 blocks of RAM, to the first address, is compared mod 2 with the information about the results of the analysis, read by the first address from the second block 13 proliferative memory. The results of the comparison modulo 2 are stored on the triggers for each of the n addresses of the first 12 and second 13 memory blocks, and then I indicate with the second group of display elements 15. This processing of the analysis results reveals and indicates malfunctions caused by repeated short baking between each of the two address chains of the controlled block of 18 networks. Similarly, in logic block 17, information about the results of the analysis read from the first 12 and second 13 blocks of RAM to the second address is processed, but the results of processing of mismatches of the type O (the constant 1H is indicated by the first group of elements 14 and dictation). Consider for example the case when a permanent O-type fault is present on the i-th address circuit of the monitored memory block 8. When the memory block is monitored with test numbers equal to the signals of the 1st bit of the address code of the i-th bit of the ad code The number of calls for which there are no failures (at the output 31 of the logical signal. 1,) always takes on logical values, while all other bits of these addresses take on values of both logical 1 and logical O. Therefore, in the first mode of operation of the device, the second address of the i-th area in the i-th bit of the second block 3 of the RAM and in all its other bits the signals of logical 1 will be recorded, and at the second address of the i-th region of the first block. The 12 main memory signals of logical 1 will be recorded in all bits, except for i-ro. When checking the memory block 18; test numbers, which used signals from all other f except the i-rol) bits of the address code, there will be no failures even during all bits of the first 1 2 and second 13 RAM blocks at the second address of all areas (except the i-th) signals of logical 1 will be recorded. In the second mode of operation of the device, input 22 sets a logical I signal, according to which control unit 4 will generate a second address (logical 1 signal) arriving at the first address input 32 of the first 12 and second 13 blocks promptly memory. Codes corresponding to all monitored address chains of the monitored memory block are sequentially received at the second address inputs 34 of blocks 12 and 13 and block 18 of the local control center. The logical block 17 consistently receives information on the results of the analysis of the codes of the addresses of the appeals for which there were no responses. in logic block 17, it is compared modulo 2 and information is stored from the outputs of the first 12 and second 13 blocks of RAM, and then goes to the first group of display elements. In our case of data, processing of the analysis results will allow detecting and then indicating the malfunction in the i-th address bus of the monitored memory block. Similarly, permanent type O or constant 1 malfunctions are detected in any other address chain, as well as in case of multiple malfunctions of the specified type. In the case when the i- and J-address circuits are closed between themselves or when there are multiple closures two address circuits between each other, the detection of such faults is carried out as well as dp faults of the type O or 1, but the memory of the results of the analysis of the addresses of the addresses is stored at the first address of the first 12 and second 13 RAM blocks, and the indication of the results of the control (after processing) by the second group of elements 15 of the display.

Claims (1)

The invention The device for monitoring address circuits, memory blocks containing the first and second groups of display elements, an address counter, the installation input of which is connected to the first inputs of the control unit and the address fixing unit and is the installation input of the device; one output of the address counter is connected to the second the input of the control unit and the other outputs are the address outputs of the device and are connected to the inputs of the first group of the address fixing unit and the multiplexer, the output of which is 5 of the second group. is the information output of the device and is connected to the first input of the comparison unit, the second input of which is the information input device, and the output is connected to the third input of the control unit, the fourth and fifth inputs of which are respectively the synchronization and data inputs of the device, the first control unit output. This is the control output of the device, and the second and third outputs are connected to the second and third inputs of the address fixing block, characterized in that, in order to increase the speed of the device, into it. input a local control unit and a logic unit, the first and third inputs of the local control unit are connected respectively to the installation and synchronization inputs of the device, the second input is the start input of the device, the fourth input is connected to one output of the counter addresses, the fifth input is connected to the second output of the control unit, the outputs of the first and second groups of the local control unit are connected respectively to the inputs of the second group of the address fixing unit multiplexer, the first output is connected to the synchronous input of the address counter, the second output is connected to the sixth input of the control unit, and the third the output is connected to the third B2C1DOM Logic block, the inputs of the first and second groups of which are connected to the outputs of the address fixing block, the first and second inputs are connected respectively to the synchronization inputs and Settings apparatus fourth input coupled to a second vyho-house control unit, and the outputs of the first and second groups are connected to the inputs of first display elements and 0g / s. / phage.