SU1193680A2 - Signature analyzer - Google Patents

Abstract

SIGNATURE ANALYZER on auth.St. No. 962962, in order to increase diagnostic capabilities by fixing all the multiplicity errors, less than eight, while ensuring the possibility of determining the serial numbers of the distorted characters in the case of double error, the second counter, trigger, multiplexer, register and a group of EXCLUSIVE OR elements, with the installation input of the second counter connected to the installation input of the Trigger O and is the analyzer reset input, the counting input of the second counter is connected to the single trigger input and is the control input of the analyzer, the single output of each bit of the second counter is the connection of the corresponding multiplexer address input, the forward trigger output is connected to the multiplexer gating input and the register recording input, the multiplexer output is connected to the third inputs of all elements And groups, each data multiplexer input It is connected with a single output of the corresponding bit of the first counter, the output of each trigger of the group is connected to the first inlet (The corresponding element is EXCLUSIVE OR groups and with the corresponding input of the register data, each output of which is connected to the second input of the corresponding; element EXCLUSIVE SHS, whose outputs are the second group from the information outputs of the analyzer. Od (x

Description

one

The invention relates to instrumentation, can be used in the adjustment, control and diagnostics of digital devices and is an improvement of the device according to the main author. Jf 962962.

The purpose of the invention is to increase the diagnostic capabilities for account of fixing all errors of multiplicity less than eight, while ensuring that it is possible to determine the sequence number of the distorted characters in the case of a double error,.

FIG. 1 shows the structural scheme of the proposed signature analyzer; in fig. 2 is a timing diagram of the signals at the output of the multiplexer for various control cycles at, -1; in fig. 3 is an example of a signature generation process in case errors occur at 7 and 19 clocks.

The error localization process for the case depicted in FIG. 3 is illustrated in table. The signal analyzer (Fig. 1) contains an n-t Bazy binary counter 1, a group of (n + 1) And 2 elements, a group of (n + 1) flip-flops 3, a second (log, n) -digit binary counter 4, trigger 5, multiplexer 6, register 7, group 8 of (n + 1) EXCLUSIVE OR elements, synchronous input 9, first control input 10, first information input 11, second control input 12, setup input 13, group of information inputs 14, the first group of 15 information outlets, the second group of 16 information outlets.

Signature alarm works as follows.

Before the start of operation, the positive impulse- (Reset), which is formed at the input 13 of the analyzer, the trigger 5 and the counter 4 are set to the initial (zero) state. Then, at the analyzer inputs 14, the SQ signature code of the binary sequence X without errors is set to correspond to the initial control cycle, which is written into triggers 3 with the arrival of the positive start pulse analyzer at input 10. This pulse sets the counter (1) to the initial (zero) state. A logic zero signal from the trigger output 93680. 2

the multiplexer 6j, which is fed into the gate, is prevented from passing signals from the data input to the multiplexer output;

5, the third input of all elements AND 2 throughout the entire initial cycle — the control receives a signal of a logical unit.

Binary counter 1 performs:

The sync pulse count is analyzed by MY binary sequence and, thus, assigning the sequence number to each binary symbol of this sequence. Each character

f5 of a sequence, equal to one, opens logical AND 2 elements, permitting the passage of the code corresponding to the sequence number of this character to the accumulating adder

2Q modulo two performed on triggers 3. Thus, after passing the last sync pulse of a sequence, the result of modulo 3 is stored in triggers 3

25 two signatures of the sequence of error-free and signatures of the analyzed sequence, representing the sum modulo two numbers of ticks, in which the symbols of the sequence are distorted, i.e.

V Sox®So2 Sl®Ayi®, ..;, ®A ,.

 h

where K is the multiplicity of errors in the analyzed sequence,

 The end of the analyzed sequence is determined by a positive stop pulse, which arrives at the input 12 of the analyzer from the test object. This signal records

  1 to trigger 5, permitting the passage of signals from the input to the output of multiplexer 6 for all the remaining n control cycles, and rewrites the code from the triggers 3 to register 7. This code is also stored in register 7 for all other n control cycles. In addition, the Stop signal, arriving at the counting input of counter 4, increases the content of the latter by one.

In each of the n subsequent cycles, the control determines the signature for a specific part of the initial sequence Z of the subsequence Z. ZR., Where is the Rademacher function of the i – th order (, 2, ..., n). From the source sequence to get i-x signatures, S is cut3

Only those ticks in which the values of the ix functions are 1, for example, when the signature is formed from characters of the sequence Z located on odd ticks, when - from characters located on even pairs of ticks, when - on the second half of the sequence Z. If at least one pair of signatures S and does not match, then errors are detected even with S (((S is the signature of the corresponding subsequence of the model sequence).

As a generator of Rademacher functions, counter 1 is used (1 in this case represents the digit number of this counter). In each of the n control cycles, to the third input of the And 2 elements, through multiplexer 6, one of the outputs of the counter 1 is connected. the number of which (1) corresponds to the address formed at the output of the counter 4. Counter 4 is incremented by one to the third inputs of the And 2 elements at the moment of the end of the previous monitoring cycle by Pulse Stop.

Thus, before the beginning of the 1st control cycle () signal

The stop content of counter 4 is incremented by one, and the output of the 1st bit of counter 1 is connected to the third inputs of the AND 2 elements through multiplexer 6. Then, the Start signal generated at the input 10 of the analyzer is triggered by the triggers 3

14, the signature S. is recorded, and the counter 1 is reset.

Further (before the arrival of the next stop pulse), the operation proceeds in the same way as at the initial control cycle, however, S- is the sum modulo two not all of the tick numbers, which distort the sequence symbols, but only those that are are given with a single value of R. (for example, when il, numbers of only odd clock distortion are added). So get n signatures

8 „-Siv.The process of forming these signals

The tour is shown in FIG. 2, where the signals at the output of the multiplexer are shown

6 representing. is a function of the Rade Maher for various control cycles with and.

36804

FIG. 3 shows a specific example of the process formed 11 subsequences Z. and X with, -1 and errors in the seventh

5 (00111) and the nineteenth (10011)

tact x, and in the table - the corresponding C1 | gnature. Signatures S. and S, 2 are modulo sums two tick numbers in which the characters

0 sequences X, - and Z are equal to one, a ,,; S, -. equal also to the sum modulo two numbers of cycles of the distorted characters.

If S (, S, ... S ,, 0, de) 5 concludes that there are no errors in the binary sequence Z.

The opposite situation indicates an error. Moreover, if the number of errors in the first or second

20 half of the analyzed sequence, included in, odd, then the n-th and (n + 1) -and triggers 3 are respectively set to one state,

25 Thus, the use of direct and inverse outputs of the higher bit size of counter 1 allows one to control the parity of the binary sequence over its entire

30 in length, which makes it possible to detect all the errors of an odd multiple of j. If one error occurs, then S is the binary number that represents the number of the clock in which this error occurs. If a

35 two errors occur, then SQ is the sum modulo two numbers of cycles on which they occur. And when, after the end of a certain 1st control cycle, the second group has 16 informational outputs as a result of adding modulo two SQ and S- -y code appears that is not equal to zero and not equal to Sp, this code is no.

rum tact of one of the errors. Code number

. At the time of the first group of 15 information outlets, the clock of the time when another error occurs.

50 The detection of all errors of multiplicity, less than eight, is ensured by the fact that the proposed signal analyzer receives not one, but (n + 1) signatures, which represent the signatures of decomposition of the analyzed binary sequence in the Rademacher function system. Moreover, all errors of odd multiplicity are found thanks to parity control, carried out with the help of the n-th and (n + 1) -th trigger group, two-fold errors due to the fact that there are no two different binary vectors, modulo two, which give zero errors of a multiplicity of four and a bit due to the specificity of the system decomposition of the Rademacher functions, which leads to such a distribution of the error between the signatures that are always detected. Determining the addresses of erroneous ticks in the case of a double error is based on the fact that, when decomposing into the Rademacher function system, at least one signature is found, which is the address of one of the errors, and since there are two errors, the address of the second error can be obtained by adding module two of this signature with the signature of the initial control cycle containing both errors. In addition, the number of undetectable error configurations for dl is reduced. Let a controlled sequence contain exactly four errors. those. there is a situation v F © A,. Then, if errors are detected, if o, then the presence of errors is detected by some signature Sjv,, At which at least one bit is equal to one. Since all the vectors A-J-I-A. are different (they are the numbers of the ticks where errors occur), there are at least two bits 1 and J in which all the error vectors are distinguished. These four two-component vectors (up to insignificantly here permutations) in bits 1 and | have the form when decomposed into a system. the Rademacher functions, the corresponding bits 1 and j for signatures have the form Sj (1, j) 0 A ,, (1, j) © 0 A, (1, j) Φ GA (1,3) © 1 Ay (l ,. one); S .... ,, (lo) 0Av, (1о) F1 A ", 2 (® О А, з (1Л®1 Ay4 (lj), that is S. | v, (1, з) А .e (1, g) FA (1.j) () ® (-f) (S; ,, (l, j) A - ,, (l, j) © Aj (lo) () Φ (- | -) (4-). Thus, since there are bits of the private signatures S gy and S -, unequal 0 detects errors of multiplicity 4. When the proof is carried out similarly, if there is one, all signatures S are for an error. S take only two values equal to 0 or, and the state of the nth and (n + 1) -th tons of iggers 3 indicates an odd number of errors, i.e. S is the binary code of the number of the beat on which a single error occurs. The same happens in the event; If the errors are K, but at the same time (K-1) i, the errors are compensated, i.e., A, j, ®A ,, j®, ..., ®A, (,, 0, If at least one of the errors A,) is not compensated for in any of the signatures, this leads to the appearance., -Say and not equal to 0. In the case of a double error, all four signatures can take on four different values, namely: ov vi®® - v A, 2; -0 (moreover, the sum modulo two values of two particular signatures, not. equal to S y, O, must be equal to Spy). The situation analysis and the decision on the presence of one, two or more errors or on their absence is carried out by the operator, these functions can also be performed on a computer, inputting into the information from the output of the triggers 3. 7. With the help of the proposed analyzer, some errors can be localized, multiplicity of not more than n. In particular, this is possible if the codes of the numbers of sequence cycles in which errors occur occur different from one another at least in one bit. 808 The possibility of detecting all multiplicity errors, less than eight and odd multiplicities, as well as determining the location of a single or double error, with the help of the analyzer, significantly reduces the debugging and testing time of complex digital devices and improves their quality.

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Claims (1)

SIGNATURE ANALYZER according to ed. No. 962962, with the fact that, in order to increase diagnostic capabilities by fixing all errors of multiplicity less than eight, while providing the ability to determine the sequence numbers of distorted characters in the event of a double error, it was introduced a second counter, a trigger, a multiplexer, a register and exclusive OR element group, wherein the input usta- Novki _h 0 of the second counter is coupled to the input for setting a G '' Trigg pa and is input to the analyzer reset the count input of the second counter is connected to a single input trigger and I'm in is connected to the control input of the analyzer, the single output of each bit of the second counter is connected, with the corresponding input of the multiplexer address, the direct output of the trigger is connected to the gating input of the multiplexer and the input of the register record, the output of the multiplexer is connected to the third inputs of all elements AND groups, each data input of the multiplexer is connected with a single output of the corresponding discharge of the first counter, the output of each trigger of the group is connected to the first input of the corresponding element EXCLUSIVE OR group and with tvetstvuyuschim input data register, each output of which is coupled to a second input of the respective:, · exclusive-OR element, the outputs of which are the second group of information outputs of the analyzer.