SU1499451A1 - Digital delay line - Google Patents

Abstract

The invention can be used to create a delay line with on-line performance monitoring for systems where the time to detect a malfunction does not have a special meaning, but strict requirements are placed on the size and weight of the equipment. The purpose of the invention is to increase the reliability of the work is achieved by providing operational monitoring of performance. To do this, the device additionally includes four D-triggers, a modulo-two adder, cyclic clock buses, fault indication buses, and new corresponding links. The drawing shows RAM 1, D - triggers 3 - 6, adder 7 modulo two, input bus 8, output bus 9, bus 10 clocks, bus 11 cyclic clock pulses, fault indication bus 12. The ability to indicate faults during continuous operation allows you to quickly draw conclusions about the reliable operation of the device. 1 il.

Description

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The invention relates to radio engineering and can be used as a delay line with on-line performance monitoring in systems where the malfunction detection time is not important, but there are strict requirements for the equipment volume.

The purpose of the invention is to increase the reliability of work by providing operational monitoring of health.

The goal is achieved by incorporating a set of D-flip-flops in a device, a modulo-two adder, cyclic synchronization buses, rudder pulses, a fault indication bus, and new connections.

The drawing shows a block diagram of a digital delay line.

The digital delay line contains a series-connected operative delay of exactly one cycle, i.e. for a time equal to the period of cyclic sync pulses arriving at the bus 11. Simultaneously with the help of the 1D1-block synchronizing pulse, the trigger 5 records the symbol of the input information. Then, in D-flip-flop 6, this symbol is again delayed by the cycle and compared on cn mat 7 with the same symbol, which is delayed in RAM 1 and flip-flop 3. In the case of the correct operation of the particular cell of RAM 1 in which this particular cell is stored. - the input information element does not fix the malfunction, and in case of failure of the signals at the inputs of the adder 7, a malfunction signal is output to the malfunction indication bus 12. Since the period of operation of the counter 2 addresses is different from the period of cyclic clock pulses arriving on the bus 11 for the period of the following clock pulses, post-storage memories of (RAM) 1, fed on the bus 10 following the next 30

D-flip-flops 3 and 4 and a modulo two 7, a counter of 2 addresses connected in series D-flip-flop 5 and D-flip-flop 6, the output of which is connected to the second input of the adder 7 modulo two, while the inputs of the D-flip-flop 5 and RAM 1 are combined and connected to the input bus 8, as well as the output bus 9. The synchronization input of the D-Trigger 3 is connected to the control input Write-read RAM 1, the 10 clock pulse bus and the counter 2 address input, the bit outputs of which are connected with address inputs of RAM 1. The synchronization inputs of D-flip-flops 4-6 are connected to the bus 11 cyclic b low-frequency pulses. The output of the D-flip-flop 3 is connected to the output bus 9, the output of the adder 7 modulo two is connected to the fault indication bus 12.

Digital delay line works as follows.

The input information is recorded sequentially in the RAM cell 1. The time difference between writing and reading from a particular cell is determined by the period of operation of the 2-address counter. The period of operation of counter 2 is chosen one interval less than the required delay, so information 55 from the output of RAM 1 is additionally delayed by a D-trigger by one clock interval. Thus, in RAM 1 and D-flip-flop 3, the required character in D-flip-flop 5 is simultaneously written to the next cell of RAM 1.

Thus, the health of all cells of RAM 1 is monitored sequentially from cycle to cycle, and the time required to monitor the entire volume of RAM 1 is equal to the product of the cycle time and the number of 35 RAM cells used 1. D-flip-flop 4 is used to fix delayed on. cycle element of the input information on the input of the adder 7..

The possibility of indicating faults occurring during the continuous operation of the device allows us to quickly draw conclusions about the reliable operation of the device.

Claims (1)

45 Formula Fig. eteny A digital delay line containing an address counter, a random access memory, whose information input is connected to the line input bus, and a write-read mode control input to a clock bus and an address counter input, whose bit outputs are connected. with the address inputs of the operative memory device, characterized in that, in order to increase the reliability of the operation by ensuring the operative control 50 Dima delay exactly one cycle, i.e. for a time equal to the period of cyclic sync pulses arriving at the bus 11. Simultaneously with the help of the 1D1-block synchronizing pulse, the trigger 5 records the symbol of the input information. Then, in D-flip-flop 6, this symbol is again delayed by the cycle and compared on the motherboard 7 with the same symbol, retained in RAM 1 and flip-flop 3. In the case of proper operation of a particular cell of RAM 1, in which this particular cell is stored, the input information element is faulty is not detected, and in the event of a loss of signals at the inputs of the adder 7, a malfunction signal is outputted to the fault indication bus 12. Since the period of operation of the counter 2 addresses is different from the period of cyclic clock pulses arriving on bus 11 for the period of the following clock pulses, post0  fooled by bus 10, next 5 A digital delay line containing an address counter, a random access memory, whose information input is connected to the line input bus, and a write-read mode control input to a clock bus and an address counter input, whose bit outputs are connected. with the address inputs of the operative memory device, characterized in that, in order to increase the reliability of the operation by ensuring the operative control 0 514994516 operability, entered into it the third synchronization inputs and the third and four-digit D-flip-flop, the modulo-inverter D-flip-flop adder and cyclic bus two, cyclic sync clock pulses, output impulses and the fault indicator bus of the second D-flip-flop is connected to the first the information input of the adder modulo two, the first D-flip-flop is connected to the output of which is connected to the bus indicator of the operative memory of the malfunction, and the second input va, the sync input to the bus of the third D-flip-flop, information-clock pulses, and its output is a Q input of which is connected to from the output pshnoy line and information output of the fourth D-flip-flop, the information input of the second D-flip-flop, the input of which is connected to synchronization which is connected to the line bus line.