SU1242958A1 - Device for checking discrete objects - Google Patents

Abstract

The invention relates to automation and computing and can be used in test diagnostics of discrete objects. The purpose of the invention is to increase the reliability of the control. This is achieved by checking the compliance of the object's response with the control sign, as well as organizing self-control, which allows detecting errors of odd multiplicity resulting from faults in the control object and in the device itself at the control step in which they occurred. The device contains an input unit, a control unit, a memory unit, three switches, an accumulator adder, a modulo two adder, a comparison unit, an error error trigger, a common error trigger, an indication unit, and an OR element. 6 Il. u 4 e

Description

The invention relates to computing, in particular to automated systems for controlling digital devices, and can be used to control digital devices during their production and operation.

The aim of the invention is to expand the field of application of the device and increase the reliability of the control.

The invention consists in expanding the scope of application by providing the possibility of obtaining diagnostic information by recording the reaction of the object in the memory cell where the corresponding test signals are stored without increasing the memory block, and also in increasing the accuracy of the control by checking the appropriateness of the response. object of the control sign and organization of the control itself, which allows detecting errors of odd multiplicity resulting from faults in the control object and in the devices e at that control step in which

they appeared.

I-

FIG. i shows the functional diagram of the device for controlling discrete objects; in fig. 2-4 are functional diagrams of control, input and display units, respectively; in fig. 5 is a timing diagram of the operation of the device; in fig. 6 - the algorithm of the device. The device for monitoring discrete objects (Fig. 1) contains a memory unit, a control unit 2, an input unit 3, an indication unit 4, a register 5, an adder 6, a switch 7, a comparison unit 8, an adder 9 modulo two, an error trigger 10, error trigger 11, first 12 and second 13 groups of elements AND, element OR 14, control object 15, control unit outputs 16-23, address sign output 24, start address sign outputs 25, synchronization sign output 26, device start sign output 27 , test outputs 28, output 29 of the modulo adder, output 30 of the error trigger, g groups of exits 31 and 32 groups of elements And, output 33 of the element OR 33, group of exits 34 of the object of control.

The control unit 2 (Fig. 2) contains the address counter 35, the trigger mode 36 and the start 37, the generator 38 clock

0

five

0

five

0

five

0

five

OUT pulses -, five elements AND 39-43, elements OR 44 and 45, overflow output 46 of the counter 35, outputs 47 and 48 of the clock generator 38.

The input unit 3 (FIG. 3) contains a unit generator 49, a manual mode key 50, keys 51, 1-51 ./1 for setting the initial test address, counter synchronization key 52, key 53 and start, and keys 54.1- 54./g for setting the test suite. When the key is closed, a single signal is received on the key corresponding to this key.

The display unit 4 (Fig. 4) contains the device stop indicators 55, test dial numbers 56.1-56., Mode, Control 57, Receive mode 58, full error 59, output response code 60.1-60, / 71 of the monitored object, odd error 61.

In FIG. 6, there are: CT - counter, T - trigger, M2 - modulo two; M is a combination summator; RG - register; R - the reaction of the object.

Memory unit 1 is designed to receive, store and issue a test sequence and output reactions of the object to be tested. It is a random-access memory device of a static type. Recording: information received at its information D-input is performed at the address received at address input A, by a recording signal received at the input WR. The information recorded in memory block 1 is read: when the corresponding address is fed to the address input . The information on its output is present as long as the corresponding input is sent to the address input: the address address.

The control unit 2 (FIG. 2) is intended to control the operation of the device.

The address counter 35 serves to set the address of the next test of the test sequence and the output response of the monitored object corresponding to this test, as well as to control the mode of operation. The entry of the initial code arriving at its D input from input 25 is made on the falling edge of the km pulse arriving at its C input from input 26. Each pulse received from the output of the elec.

OR 44 to the counting input of the counter 35 of the address, increases its state by one.

The mode trigger 36 is designed to memorize the mode in which the device operates. The establishment of a trigger in a single state is accomplished by a single signal arriving at its S input from the output 46 of the overflow of the address counter 35 ,.

The trigger 37 is designed to control the start of the generator 38 clock pulses, its inclusion occurs on the Start signal, coming to the input 27 of block 2, and off - on a single signal coming from the output of the element OR 45

The generator 38 clock pulses is designed to synchronize the operation of the device. At its outputs 47 and 48, a series of clock pulses are formed. .

Element 39 is designed to control the address counter 35, the pulses from the output 48 of the generator 38 clock pulses arrive at the counting input of the counter 35 of the address only if the inverse input of the element 39 receives the zero signal from the input of control unit 2.

Element 40 is designed to control the synchronization of the register 5. The pulses arriving at its second input from the output 47 of the generator 38 clock pulses pass to the output if a single signal from the single output of the mode trigger 36 arrives at its first input, which corresponds to the Control mode .

Element And 41 is intended to control the gating, timing of the comparison unit 8. A single signal at the output of the AND 41 element appears if a single signal is received at its first input from the overflow output 46 of the address counter 35, and the device is in the Monitoring mode. Then the second input element And 41 receives a single signal with. single output trigger 36 mode.

Element And 42 is designed to control the timing of trigger 10 error. The pulses from the output 48 of the generator 38 clock pulses pass to the output of the element I 42 only if the trigger 36 of the mode is in one state, i.e.

42958

activation of trigger 10 error is possible only in the Control mode.

Element I 43 is designed to control the shutdown of the device. Signal

5 appears at its output if the device is in the Control mode and at the output 46 of the counter 35, a single overflow signal appears. Element. OR 44 is intended for

10 organization of the manual diagnostic mode. At the counting input of the counter 35 address pulses come through the element OR 44 from the output of the element And 39 in automatic mode and from the input 24

(5 in manual mode.

The element OR 45 is designed to control the switching off of the start trigger 37. Start trigger 37 is turned off at a single ry signal with a c-output signal

20 cops And 43 and for a single signal from the input 33 of block 2.

The control unit 2 operates in three modes: two automatic - Reception and Control and one manual - Diagnostics.

In the initial state, the counter 35 of the address and the triggers 36 and 37 are in the state O. The information inputs of the counter 35 of the address arrive

30 starting address (set by the conversion factor) from input 25 of the starting address, which is recorded on it by the front of the clock pulse received from input 26. To

35 to a single signal received from the input 27, the trigger trigger 37 goes into a single state and starts the generator 38 of clock pulses, which begins to form on its

40 outputs 47 and 48 of the tactical series, of the pulses. At the input 29 of the signal receives a zero signal that permits the passage of clock pulses from the output. 48 generator 38 clock pulses

 through the elements. AND 39 and OR 44 to the counting input of the counter 35. The counter begins to count, and at its output the test addresses are received, arriving at the output 20 of block 2. At the output 19 of the block

59 2 clock pulses come from the output 47 of the generator 38. When the address of the last test is generated in the address counter 35, the single signal appears at its output 46, and

55 address 35 chik returns to zero state. The overflow signal from the output 46 of the counter 35 of the address of the mode trigger 36 goes into a single

standing The counting input of the address counter 35 continues to receive clock pulses from the output 48 of the generator 38 clock pulses through the elements AND 39 and OR 44. At the bit outputs of the counter 35 addresses sequentially, test sequence addresses are formed, which arrive at output 20. The output 17 has a single signal , at outputs 16, 18, and 20 — zero, clock outputs from output 47 go to outputs 19 and 21, and output 38 to clock 23 from output of the generator. After the appearance of a single overflow signal at output 46 (the mode trigger 36 is in the single state), it enters through the AND 41 element to the output 22 and through the AND 43 element to the first input of the OR 45 element. The single signal from the elec- tronic output. ment or 45 trigger trigger 37 goes to the zero state and turns off the generator 38 clock pulses.

If an odd error is detected in the Control mode, then a single signal is sent to the inverse input of the AND 39 element from input 29, which prohibits the passage of clock pulses to the counting input of the address counter 35, and the counter remains in its previous state, i.e. at its output, the address of the test is recorded at which the error was detected. A single signal received at the R input of the trigger 37 through the element: ШШ 45 from input 33 transfers it to the zero state and turns off the generator 38 clock pulses.

If necessary, in the Manual Diagnostics mode, the jca 35 count status can be changed. single: pulses arriving at its counting input through the element OR 44.

The input unit 3 (Fig. 3) is intended for inputting test information into the memory unit 1 in the form of test sets and for controlling the control unit 2.

The display unit 4 is designed to monitor the operation mode of the device and display the output reactions of the object being monitored and test sets corresponding to these output reactions in the Diagnostics mode.

Register 5 is for recording, storing, and cyclic

the sum of the output reactions of the controlled object. The information received at the information D input of the register 5 is recorded into it on the falling edge of the clock pulse received at its C input from the output 21 of the control unit 2.

The C-adder 6 is intended for C1 1 of the next B1 of the input reaction of the controlled object with the cyclically sum output reactions obtained in the previous cycle and stored in register 5.

Switch 7 is intended for switching information arriving at the information inputs of memory block 1.

When a single signal arrives at the first control input of the switch 7 from the output 18 of the control unit 2 on. the information inputs of the memory block 1 from the output 28 of the block 3 receives the next test set. When a single signal arrives at the second pack

the equal input of switch 7 from output 17 of control unit 2 to the information: inputs of memory 1 from input 34 of the device receives the next output response of the control object.

Comparison unit 8 is designed to compare the checksum of the output reactions of the controlled object obtained after passing all the test sets and stored in register 5 with the reference checksum stored in memory block 1.

Comparison unit 8 operates according to a logic function.

40

Z Y (X ,: .4-) () + +, o. + (x y n- x „y)

i J,

where x, x ..: “U ,,.

the values of the digits of the control su # 1y stored in register 5; the value of the bits of the reference checksum stored in memory block 1; control signal value.

Thus, on the comparison unit 8, a single signal appears only in the case of a checksum inequality, obtained after the passage of all the test sets and stored. -

Y

The case is in register 5, and the reference checksum, provided that the single input of the comparison unit 8 is received on the etching ui input of the comparison unit 8 from the output 22 of the control unit 2.

Modulo 9 modulo two is intended to check the evenness of the cyclic sum of the output reactions of the object being monitored. It performs the addition modulo two cyclical sums of the output reactions of the monitored object obtained in this cycle and stored in register 5, and the check bit of the parity check coming from the output of field 1.2 of memory 1.

The trigger 10 (odd) error is assigned to register the odd error, it goes into one state when a single signal arrives at its S-input from the output of adder 9 modulo two on the trailing edge of a synchronizing pulse received at its C-input from output 23 - block 2 control. I

The total error trigger 11 is intended to register a common error. It goes into a single state when it arrives at its single signal from the output of the element OR 1A, i.e. switching of trigger II of the total error occurs in, if the trigger 10 of an odd error in the unit state or at the output of the comparator unit 8 appears a single signal corresponding to the inequality of the test and reference sums.

Groups 12 and 13 of the And elements are intended to control the output signals of the memory 1, which are fed to the input of the indication 4 if the total error trigger 11 is in the single state, i.e. if a common error is registered, and the output 32 of the device when the second input of the group of 13 elements And receives a single signal from the output 17 of the control unit 2, i.e. when the device is / it in the Control mode.

The element OR 14 is designed to control the general error trigger 11 and the control unit 2. A single signal at its output appears when the trigger 10 of the odd error is in the single state or on

A single signal appears at the output of comparator block 8.

The device works as follows 5 times.

In the initial state, all the memory elements are in the zero state (the circuit for setting the memory elements to the initial state is conventionally not shown),

The device works in three modes: two automatic Reception and Control and one manual - Diagnostics.

5 Before the device starts operating, the binary code of the starting address (it corresponds to the number of test sets in

0 test sequence), which is recorded in the control unit 2 by the pulse received from the output 26 of the input unit 3.

In receive mode, output 18 blocks

5 ka 2 control there is a single signal, which is fed to the input of the switch 7 and the input of the display unit 4. Indicator 58 indicates that the device is in

0 Receive mode. The first test set from the output 28 of the input unit 3 goes through the switch 7 to the information input of the memory unit 1. The Start signal received from the output

5 27 input units 3, control unit 2 starts operating in the Receive mode.

Using the pulses input to the recording from output 19 of control unit 2, test sets are written to memory block 1 and fed to information input through switch 7 from output 28 of block 3. The address sequence is fed to the address input of memory block 1 from output 20 of the block 2

 management After recording in memory 1 of the last test set, control unit 2 automatically switches to the Monitoring mode. At the output 17, a single signal appears, which is fed to the second input of the group 13 of elements I, to the control input of the switch 7 and the input of the display unit 4. Indicator 57 indicates that the device is working.

- in Control mode. In accordance with the first address arriving at the address input of memory block 1, from its output 1.1 to output 32 of the device

0

0

through the group of 13 elements comes the first test suite. The output response of the control object 15 from the output 34 goes through the switch 7 to the information input of the memory unit 1 and, according to the pulse received from the output of the control unit 2, is recorded in the memory block 1 at the address of the test set to which it corresponds. From the output 34, the output response of the controlled object also enters the first input of the combinational adder 6, where it is summed with the contents of register 5 (the initial state of register 5 is zero) with the resulting amount on the trailing edge of the pulse received at the synchronization input the register 5 from the output 2 of the control unit 2 is written to the register 5, from the output of which it is fed to the input of the adder 9 modulo two. At the other input of the adder 9 J1O, the module two receives a signal of the control for the parity of the output 1.2 of the block 1 of the memory, which together with the contents of the register a 5 is summed modulo two. If an odd error does not occur, then a zero signal is present at the output of sum 9 modulo two, and the cycle of operation of the device is repeated.

If, at this test step, an odd error occurs, then the output of modulator 9 modulo two produces a single signal that goes to the input of the display unit 4, the indicator 61 of which signals the occurrence of an odd error, In addition, the single signal is fed to the input of the control unit 2 and to the S input of the error trigger U. On the leading edge of the pulse arriving at the synchronization input from the output 23 of control unit 2, the error trigger 0 goes to one state. A single signal through the element OR 1 is fed to the input of the control unit 2 and to the S input of the trigger 11 of the total error. The latter goes to the single state, which is indicated by the indicator 59 of the display unit 4. A single signal from the output of the trigger 11 of the general error also goes to the second input of a group of 12 elements AND, and decides to feed the output response of the monitored object to the input of the display unit 4, which is displayed

hO indicators. 1-60./77. The control unit 2, in accordance with the single signals received at its first and second control inputs, stops its operation, and its output 20 contains the address of the test set for which it was detected that there was an incomprehensible error. This address goes to the fourth input of the display unit 4 and is displayed by its indicator 1-1i. 56.1-56. and.

If in the process of testing, odd errors are not detected, then after the testing is completed, a unit control signal is supplied to the control input of the comparison unit 8 from output 22 - control unit 2. Comparison unit 8 compares the reference amount received at its first input from output 1.1 of block 1 of memory with the checksum obtained as a result of testing and arriving at its second input from output of register 5, i

If the reference and check sums are equal, then the zero signal is present at the output of the B block of the comparison, the total error trigger 11 remains in the zero state, the control block 2 automatically stops working, and at its output 16 a single signal appears that goes to the block 4 indications. The indicator 55 signals that the device has stopped, which, together with the absence of signals from error triggers, indicates that the control object is normal.

If etahgon and check sums do not match, then a single signal S appears through the output of the B block of comparison, which through the OR 14 element goes to the second control input of the control block 2 and to the common error J 1, which goes into the single state. A single signal from the trigger output 11 of the common error is fed to the inputs of a group of 12 elements -I and block 4 of the display. The control unit 2, on a signal inputted to its second control input, stops its operation, and a single signal appears at its output 16 In display unit 4, the address of the last test set and its correspondence are displayed; as well as a stop signal and a general error signal.

Thus, the device operates in two automatic modes Reception and Control. four

If, however, an error was detected during the control, as a result of summation, the operator has the opportunity to view the sequence of output reactions of the object being monitored. After each depression of the key 50 of the input unit 3, a single signal is generated at its output 24. According to these signals, control unit 2 generates a sequence of addresses that, from output 20, arrive at the address input of memory block 1. At the output of block 1. memory., There are output reactions of the monitored object, which flow through a group of 12 elements I (since trigger 11 of the total error is in one state) to the input of block A of the display. Thus, in block 4 of the display, after each sweeping of the key 50 of the block 3 of the input, the number (address) of the test set is displayed and the output response of the controlled object corresponding to this test set, i.e. the operator has enough information to localize the fault that occurred.

If an odd error is detected, in the display unit 4 the number of the test set is displayed, during the processing of which an odd error occurred, and the output response of the monitored object corresponding to this test set.

Claims (1)

Invention Formula A device for monitoring discrete objects comprising an input unit, a memory unit, an adder, a register, a comparison unit, a control unit, including a clock pulse generator, the first AND element, a start trigger, a mode trigger, an address counter, and the first OR element, and the outputs of the address counter are connected to the address inputs of the memory unit, the group of outputs of the monitored discrete object is connected to the first group of inputs of the adder, the group of outputs of which is connected to the first group of information inputs of the comparison unit and to the second oh group of inputs of the adder, characterized by the fact that, in order to expand the field of application of the device and increase the reliability 4295812 control, it contains the switch, the first and second groups of AND elements, the display unit, the modulo adder two, the error trigger, the total 5 error trigger, the second S1I element, and the control unit contains the third OR element, the second, the third, the fourth, and the fifth elements And, and the outputs of the sign of the initial address of the input block 0 are connected to the information inputs of the address counter, the synchronization input of which is connected to the output of the synchronization feature of the input block, the output of the sign of the change of the address of which is connected to the first input of the first element OR, o The one of which is connected to the counting input of the address counter, the overflow output of which is connected to the first inputs of the first, second And elements and to the single mode trigger input, the direct output of which is connected to the first inputs of the third and fourth And elements, the second inputs of the first and the second element 5 and, the first control input of the switch, the first inputs of the AND elements of the first group and the first information input of the display unit, the output of the first element AND is connected to the second input 0 of the first element OR, the direct input of the fifth element This AND is connected to the first output of the clock pulse generator and the second input of the fourth element I, the second output of the generator of clock pulses is connected to the second i input of the third element I and the recording input of the memory block, the information inputs of which are connected to the switch outputs, the first the group of informational inputs of which is connected to the group of outputs of the monitored discrete object, the second group of informational inputs of the switch is connected to the group of test outputs of the input unit 5, the output of the sign of the block start operation the input is connected to a single trigger trigger input, the direct output of which is connected to the trigger input of the clock pulse generator; the inverse trigger trigger output is connected to the second information input of the display unit; the output is equal to the comparison unit OR is connected to the first input of the second element OR; which 5 is connected to the single input of the trigger of the total error and the first input of the third element OR, the output of which is connected to the zero input of the trigger trigger, direct The 13i output of the common error trigger is connected to. the third information input of the display unit and the first inputs of elements AND of the second group, the second inputs of which are connected to the outputs of the memory block, the second inputs of elements AND of the first group are connected to the test outputs of the memory block, the second group of information inputs of the comparison block is connected to the codes of the reference field of the memory block ti, the synchronization input of which is connected to the output of the first element AND, the output of the second element AND is connected to the second input of the third element OR, the output of the third element AND is connected to the input of the synchronization register, the output of the fourth element And is connected to the synchronization input of the error trigger, the information input of which is connected to the output of the modulo two adder, from even 58 .14 the vegetative information input of the display unit and the inverted input of the fifth element I, the inverse output of the mode trigger are connected to the fifth information input of the display unit and the second control input of the switch, the outputs of the And elements of the first group are connected to the information inputs of the monitored discrete object, moves of elements And of the second group are connected to the first group of information inputs of the display unit, the second group of information inputs of which are connected to bit outputs the address counter, the direct output of the error trigger is connected to the second input of the second element OR, the output of the parity check feature of the memory unit is connected to the synchronization input cyif mator modulo two. 2 It fig.Z Start )